CN107247269A - For the detection device of acquisition process laser signal, pixel cell and array - Google Patents
For the detection device of acquisition process laser signal, pixel cell and array Download PDFInfo
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- CN107247269A CN107247269A CN201710435596.1A CN201710435596A CN107247269A CN 107247269 A CN107247269 A CN 107247269A CN 201710435596 A CN201710435596 A CN 201710435596A CN 107247269 A CN107247269 A CN 107247269A
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S17/00—Systems using the reflection or reradiation of electromagnetic waves other than radio waves, e.g. lidar systems
- G01S17/02—Systems using the reflection of electromagnetic waves other than radio waves
- G01S17/06—Systems determining position data of a target
- G01S17/08—Systems determining position data of a target for measuring distance only
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
Abstract
For solve the measurement of existing laser radar range system not enough precisely, sweep speed is slow, the low problem of image spatial resolution, the invention provides a kind of detection device, pixel cell and array for acquisition process laser signal.Each pixel cell includes photodiode and the sample circuit for being connected and being integrated in one with photodiode negative pole end；Each pixel cell in pixel unit array is to that should have complete reading circuit, during work, and each pixel cell carries out data conversion simultaneously, and the mode detected relative to traditional single-point drastically increases the sweep speed of LDMS；Each photodiode of pixel unit array is by the different spatial field of view angle of camera lens correspondence, and image spatial resolution is high.
Description
Technical field
The invention belongs to technical field of laser detection, and in particular to a kind of detection for acquisition process laser signal is filled
Put, pixel cell and pixel unit array.
Background technology
With the development of laser technology, embedded technology and integrated optics, laser ranging just towards digitlization, automation,
Low cost, the direction of miniaturization are developed.Range laser radar has precision high, and system bulk is small, measures rapid advantage, has
It is widely applied prospect.
How accurately target location is obtained during laser radar range, and this has very for improving image resolution ratio
Important effect, especially for the target vehicle constantly moved, because vehicle interior has electromagnetic interference, easily causes measurement not
Enough accurate the problem of.
In addition, traditional mobile lidar detector majority uses single-spot testing mode, it needs to configure mechanical scanning
Device, sweep speed is slow, and image spatial resolution is low.Need to select focal plane array detector to improve sweep speed,
But it is due to that the existing focal plane array detector chip package process overwhelming majority is by detector array and reading circuit array
It is separated into two layers, detector array is placed in chip bottom, its last layer is the A/D converter and amplifying circuit of reading circuit,
Diode will first pass through the line layer of the reading circuit on diode upper strata when receiving optical signal, during due to light projection to line layer
Easily occur light reflection and cause light loss, reduce the light income of diode.
The content of the invention
Based on background above, for solve existing laser radar range system measurement not enough precisely, sweep speed is slow, image
The low problem of spatial resolution, the invention provides a kind of detection device, pixel cell and battle array for acquisition process laser signal
Row.
The adopted technical solution is that：
Pixel cell for gathering laser signal, it is characterized in that：Including photodiode and with the pole of photoelectricity two
The sample circuit that pipe negative pole end is connected and is integrated in one；
The sample circuit includes NMOS tube NM7, switch S1, S2, S3, S4, S5, S6, electric capacity C1, C2；Switch S1~S4
Constituted by a NMOS tube and a PMOS docking, switch S5~S6 is constituted by a PMOS；Switch S1~S4's
NMOS tube is designated as NM1, NM2, NM3 and NM4 respectively, and switch S1~S4 PMOS is designated as PM1, PM2, PM3 and PM4, opened respectively
The PMOS for closing S5~S6 is designated as PM5 and PM6 respectively；
The source electrode that NM7 grid meets clamp voltage Vb, NM7 connects the negative pole end of photodiode, NM7 drain electrode simultaneously with
NM1, NM2 drain electrode and PM1, PM2 drain electrode are connected；NM1 and PM1 source electrode meets electric capacity C1 one end, NM2 and PM2 simultaneously
Source electrode connect electric capacity C2 one end simultaneously；Electric capacity C1 and electric capacity the C2 other end are grounded respectively；
NM1 and PM1 source electrode also connects PM5, PM3 and NM3 drain electrode simultaneously；PM5 source electrode meets reset power Vdd；PM5's
Grid meets resetting voltage Vrst；One of output end vo ut1 that PM3 and NM3 source electrode connects as sample circuit；
NM2 and PM2 source electrode also connects PM6, PM4 and NM4 drain electrode simultaneously；PM6 source electrode meets reset power Vdd；PM6's
Grid meets resetting voltage Vrst；Another output end vo ut2 that PM4 and NM4 source electrode connects as sample circuit.
Present invention also offers a kind of pixel unit array for being used to gather laser signal, it is characterized in that：Including
Pixel cell described in multiple claims 1；All pixels unit is separate to be set and the different spatial field of view angle of correspondence.
Further, all pixels unit is integrated on substrate；The bottom of the substrate is provided with saturating by multiple Fresnels
The microlens array that mirror is constituted；One pixel cell of each Fresnel Lenses correspondence, for transmiting echo-signal light and making echo
Flashlight is converged on the photodiode of respective pixel unit.
It is used to gathering and handle the detection device of laser signal invention also provides a kind of, including detector array,
Signal acquisition process unit, substrate, interconnection metal, metal wiring layer, sequential control circuit and the row for generating row selects signal
Modeling block；It is characterized in that：
Light of the detector array by multiple independent, the spatial field of view angle that correspondence is different settings over the substrate
Electric diode is constituted；
The signal acquisition process unit includes sample circuit and by row differential amplifier circuit, A/D change-over circuits and data
The process circuit that output module is constituted；Data outputting module includes the column selection module for being used to generate column selection signal；
Sample circuit is corresponded with the photodiode, and each sample circuit is negative with corresponding photodiode
Extremely it is connected and is integrated in and is integrally formed a pixel cell；All pixels unit constitutes a pixel unit array；
Pixel unit array and process circuit are integrated over the substrate, and pixel unit array is by interconnecting metal and metal
Wiring layer is connected, and metal wiring layer is connected by data column line with process circuit；
The quantity of row differential amplifier circuit is equal to the columns of pixel unit array, and a row differential amplifier circuit correspondence one is arranged
Pixel cell；The output end of all sample circuits of each row pixel cell is put with the row difference corresponding to the row pixel cell
The input of big circuit is connected；Input of the output end of all row differential amplifier circuits with the A/D change-over circuits is connected；
The output end of A/D change-over circuits is connected with the input of the data outputting module；A/D change-over circuits are used for will row
The voltage difference si of differential amplifier circuit output is converted to data signal；Sequential control circuit is used to control the row modeling block
With column selection module work；Data outputting module, which is used to export, passes through photoelectricity determined by the row modeling block and column selection module
Being used for corresponding to diode calculates the data signal of phase；
The sample circuit includes NMOS tube NM7, switch S1, S2, S3, S4, S5, S6, electric capacity C1, C2；Switch S1~S4
Constituted by a NMOS tube and a PMOS docking, switch S5~S6 is constituted by a PMOS；Switch S1~S4's
NMOS tube is designated as NM1, NM2, NM3 and NM4 respectively, and switch S1~S4 PMOS is designated as PM1, PM2, PM3 and PM4, opened respectively
The PMOS for closing S5~S6 is designated as PM5 and PM6 respectively；
The source electrode that NM7 grid meets clamp voltage Vb, NM7 connects the negative pole end of photodiode, NM7 drain electrode simultaneously with
NM1, NM2 drain electrode and PM1, PM2 drain electrode are connected；NM1 and PM1 source electrode meets electric capacity C1 one end, NM2 and PM2 simultaneously
Source electrode connect electric capacity C2 one end simultaneously；Electric capacity C1 and electric capacity the C2 other end are grounded respectively；
NM1 and PM1 source electrode also connects PM5, PM3 and NM3 drain electrode simultaneously；PM5 source electrode meets reset power Vdd；PM5's
Grid meets resetting voltage Vrst；One of output end vo ut1 that PM3 and NM3 source electrode connects as sample circuit；NM2 and
PM2 source electrode also connects PM6, PM4 and NM4 drain electrode simultaneously；PM6 source electrode meets reset power Vdd；PM6 grid connects reset electricity
Press Vrst；Another output end vo ut2 that PM4 and NM4 source electrode connects as sample circuit；
Output end vo ut1 and Vout2 connect two inputs of row differential amplifier circuit respectively.
Further, above-mentioned A/D change-over circuits include ramp generating circuit and multiple comparators, and the quantity of comparator is equal to
The columns of pixel unit array, a comparator one row pixel cell of correspondence；The waveform signal output end of ramp generating circuit with
One of input of each comparator is connected, the voltage signal that all sample circuits of each row pixel cell are exported
Another input of the comparator corresponding to the row pixel cell, all ratios are sent into by corresponding row differential amplifier circuit
Output end compared with device connects the input of data outputting module；
Ramp generating circuit includes load resistance R, integrating capacitor C and operational amplifier；A load resistance R termination voltage
Vin1, load resistance the R other end connect the reverse input end of operational amplifier and integrating capacitor C one end, integrating capacitor C simultaneously
Another termination operational amplifier output end Vramp, integrating capacitor C two ends are also parallel with reset switch RST, operation amplifier
The input termination voltage Vin2 in the same direction of device；Voltage Vin1, Vin2 are used to control the ramp signal produced by ramp generating circuit, its
The bleeder circuit of middle voltage Vin1, Vin2 in detection device is produced；
Data outputting module also includes Nbit counters, output buffer module and multiple memories；Multiple memories it is defeated
Enter end respectively with the output end one-to-one corresponding of the multiple comparator to be connected, Nbit counters and the column selection module are sent respectively
Control signal gives the control end of the multiple memory, the data output end of the multiple memory by data/address bus with it is defeated
The input for going out buffer module is connected, and the data signal for calculating phase is exported by the output end of output buffer module.
Further, the bottom of above-mentioned substrate is provided with the microlens array being made up of multiple Fresnel Lenses；It is each luxuriant and rich with fragrance
Nie Er lens one pixel cell of correspondence, for transmiting echo-signal light and making echo-signal light converge to respective pixel unit
On photodiode.
The present invention has advantages below compared with prior art：
1st, acquisition precision height of the present invention, noise filtering ability are good, strong antijamming capability, applied to energy in LDMS
Enough improve the measurement accuracy and antijamming capability of system.
2nd, the present invention carries out each picture in face battle array detection, pixel unit array using pixel unit array to echo-signal
Plain unit is to that should have complete reading circuit, during work, and each pixel cell carries out data conversion simultaneously, single relative to traditional
The mode of point detection, drastically increases the sweep speed of LDMS.
3rd, each photodiode of pixel unit array is by the different spatial field of view angle of camera lens correspondence, image space point
Resolution is high.
4th, each photodiode and sample circuit in pixel unit array are integrated in one, and circuit is simple, to signal
Processing realized in the chip of a small size.
5th, detection device is designed using back-illuminated type, and its metal wiring layer is arranged on the bottom of photodiode, the pole of photoelectricity two
Pipe can be contacted directly with transparent surface, reduce the loss of intermediate link light, and be effectively reduced chip thickness.
6th, the substrate bottom of detection device is provided with microlens array, and one lenticule of each photodiode correspondence more has
Effect converges in echo-signal light on corresponding photodiode, reduces light interference unnecessary between photodiode.
7th, using the present invention detection device LDMS, it is to avoid LDMS is to mechanical scanner
Dependence, while improving the reliability of system.
Brief description of the drawings
Fig. 1 is the overall structure diagram of detection device；
Fig. 2 is the circuit composition schematic diagram of signal acquisition process unit in detection device；
Fig. 3 is the composition structural representation of detection device；
Fig. 4 is the side cutaway view of detection device；
Fig. 5 is the reading circuit and its output interface overall system architecture schematic diagram of detection device；
Fig. 6 exports wiring diagram for the pixel of detection device；
Fig. 7 is the overall theory diagram of detection device；
Fig. 8 is the schematic diagram of ramp generating circuit in detection device；
Fig. 9 is the schematic diagram of sample circuit in detection device；
Figure 10 exports schematic diagram for the one-dimensional row gating module of detection device；
Figure 11 exports schematic diagram for the two-dimentional row/column gating module of detection device；
Figure 12 is the SECO figure of detection device；
Figure 13 enables gating switch logical schematic for the addressed row of detection device；
Figure 14 enables gating switch logical schematic for the addressed column of detection device；
Description of symbols in the figures above：
101- microlens arrays, 102- substrates, 103- device active regions (epitaxial layer), 104- metal wiring layers, 105- is mutual
Connect metal, 106- pixel unit arrays, 1061- photodiodes, 107- data column lines, 108- data/address bus, 109- rows gating
Address wire, 110- sample circuits, 112- process circuits, 1121- row differential amplifier circuits；1122-A/D change-over circuits；1123- numbers
According to output module, 122,124-N type doped layers, 125-P type doped layers, 126- cathode electrodes, 127- anode electrodes, 128-SiO2
Separation layer.
Embodiment
The present invention is elaborated below in conjunction with the accompanying drawings.
Detection device provided by the present invention for acquisition process laser signal is mainly adopted by detector array and signal
Collect processing unit to constitute.
It is used for the output signal for receiving and handling detector array, including sampling electricity referring to Fig. 2 signal acquisition process unit
Road 110 and the process circuit being made up of row differential amplifier circuit 1121, A/D change-over circuits 1122 and data outputting module 1123
112；Sample circuit 110, row differential amplifier circuit 1121, A/D change-over circuits 1122 and data outputting module 1123 connect successively；
Sample circuit 110 is used to complete the collection to picture element signal and charge accumulated, is then exported with two-way voltage signal and gives row difference
Amplifying circuit 1121, the difference signal that row differential amplifier circuit 1121 is obtained is transferred to A/D change-over circuits 1122, passes through A/D
Change-over circuit 1122 is converted to analog signalses the data signal for calculating phase, and the data signal is defeated eventually through data
Go out module 1123 and transmit the primary processor to outside detection device；
Referring to Fig. 3, detector array is made up of multiple independent photodiodes 1061 for being used to gather laser signal；Light
Electric diode 1061 is arranged on substrate 302 (material is Si), is distributed in the device between substrate 102 and metal wiring layer 104
Active area (epitaxial layer) 103；
Referring to Fig. 6 and Fig. 7, the negative pole end of each photodiode 1061 is respectively connected with a sampling electricity in detector array
Road 110 is simultaneously integrated in being integrally formed a pixel cell；All pixels unit constitutes a pixel unit array 106；Place
Circuit 112 is managed as the reading circuit of pixel unit array；
Referring to Fig. 1 and Fig. 3, detection device also includes substrate 102, (the interconnection metal is used for interconnection metal 105 as contact
Realize the connection of device and Si substrates), metal wiring layer 104, sequential control circuit and the row modeling for generating row selects signal
Block；Pixel unit array 106, process circuit 112, sequential control circuit and row modeling block it is integrated on the substrate 102, pixel list
Element array 106 is connected by interconnecting metal 105 with metal wiring layer 104, and metal wiring layer 104 passes through data column line 107 and place
Circuit 112 is managed to be connected；
Referring to Fig. 1 and Fig. 3, metal wiring layer 104 is made up of multiple metal line units, each row metal line unit point
Dui Ying not a row pixel cell；Each metal line unit is made up of more metal layers and multilayer dielectricity layer, in every layer of metal
Tie point is equipped with layer, multilayer dielectricity layer is separately positioned between adjacent two layers metal level, and dielectric layer is SiO2Material it is exhausted
Edge layer；
Referring to Fig. 3, the bottom of substrate 102 is additionally provided with the microlens array being integrated in one with substrate 102, microlens array
It is made up of multiple Fresnel Lenses, one pixel cell of each Fresnel Lenses correspondence, for transmiting echo-signal light and making back
Ripple flashlight is converged on the photodiode 1061 of respective pixel unit, is conducive to photodiode 1061 to absorb optical signal,
The microlens array effectively increases substrate surface transmissivity.
Referring to Fig. 4, the top of substrate 102 is provided with SiO2Separation layer 128, in SiO2Separation layer 128 is used to embed provided with multiple
It is more than at the hole of cathode electrode 126 and anode electrode 127, the contact surface that cathode electrode 126 is inlaid into substrate 102 provided with area
The n-type doping layer 124 of the sectional area of cathode electrode 126, anode electrode 127, which is inlaid at the contact surface in substrate 102, is provided with area
More than the p-type doped layer 125 of the sectional area of anode electrode 127.The bottom of substrate 102 has n-type doping layer 122, and microlens array is set
Put in the bottom of n-type doping layer 122.
Sample circuit
Referring to Fig. 6 and Fig. 7, sample circuit 110 has multiple, and it is corresponded with photodiode 1061, each photoelectricity two
The negative pole end of pole pipe 1061 is respectively connected with a sample circuit 110 and is integrated in one.
Referring to Fig. 9, sample circuit 110 includes NMOS tube NM7, switch S1, S2, S3, S4, S5, S6 and electric capacity C1, C2；Open
Close S1~S4 to constitute by a NMOS tube and a PMOS docking, switch S5~S6 is constituted by a PMOS；Switch
S1~S4 NMOS tube is designated as NM1, NM2, NM3 and NM4 respectively, and switch S1~S4 PMOS is designated as PM1, PM2, PM3 respectively
And PM4, switch S5~S6 PMOS be designated as PM5 and PM6 respectively；
NM7 source electrode connects the negative pole end of photodiode, NM7 drain electrode and PM1, PM2 for draining simultaneously with NM1, NM2
Drain electrode be connected, NM7 grid meets clamp voltage Vb；NM1 and PM1 source electrode connects electric capacity C1 one end simultaneously, NM2 and PM2's
Source electrode connects electric capacity C2 one end simultaneously；Electric capacity C1 and electric capacity the C2 other end are grounded respectively；
NM1 and PM1 source electrode also connects PM5, PM3 and NM3 drain electrode simultaneously；NM1 and PM1 grid connects control signal respectively
Vs1 and Vs2；PM5 source electrode meets reset power Vdd；PM5 grid meets resetting voltage Vrst；PM3 and NM3 source electrode connects work
For one of output end vo ut1 of sample circuit；PM3 and NM3 grid meets control signal Vs3 and Vs4 respectively；
NM2 and PM2 source electrode also connects PM6, PM4 and NM4 drain electrode simultaneously；NM2 and PM2 grid connects control signal respectively
Vs2 and Vs1；PM6 source electrode meets reset power Vdd；PM6 grid meets resetting voltage Vrst；PM4 and NM4 source electrode connects work
For another output end vo ut2 of sample circuit；PM4 and NM4 grid meets control signal Vs3 and Vs4 respectively；
Control signal Vs1 is the modulated signal that the primary processor outside detection device is sent, and control signal Vs2 is adjusted by described
Signal processed, which is negated, to be obtained；
NM7 is clamp circuit, during for voltage change on electric capacity C1, C2, it is to avoid photodiode both end voltage is sent out
Raw big change；
Output end vo ut1 and Vout2 connect the input in the same direction and reverse input end of row differential amplifier circuit 1121 respectively.
The operation principle of sample circuit shown in Fig. 9：
The NMOS tube NM7 being connected with photodiode plays clamping action, and Vb is clamp voltage.
Electric capacity C1, C2 are integrating capacitor in pixel, and switch S1, S2 effect are integral processes in control pixel, switch S1
NMOS tube NM1, switch S2 PMOS PM2 control signal Vs1 and switch S1 PMOS PM1, switch S2 NMOS tube
NM2 control signal Vs2 is the control signal of row modeling block output, Vs1 and Vs2 voltages are opposite；Vs1 be set to high Vs2 be set to it is low,
Then S1 closes S2 and disconnected；Vs1 is set to low Vs2 and is set to height, then S1 disconnects S2 closures.
Switch S3, S4 effect be control pixel in integral voltage output, S3, S4 is respectively by a pair of PMOS and NMOS tube pair
Connect and form, the control signal Vs4 for switching S4 PMOS PM4 control signal Vs3 and switch S3 NMOS tube NM3 is row modeling
The row gating signal of block output, Vs3 is set to high Vs4 and set low, and can disconnect S3 and S4, and Vs3 is set to height by Vs4 is set low, can made
S3 and S4 closures.
Switch S5, S6 effect are the resets for controlling electric capacity in pixel, and the Vrst signals of its control end come from row modeling
Block, Vrst is set to height, can disconnect S5 and S6, and Vrst is set low, and can close S5 and S6.
The course of work of sample circuit shown in Fig. 9
In Figure 12, upper figure represents signal cycle of certain a line per frame back and forth, and figure below represents that frame in a line signal is specific
Situation of change, unlike signal controls the keying of different switches, adopted with reference to the working condition explanation of Fig. 9 and 12 and switch
The course of work of sample circuit：
Step one：Switch S3, S4, S5 and S6 are disconnected, switch S1 and S2 is alternately closed according to control signal Vs1 and Vs2, outside
Portion's light source is according to modulated signal transmitting modulation light, and control signal Vs1 is identical with modulated signal, control signal Vs2 just with modulation
Signal is on the contrary, the electric charge that echo is produced is stored in electric capacity C1 and electric capacity C2.
Step 2：Switch S1 and S2 is disconnected, S5 and S6 still remain off, by row selects signal closure switch S3 and
S4, electric capacity C1 and C2 voltage are transported on two alignments Vout1 and Vout2, is transferred in row differential amplifier circuit, obtains
The difference of voltage on electric capacity C1 and C2, then voltage difference si is transferred in A/D change-over circuits, convert analog signals into numeral
Signal, is transferred to outside detection device eventually through data outputting module.
In this step, electric capacity C1 voltage is A1∫ m (t) m (t-Td) dt, electric capacity C2 voltage is A1∫[1-m(t)]m
(t-Td) dt, A is exported after differential amplifier circuit is handled2∫ [2m (t) -1] m (t-Td) dt=A3·(Tc-Td)；Its
In, A1、A2And A3It is coefficient, and is definite value in the case where the time is approximately constant.
Step 3：After the end of transmission, closure switch S5, S6 disconnect switch S3, S4, and switch S1, S2 are still within disconnecting shape
State, complete paired data alignment and electric capacity C1 and C2 are resetted.
Step 4：Switch S3, S4, S5 and S6 are disconnected, switch S1 and S2, light are alternately closed according to control signal Vs1 and Vs2
Source postpones a chip lengths according to modulated signal transmitting modulation light, control signal Vs1 than modulated signal, and control signal Vs2 is just
Good and control signal Vs1 is on the contrary, the electric charge that echo-signal is produced is stored in electric capacity C1, C2.
Step 5：Switch S1 and S2 is disconnected, S5 and S6 are remained off, and pass through row selects signal closure switch S3
And S4, electric capacity C1 and C2 voltage are transported on two output end vos ut1 and Vout2, are transferred in row differential amplifier circuit
The difference of the upper voltage of electric capacity C1, C2 is obtained, then voltage difference si is transferred in A/D change-over circuits, analog signal is changed
For data signal, it is transferred to eventually through data outputting module outside detection device, after the end of transmission, closure switch S5 and S6,
Electric capacity in pixel cell is resetted.
In this step, electric capacity C1 voltage is A1∫ m (t-Tc) m (t-Td) dt, electric capacity C2 voltage is A1∫[1-m(t-
Tc)] m (t-Td) dt, A is exported after differential amplifier circuit is handled2∫ [2m (t-Tc) -1] m (t-Td) dt=A3·Td。
Step 6：Closure switch S1, S2, S5, S6, disconnect switch S3, S4, photodiode and electric capacity C1, C2 are entered
Row resets.
Step 2 and two data (A of step 5 output3And A (Tc-Td)3Td) it is used to send into outside detection device
Calculated to obtain range information in primary processor.
Obtain range information circular be：By A3And A (Tc-Td)3Td makees ratio in FPGA, obtainsTd is can obtain in the case of known Tc；And due toD is object to be measured to detector
The distance of array, c is the light velocity, can be obtained apart from D.
It is related to m in C1 and C2 magnitude of voltage, parameter in above-mentioned steps two and step 5 and refers to m-sequence, Tc refers to one
The time of small-pulse effect, the time span of chip；Td is the time delay returned.
Row differential amplifier circuit
Referring to Fig. 7, the quantity of row differential amplifier circuit 1121 is equal to the columns of pixel unit array, a row differential amplification
Circuit one row pixel cell of correspondence；The output end of all sample circuits of each row pixel cell is right with the row pixel cell institute
The input for the row differential amplifier circuit answered is connected；The output end of all row differential amplifier circuits with A/D change-over circuits 1122
Input be connected.
A/D change-over circuits
Referring to Fig. 7, A/D change-over circuits 1122 include ramp generating circuit and multiple comparators, and the quantity of comparator is equal to
The columns of photodiode 1061, a comparator one row photodiode of correspondence；The waveform signal output of ramp generating circuit
End is connected with one of input of each comparator, the row differential amplification electricity corresponding to each row photodiode 1061
The output end on road 1121 is connected with another input of each comparator, and the output end of all comparators connects data output
The input of module.
Referring to Fig. 8, ramp generating circuit includes load resistance R, integrating capacitor C and operational amplifier；The one of load resistance R
Termination voltage Vin1, load resistance the R other end connect the reverse input end of operational amplifier and integrating capacitor C positive pole simultaneously,
Integrating capacitor C negative pole meets the output end Vramp of operational amplifier, and integrating capacitor C two ends are also parallel with reset switch RST,
The input termination voltage Vin2 in the same direction of operational amplifier；Voltage Vin1, Vin2 are oblique produced by for controlling ramp generating circuit
The bleeder circuit of ripple signal, wherein voltage Vin1, Vin2 in detection device is produced.
Data outputting module
Referring to Fig. 7, data outputting module 1123 includes Nbit counters, column selection module, output buffer module and multiple deposited
Reservoir；The input of multiple memories is corresponded with the output end of multiple comparators in A/D change-over circuits to be connected, Nbit meters
Number device and column selection module send control end of the control signal to all memories respectively, and the data output end of all memories leads to
Cross data/address bus and be connected with exporting the input of buffer module, exported and believed for calculating the numeral of phase by output buffer module
Number.
Sequential control circuit
Sequential control circuit is used to control the column selection module work in row modeling block and the data outputting module in detection device
Make, sequential control circuit can use existing module.
As shown in figure 13, the row modeling block of detection device enters row decoding by the output to linage-counter, can be gone
Signal is selected, cycle phase of the enable time respectively with row clock signal is same；Wherein Row_clk is row clock signal, 1 in Figure 13,2 points
Biao Shi not row gating switch control signal, Q<1>To Q<n>The output data of 1bit counters, NQ are represented respectively<1>To NQ<n>
Represent the output data of Nbit counters.
As shown in figure 14, the column selection module of detection device enters row decoding by the output to column counter, can be arranged
Signal is selected, cycle phase of the enable time respectively with column clock signal is same；Wherein Col_clk is column clock signal, 1 in Figure 14,2 points
Biao Shi not row gating switch control signal, Q<1>To Q<n>The output data of 1bit counters, NQ are represented respectively<1>To NQ<n>
Represent the output data of Nbit counters.
The operation principle of detection device：
As shown in fig. 6, each pixel cell is respectively provided with the row gating address wire 109 being connected with row modeling block, row gating
Address wire 109 is connected to control respectively the switch S1-S6 and reset power Vdd of the sample circuit of each pixel cell, its
Middle switch S1 and S2, to signal, switchs S3 and S4 by Vs3 and Vs4 to signal, wherein switch S5, S6 and reset electricity by Vs1 and Vs2
Source Vdd is to signal by Vrst；Each row pixel cell shares two single data alignments 107, and the output end of data column line 107 is successively
Connect row differential amplifier circuit, A/D change-over circuits and data outputting module；After the integration of sample circuit 110 terminates, A/D conversion electricity
Ramp generating circuit in road is started working, and the row selects signal provided by row modeling block is selected in certain one-row pixels unit
The data read-out of sample circuit；
The output of the differential signal and ramp generating circuit of the corresponding row differential amplifier circuit output of each row pixel cell
Signal is respectively fed to two inputs of the comparator corresponding to each row pixel cell, after the output end upset of comparator,
The count value of current Nbit counters is left in the corresponding memory of the comparator；
After ramp generating circuit work cut-off, the column selection signal provided by the column selection module in data outputting module, control
Data in memory processed are successively read on data/address bus, then by the output buffer module in data outputting module by number
According to reading into outside detection device.
Claims (6)
1. the pixel cell for gathering laser signal, it is characterised in that：Including photodiode and with photodiode negative pole
The sample circuit that end is connected and is integrated in one；
The sample circuit includes NMOS tube NM7, switch S1, S2, S3, S4, S5, S6, electric capacity C1, C2；Switch S1~S4 by
One NMOS tube and a PMOS docking are constituted, and switch S5~S6 is constituted by a PMOS；Switch S1~S4 NMOS
Pipe is designated as NM1, NM2, NM3 and NM4 respectively, and switch S1~S4 PMOS is designated as PM1, PM2, PM3 and PM4, switchs S5 respectively
~S6 PMOS is designated as PM5 and PM6 respectively；
The source electrode that NM7 grid meets clamp voltage Vb, NM7 connects the negative pole end of photodiode, NM7 drain electrode simultaneously with NM1,
NM2 drain electrode and PM1, PM2 drain electrode are connected；NM1 and PM1 source electrode connects the source of electric capacity C1 one end, NM2 and PM2 simultaneously
Pole connects electric capacity C2 one end simultaneously；Electric capacity C1 and electric capacity the C2 other end are grounded respectively；
NM1 and PM1 source electrode also connects PM5, PM3 and NM3 drain electrode simultaneously；PM5 source electrode meets reset power Vdd；PM5 grid
Meet resetting voltage Vrst；One of output end vo ut1 that PM3 and NM3 source electrode connects as sample circuit；
NM2 and PM2 source electrode also connects PM6, PM4 and NM4 drain electrode simultaneously；PM6 source electrode meets reset power Vdd；PM6 grid
Meet resetting voltage Vrst；Another output end vo ut2 that PM4 and NM4 source electrode connects as sample circuit.
2. the pixel unit array for gathering laser signal, it is characterised in that：Including the pixel list described in multiple claims 1
Member；All pixels unit is separate to be set and the different spatial field of view angle of correspondence.
3. the pixel unit array according to claim 2 for being used to gather laser signal, it is characterised in that：All pixels list
Member is integrated on substrate；The bottom of the substrate is provided with the microlens array being made up of multiple Fresnel Lenses；Each phenanthrene alunite
Your lens one pixel cell of correspondence, for transmiting echo-signal light and making echo-signal light converge to the light of respective pixel unit
On electric diode.
4. for gathering and handling the detection device of laser signal, including detector array, signal acquisition process unit, substrate,
Interconnect metal, metal wiring layer, sequential control circuit and the row modeling block for generating row selects signal；It is characterized in that：
Photoelectricity two of the detector array by multiple independent, the spatial field of view angle that correspondence is different settings over the substrate
Pole pipe is constituted；
The signal acquisition process unit includes sample circuit and by row differential amplifier circuit, A/D change-over circuits and data output
The process circuit of module composition；Data outputting module includes the column selection module for being used to generate column selection signal；
Sample circuit and the photodiode are corresponded, the negative pole end of each sample circuit and corresponding photodiode
It is connected and is integrated in and is integrally formed a pixel cell；All pixels unit constitutes a pixel unit array；
Pixel unit array and process circuit are integrated over the substrate, and pixel unit array is by interconnecting metal and metal line
Layer is connected, and metal wiring layer is connected by data column line with process circuit；
The quantity of row differential amplifier circuit is equal to the columns of pixel unit array, a row differential amplifier circuit one row pixel of correspondence
Unit；The output end of all sample circuits of each row pixel cell with corresponding to the row pixel cell row differential amplification electricity
The input on road is connected；Input of the output end of all row differential amplifier circuits with the A/D change-over circuits is connected；
The output end of A/D change-over circuits is connected with the input of the data outputting module；A/D change-over circuits are used for row difference
The voltage difference si of amplifying circuit output is converted to data signal；Sequential control circuit is used to control the row modeling block and institute
State the work of column selection module；Data outputting module, which is used to export, passes through the pole of photoelectricity two determined by the row modeling block and column selection module
The corresponding data signal for being used to calculate phase of pipe；
The sample circuit includes NMOS tube NM7, switch S1, S2, S3, S4, S5, S6, electric capacity C1, C2；Switch S1~S4 by
One NMOS tube and a PMOS docking are constituted, and switch S5~S6 is constituted by a PMOS；Switch S1~S4 NMOS
Pipe is designated as NM1, NM2, NM3 and NM4 respectively, and switch S1~S4 PMOS is designated as PM1, PM2, PM3 and PM4, switchs S5 respectively
~S6 PMOS is designated as PM5 and PM6 respectively；
The source electrode that NM7 grid meets clamp voltage Vb, NM7 connects the negative pole end of photodiode, NM7 drain electrode simultaneously with NM1,
NM2 drain electrode and PM1, PM2 drain electrode are connected；NM1 and PM1 source electrode connects the source of electric capacity C1 one end, NM2 and PM2 simultaneously
Pole connects electric capacity C2 one end simultaneously；Electric capacity C1 and electric capacity the C2 other end are grounded respectively；
NM1 and PM1 source electrode also connects PM5, PM3 and NM3 drain electrode simultaneously；PM5 source electrode meets reset power Vdd；PM5 grid
Meet resetting voltage Vrst；One of output end vo ut1 that PM3 and NM3 source electrode connects as sample circuit；NM2's and PM2
Source electrode also connects PM6, PM4 and NM4 drain electrode simultaneously；PM6 source electrode meets reset power Vdd；PM6 grid connects resetting voltage
Vrst；Another output end vo ut2 that PM4 and NM4 source electrode connects as sample circuit；
Output end vo ut1 and Vout2 connect two inputs of row differential amplifier circuit respectively.
5. the detection device according to claim 4 for being used to gathering and handling laser signal, it is characterised in that：A/D is changed
Circuit includes ramp generating circuit and multiple comparators, and the quantity of comparator is equal to the columns of pixel unit array, and one is compared
Device one row pixel cell of correspondence；The waveform signal output end of ramp generating circuit and one of input of each comparator are equal
It is connected, the voltage signal that all sample circuits of each row pixel cell are exported is sent by corresponding row differential amplifier circuit
Enter another input of the comparator corresponding to the row pixel cell, the output end of all comparators connects data outputting module
Input；
Ramp generating circuit includes load resistance R, integrating capacitor C and operational amplifier；A load resistance R termination voltage
Vin1, load resistance the R other end connect the reverse input end of operational amplifier and integrating capacitor C one end, integrating capacitor C simultaneously
Another termination operational amplifier output end Vramp, integrating capacitor C two ends are also parallel with reset switch RST, operation amplifier
The input termination voltage Vin2 in the same direction of device；Voltage Vin1, Vin2 are used to control the ramp signal produced by ramp generating circuit, its
The bleeder circuit of middle voltage Vin1, Vin2 in detection device is produced；
Data outputting module also includes Nbit counters, output buffer module and multiple memories；The input of multiple memories
Correspond and be connected with the output end of the multiple comparator respectively, Nbit counters and the column selection module send control respectively
Signal gives the control end of the multiple memory, and the data output end of the multiple memory is slow with output by data/address bus
The input of die block is connected, and the data signal for calculating phase is exported by the output end of output buffer module.
6. being used for according to claim 4 or 5 gathers and handled the detection device of laser signal, it is characterised in that：It is described
The bottom of substrate is provided with the microlens array being made up of multiple Fresnel Lenses；One pixel list of each Fresnel Lenses correspondence
Member, for transmiting echo-signal light and making echo-signal light converge to the photodiode of respective pixel unit.
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