CN107239092A - Temperature independent reference electric current for calibration is generated - Google Patents

Temperature independent reference electric current for calibration is generated Download PDF

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Publication number
CN107239092A
CN107239092A CN201710142405.2A CN201710142405A CN107239092A CN 107239092 A CN107239092 A CN 107239092A CN 201710142405 A CN201710142405 A CN 201710142405A CN 107239092 A CN107239092 A CN 107239092A
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voltage
circuit
resistor
temperature
electric current
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CN201710142405.2A
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CN107239092B (en
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S.P.泰戈
S.雅达拉
R.萨米内尼
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SanDisk Technologies LLC
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SanDisk Technologies LLC
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Arrangements For Transmission Of Measured Signals (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Disclosed herein is the technology for being used to generate temperature independent reference electric current that can be used during calibrating.Temperature independent reference electric current can be generated based on the electric current by calibrating resistor on piece.The need for piece external calibration resistor, described external calibration resistor is probably expensive and causes slower calibration.Voltage on piece at a terminal of calibrating resistor can be modulated to substantially eliminate the temperature coefficient of calibrating resistor on piece.This can cause the electric current by calibrating resistor on piece temperature independent.Temperature independent reference electric current can be based on reference voltage and target alignment resistance.

Description

Temperature independent reference electric current for calibration is generated
Priority request
The application is entitled " the Temperature Independent Reference submitted on October 30th, 2015 Current Generation for Calibration (being used for the temperature independent reference electric current generation calibrated) " United States Patent (USP) The continuation in part application of application number 14/928,466 and its priority is required, the U.S. Patent application is required in 2014 12 The U.S. Provisional Patent Application No. of entitled " ON CHIP ZQ CALIBRATION (ZQ is calibrated on piece) " submitted for 17th moon No.62/093,307 priority；Described two applications are hereby incorporated by by quoting with entire contents.
Background technology
This technology is related to semiconductor and/or non-volatile memory devices.
Most of semiconductor equipments include input circuit and output circuit, and the input circuit is configured for via defeated Enter pad (or pin) and receive the signal from the external world, the output circuit is configured for via output pad (or pin) outwards Portion provides internal signal.Input circuit has terminating resistor, and the terminating resistor is used for the impedance matching of external transmission lines. Output circuit has output driver, and the output driver has resistance (RConducting).Due to various situations, such as, supply voltage Change, the change of running temperature etc., the impedance of terminating resistor and both output drivers can change.Therefore, impedance is lost With possible increase.
Impedance mismatching can cause signal reflex, and it can damage signal integrity.Due to the speed of service of electric product It has been improved that, the swing width of the signal docked between semiconductor equipment is (that is, between high logic level and low logic level Difference) it has been gradually reduced, so that the time delay for being used in signal transmission minimizes.However, the swing width of signal subtracts It is small to be easy to signal being externally exposed noise, cause the signal reflex at Interface Terminal to become tighter due to impedance mismatching Weight.Therefore, impedance mismatching can cause difficulty and the distortion of output data of high speed data transfer.
, can the periodically output driver of calibrator (-ter) unit and the terminal resistance of equipment in order to mitigate impedance mismatching Device.A kind of collimation technique is referred to as ZQ calibrations.Traditionally, ZQ calibrations can use the accurate calibration resistor outside piece.Institute The variable impedance circuit calibrated relative to off chip resistor device can be had by stating chip.The resistance of ZQ calibration regulation variable impedance circuits Resist until it is calibrated to off chip resistor device.This generates the impedance of the impedance for the output driver that can be used for adjustment equipment Code.
Brief description of the drawings
In different drawings, the element with same reference numerals refers to same parts.
Figure 1A is the sketch of the one embodiment for calibrating circuit, and the calibration circuit has the life of temperature independent reference electric current Into.
Figure 1B is the sketch for another embodiment for calibrating circuit, and the calibration circuit has the life of temperature independent reference electric current Into.
Fig. 2A is the sketch of one embodiment of temperature independent reference current generating circuit, wherein, calibrating resistor on piece There can be positive TCO.
Fig. 2 B are Fig. 2A IPTATThe sketch of one embodiment of current generating circuit.
Fig. 2 C1 are the sketches of one embodiment of circuit, and the circuit is used to save to calibration when the circuit using Figure 1A Point provides Fig. 2A temperature independent reference electric current.
Fig. 2 C2 depict one embodiment of circuit, and the circuit is provided when the circuit using Figure 1B to calibration node ITIREF。
Fig. 2 D are the sketches of one embodiment of temperature independent reference current generating circuit, wherein, calibrating resistor on piece With negative TCO.
Fig. 3 describes using calibrating resistor on piece one embodiment of the process to perform impedance calibration.
Fig. 4 A depict one embodiment of Figure 1A variable impedance circuit 104.
Fig. 4 B depict one embodiment of Figure 1B variable impedance circuit 104.
Fig. 5 shows one embodiment of circuit, and the circuit is used to change voltage modulated resistance according to supply voltage The resistance of device.
Fig. 6 A are the perspective views for the 3D stack non-volatile memory devices that can wherein put into practice embodiment.
Fig. 6 B are the functional block diagrams of memory devices (such as, Fig. 6 A 3D stacks non-volatile memory devices).
Fig. 7 depicts the viewgraph of cross-section of the block with the 3D non-volatile memory devices directly gone here and there.
Embodiment
Disclosed herein is the technology and device that are used to generate temperature independent reference electric current that can be used during calibrating.Can To generate temperature independent reference electric current based on the electric current by calibrating resistor on piece.In one embodiment, temperature is unrelated Reference current is used in ZQ calibration circuits.In one embodiment, temperature independent reference electric current is based on reference voltage and target school Quasi- resistance.For example, temperature independent reference electric current can be equal to reference voltage divided by target alignment resistance.In one embodiment, The calibration voltage in circuit is calibrated to reference voltage with ZQ to be compared.According to this result of the comparison, variable impedance can be adjusted So that variable impedance is close to or equal to target alignment resistance.
In one embodiment, the equipment has calibrating resistor on piece.Which reduce for piece external calibration resistor The need for.Piece external calibration resistor is probably expensive.A part for cost can be used for providing volume for piece external calibration resistor Export trade pads to connect.In addition, can be slow using the ZQ calibrations of piece external calibration resistor.The reason so done is Capacity load on pad or pin is connected to piece external calibration resistor.Presently disclosed embodiment provides quickly calibrated (example Such as, quick ZQ calibrations).Presently disclosed embodiment provides cost-effective calibration (for example, cost-effective ZQ calibrations).
The resistance of calibrating resistor can depend on temperature on piece.For example, its resistance can subtract with the rise of temperature Small or increase.Temperature dependency can be represented by the temperature coefficient (TCO) with symbol and size.For just in this linguistic context Temperature coefficient, it is meant that at least in the temperature range of the equipment normal operating, resistance increases with the rise of temperature And reduce with the reduction of temperature.For negative temperature coefficient in this linguistic context, it is meant that at least in the equipment just The temperature range often operated, resistance reduces with the rise of temperature and increased with the reduction of temperature.
Note, if carrying out operation resistance device using the constant voltage for two terminals for being applied to resistor, pass through resistance The electric current of device can be the function of temperature.For example, if resistance declines with the rise of temperature, electric current is by with temperature Raise and increase --- assume in view of constant voltage difference.
Note, the device temperature for performing correction can be with widely varied.Accordingly, in response to temperature change, calibrated on piece The resistance of resistor can be with time to time change.In certain embodiments, based on the electric current next life by calibrating resistor on piece Into temperature independent reference electric current.Here, temperature independent reference electric current refers to that its size is temperature-independent with reference to electricity Stream.
In one embodiment, the voltage on piece at a terminal of calibrating resistor is modulated to substantially eliminate on piece The temperature coefficient of calibrating resistor.This can cause the electric current by calibrating resistor on piece temperature independent.For example, in view of certain Individual reference voltage is applied to a terminal of calibrating resistor on piece, apply to the voltage of another terminal can be modulated to Temperature change, so that being all constant by how the electric current temperature of calibrating resistor on piece changes.
Figure 1A is the sketch of one embodiment of circuit 100, and the circuit performs calibration using temperature independent reference electric current. In one embodiment, the impedance of the regulation of circuit 100 variable impedance circuit 104 is until its impedance and target resistance (RT) matching. The circuit can be used in ZQ calibration procedures to determine such as calibration code.However, substitution uses piece dispatch from foreign news agency for target resistance Device is hindered, the circuit performs calibration using on-chip resistor 110.In one embodiment, circuit 100 is located at integrated circuit On.
Temperature independent reference current generating circuit 106 is based on the electric current (I by calibrating resistor on piece 110CR) generate Temperature independent reference electric current (temperature independent reference current, ITIREF)112.Although temperature Change, temperature independent reference current generating circuit 106 is by temperature independent reference electric current (ITIREF) maintain constant size.This area It is interior ordinarily skilled artisan will understand that, due to the non-ideal characteristic of real world circuit element, maintaining constant size can wrap Include the temperature independent reference electric current (I relative to temperatureTIREF) size in some small changes.
Because the resistance for for example making calibrating resistor 110 on the material on piece used in calibrating resistor, piece has temperature Coefficient (TCO).In one embodiment, TCO is positive TCO.That is, on piece calibrating resistor 110 resistance keyed temperature The rise of degree and increase and reduce with the reduction of temperature.In one embodiment, TCO is negative TCO.That is, The rise of the resistance keyed temperature of calibrating resistor 110 on piece and reduce and increase with the reduction of temperature.In a reality Apply in example, resistor 110 is formed by polysilicon.However, it is possible to use different semiconductors.In one embodiment, resistor 110 are formed by doped semiconductor, such as, doped silicon.In addition, resistor 110 can be by not being that the material of semiconductor is formed.One In individual embodiment, resistor 110 is located within integrated circuit.
Calibrating resistor 110, which has, in Figure 1A circuit 100, on piece applies to the reference voltage V of a terminalREF.Separately One terminal is provided with modulation voltage VM.In one embodiment, modulation voltage eliminates the TCO of resistor 110.In the art Ordinarily skilled artisan will understand that, due to real world circuit element (include those provide modulation voltages circuit element) it is non- Ideal characterisitics, some small temperature dependencies of resistance of resistor 110 can be included by eliminating the TCO of resistor 110.
In one embodiment, by eliminating the TCO of resistor 110, the electric current (I of resistor is passed throughCR) temperature independent. Therefore, although temperature change, electric current (ICR) constant size can be maintained at.One of ordinary skilled in the art will be understood that, Due to the non-ideal characteristic of real world circuit element, although temperature change, by electric current (ICR) maintain constant size and can wrap Include relative to temperature and electric current (ICR) size in some small changes.
For the modulation voltage with TCO, it is meant that the size of modulation voltage is the function of temperature.Therefore, positive TCO pairs Mean that its size increases with the rise of temperature and reduced with the reduction of temperature in modulation voltage.Negative TCO pairs Mean that its size reduces with the rise of temperature and increased with the reduction of temperature in modulation voltage.
In one embodiment, modulation voltage substantially eliminates the TCO of resistor 110.In one embodiment, base is passed through The TCO of resistor 110 is eliminated in sheet, passes through the electric current (I of resistorCR) substantially temperature independent.
The output calibration electric current of variable impedance circuit 104 (ICAL).In one embodiment, ICALIt is (VPower supply/2)/RT, wherein, RTIt is target alignment resistance.Calibration logic 102 is to variable impedance circuit 104 output impedance code (DAC<n:0>).In this example In, impedance code has n+1.Variable impedance circuit 104 adjusts its impedance based on impedance code.In one embodiment, calibration section Voltage at point is VPower supply–(ITIREF*RVIC), wherein, ITIREFIt is temperature independent reference electric current, and RVICIt is variable impedance circuit 104 impedance under given DAC.Voltage at calibration node can be referred to as VCAL.Note, calibration electric current (ICAL) big I With equal to ITIREF.In one embodiment, ICALEqual to (VPower supply–VCAL)/RVIC.Calibration logic 102 can be realized in many ways, The including but not limited to any combination of state machine, processor, Digital Logic or these elements.Processor, which can be performed, is stored in meter Instruction on calculation machine readable memory.
Variable impedance circuit 104 can include multiple circuit elements, such as, transistor.In one embodiment, can variable resistance Reactive circuit 104 carrys out those transistors of on or off to change the resistance of variable impedance circuit 104 in response to the value of impedance code (DAC) It is anti-.In one embodiment, variable impedance circuit 104 is binary weighting transistor circuit.In one embodiment, can variable resistance Reactive circuit 104 is configured for the different value in response to " n+1 " position impedance code (DAC) and has 2n+1Individual different impedance.Figure 4A provides the further detail below of one embodiment of Figure 1A variable impedance circuit 104.
The inverting input of comparator 108 is provided with reference voltage VREF.In one embodiment, VREFIt is VPower supplyIt is big Small half.Therefore, in one embodiment, ICALEqual to (2VREF–VCAL)/RVIC.Comparator 108 is by non-inverting input (example Such as, VCAL) place voltage size and VREF(providing to inverting input) is compared.In one embodiment, ITIREFIt is big It is small to be based on reference voltage (VREF) and target resistance (RT), variable impedance circuit 104 is calibrated to the target resistance.At one In embodiment, below equation is set up：
ITIREF=VREF/RT (1)
In one embodiment, in addition to equation 1, below equation is set up：
VREF=VPower supply/2 (2)
Wander back to, target resistance (RT) can be that variable impedance circuit 104 is calibrated to resistance.Calibrating resistor on piece 110 resistance can be with target resistance (RT) related.However, the resistance of calibrating resistor 110 needs not be equal to target electricity on piece Hinder (RT).For example, electric current and resistance can be necessarily to scale on piece.For example, the resistance of calibrating resistor 110 can on piece To be exaggerated from target resistance to allow on piece electric current to be reduced.
Comparator 108 is indicated at non-inverting input to the output signal of calibration logic 102 (" mark "), the calibration logic The size of voltage be greater than also being less than the size of the voltage at inverting input.Value of the calibration logic 102 based on mark come Adjust impedance code (DAC).In one embodiment, if the overtension at mark instruction calibration node is (relative to VREF), then New impedance code will cause variable impedance circuit 104 to increase its impedance.On the other hand, if mark is indicated at calibration node Brownout is (relative to VREF), then new impedance code (DAC) will cause variable impedance circuit 104 to reduce its impedance.In a reality Apply in example, perform binary search to seek new impedance code.In one embodiment, linear search is performed to find new resistance Anti- code.In one embodiment, as long as VCALHigher than VREF, mark is " 1 ".In one embodiment, V is worked asCALSlightly less than VREF When, mark becomes " 0 ", and finely tunes completion.In one embodiment, when completing fine setting, in variable impedance circuit 104 The impedance of pmos driver (for example, 402 in Fig. 4 A) is equal to, or slightly larger than RT。
As described above, Figure 1A circuit can be used together with Fig. 4 A pmos driver.Figure 1B is depicted similar to figure One embodiment of the circuit of 1A circuit, but can be with NMOS drivers (those such as, described in Fig. 4 B) together Use.Note, and in figure ia, variable impedance circuit is connected to VPower supplyBetween calibration node, in fig. ib, variable impedance electricity Road be connected to calibration node between.The operation of Figure 1B circuit 100 is similar to Figure 1A circuit, with some differences. In Figure 1B, VCALEqual to ITIREF*RVIC, wherein, RVICIt is impedance of the variable impedance circuit 104 under existing DAC.In an implementation In example, when completing fine setting, the impedance of the NMOS drivers (for example, driver 422 in Fig. 4 B) in variable impedance circuit 104 Equal to or slightly less than RT。
Fig. 2A is that there is provided one embodiment of Figure 1A or Figure 1B temperature independent reference current generating circuit 106 for sketch Further detail below.Circuit 106 includes calibrating resistor 110 on piece.The resistance of calibrating resistor 110 becomes with temperature on piece Change.In other words, the resistance of calibrating resistor 110 has TCO on piece.For example, the resistance of calibrating resistor 110 can be with piece The rise of temperature and increase (for example, the TCO of resistance is positive).On piece the voltage of calibrating resistor 110 have positive TCO with Keep constant, this represents the electric current (I by calibrating resistor 110 on pieceCR) will reduce with the rise of temperature.Fig. 2A electricity Road can be used together with the resistor 110 with positive TCO.Alternately, the resistance of calibrating resistor 110 can be with piece The rise of temperature and reduce (for example, the TCO of resistance is negative).With suitably modified, the concept of the circuit to Fig. 2A It can be used together with the resistor with negative TCO.Fig. 2 D, which are shown, to be used together with the resistor with negative TCO Circuit one embodiment.For calibrating resistor 110 on the piece with negative TCO, the electricity on piece on calibrating resistor 110 Pressure keeps constant, and this represents ICRIt will increase with the rise of temperature.
The TCO of calibrating resistor 110 is positive or negative can to depend on making the material of resistor 110, mix on piece Miscellaneous and other factors.For example, the resistivity of undoped silicon can have negative TCO.However, according to the impurity for doping Type and doping concentration, doped silicon can have positive TCO or negative TCO.In addition, the TCO of the resistivity for semiconductor Size can depend on for adulterate impurity type and doping concentration.In one embodiment, calibrating resistance on piece Device 110 is made by silicon, and the silicon is doped with the impurity of a type and concentration, and the impurity causes the resistivity of doped silicon to have Positive TCO.
A terminal of calibrating resistor 110 is provided with the V from operational amplifier 214 on pieceREF.Note, calibration electricity One terminal of resistance device 110 is coupled to the non-inverting input of operational amplifier 214.In addition, operational amplifier 214 is anti-phase defeated Enter end and be provided with VREF.Because the non-inverting input of operational amplifier 214 is forced VREF, so calibrating resistor on piece 110 terminal is provided with VREF。
Another terminal of calibrating resistor 110 is provided with modulation voltage (V on pieceM).The size of modulation voltage can be with It is the function of temperature.Here, this is referred to as the modulation voltage with TCO.This causes the voltage on calibrating resistor 110 on piece to be The function of temperature.In one embodiment, the TCO of modulation voltage eliminates the TCO of the resistance of calibrating resistor 110 on piece.This can To cause the electric current (I by calibrating resistor on piece 110CR) temperature independent.Therefore, although temperature change, ICRIt can be tieed up Hold in constant size.
In Fig. 2A circuit, modulation voltage (VM) size can be less than VREFSize.Therefore, the V of reductionMResult It is the bigger voltage on piece on calibrating resistor 110, and from there through the bigger electric current of calibrating resistor on piece 110 (ICR).In one suchembodiment, VMWith negative TCO to eliminate the positive TCO of calibrating resistor 110 on piece.With Temperature rise, the resistance of calibrating resistor can increase, but VMIt can reduce, although so that temperature change, passes through The electric current of calibrating resistor is constant.
Pass through the electric current (I of calibrating resistor on piece 110CR) PMOS transistor 222 is also flowed through, its electric current is mirrored onto PMOS Transistor 224.Temperature independent reference electric current (I may be used as by the electric current of PMOS transistor 224TIREF).Note, it is understood that there may be ICRSome scaling.For example, PMOS transistor 224 can be selected with the ratio of PMOS transistor 222 to zoom in or out electric current ICR.The temperature independent reference electricity that can be used for by the electric current or its some versions of PMOS transistor 224 in Figure 1A or Figure 1B Flow (ITIREF).For example, can be before the calibration node being supplied to the electric current by transistor 224 in Figure 1A or Figure 1B to it Zoom in or out.However, in one embodiment, due to ITIREFBased on ICR, so ITIREFIt is temperature independent.Therefore, to the greatest extent Pipe temperature change, ITIREFConstant size can be maintained at.In fig. 2, transmitting circuit 270 is depicted for calibration section Point provides ITIREF.Transmitting circuit 270 can be realized using transistor.For example, transmitting circuit 270 can be current mirror.Fig. 2 C1 With example transmitting circuit 270 is depicted in Fig. 2 C2.
It is further noted that the output end of operational amplifier 214 is connected to the gate terminal and PMOS of PMOS transistor 222 The gate terminal of transistor 224.Source terminal of PMOS transistor 222 and 224 is also connected respectively to voltage source.Therefore, PMOS The drain terminal of transistor 222 is connected to the non-inverting input of operational amplifier 214.
Then, generation modulation voltage (V will be discussedM) details.Modulation voltage (VM) size be at least partially based on absolutely To temperature proportional (proportional to absolute temperature) electric current (IPTAT).Fig. 2A is depicted IPTATCurrent source 201.I can be realized by bandgap reference (BGR) circuitPTATCurrent source 201.It therefore, it can join by band gap (BGR) circuit is examined to generate IPTAT.I is depicted in Fig. 2 BPTATOne embodiment of current source 201.
IPTATCurrent source 201 is connected between the inverting input of supply voltage and operational amplifier 202.Operational amplifier 202 non-inverting input is provided with VBGP.Due to circuit configuration, the voltage at non-inverting input should be forced VBGP。
The output end of operational amplifier 202 is connected to the gate terminal of nmos pass transistor 204.The source of nmos pass transistor 204 Extreme son is connected to the inverting input of operational amplifier 202.The drain terminal of nmos pass transistor 204 is connected to PMOS transistor 208, the PMOS transistor forms current mirror together with PMOS transistor 210.
Bandgap reference resistor RBGR206 are connected between the inverting input of operational amplifier 202 and ground.RBGR 206 In electric current be IPTAT(it is referred to as I plus the electric current of transistor 203CTAT).In addition, during circuit operation, operational amplifier 202 inverting input will be forced VBGP.Resistor RBGR206 resistance will be referred to as " RBGR”.Therefore, resistor RBGR 206 be of virtually be supplied to reception IPTATAnd ICTATTerminal VBGP.Therefore, ICTATProvided by equation 3：
ICTAT=VBGP/RBGR-IPTAT (3)
Electric current (ICTAT) can also be expressed by equation 4：
ICTAT=VBGP/RBGR-VT*lnN/RPTAT (4)
Electric current ICTATFlow through nmos pass transistor 204 and PMOS transistor 208.By the electric current of PMOS transistor 208 by mirror As arriving PMOS transistor 210.Note, the source terminal of PMOS transistor 208 and PMOS transistor 210 is connected respectively to power supply electricity Pressure, and their gate terminal is connected.In one embodiment, PMOS transistor 208 and 210 is dimensionally similar, from And to be substantially equal to I by the electric current of transistor 210CTAT.However, PMOS transistor 208 and 210 needs not be identical Size, wherein, the electric current by transistor 210 can be ICTATZoom version.The electric current of PMOS transistor 210 can also flow Through voltage modulated resistor RCT212.In one embodiment, this electric current is ICTAT.As described above, this can also be ICTAT Some zoom versions.Voltage modulated resistor RCT212 are connected between the inverting input of operational amplifier 216 and ground.Cause This, the voltage at the inverting input of operational amplifier 216 can be provided by equation 5：
VRCT=ICTAT*RCT (5)
The output end of operational amplifier 216 is connected to the gate terminal of nmos pass transistor 218.The source of nmos pass transistor 218 Pole is connected to ground.The drain electrode of nmos pass transistor 218 is connected to the non-inverting input of operational amplifier 216.Operational amplifier 216 Non-inverting input at voltage can be forced VRCT.Therefore, modulation voltage VMV can be equal toRCT.It can be said that not connecing The node of the voltage modulated resistor 212 on ground is coupled to the Second terminal of calibrating resistor 110, because voltage VRCTIt can be carried Supply the Second terminal of calibrating resistor 110.
Several sub-circuits are highlighted in temperature independent reference current generating circuit 106.Voltage modulation circuit 232 It is configured for providing modulation voltage (V to one of terminal of calibrating resistor 110M).For example, voltage modulation circuit 232 is adjusted Voltage at the terminal of calibrating resistor 110 processed is to eliminate the temperature coefficient of calibrating resistor.Therefore, by calibrating resistor 110 electric current can be with temperature independent.Voltage modulation circuit 232 is by IPTATSource 201, resistor 206 and 212, operational amplifier 202 and 216 and transistor 204,208,210 and 218 constitute.Other circuit elements can be used for voltage modulation circuit 232.Electricity Pressure modulation circuit 232 is also referred to as temperature dependent voltage generative circuit.Temperature dependent voltage generative circuit can be configured Voltage (V at the Second terminal for generating calibrating resistor 110M), the voltage, which has, to be configured for eliminating school The temperature coefficient of the temperature coefficient of quasi- resistor 110.
Reference voltage circuit 236 is configured for providing with reference to electricity to another terminal of calibrating resistor 110 Press (VREF).Reference voltage circuit 236 is made up of operational amplifier 214 and transistor 222.Temperature independent reference current circuit 234 It is configured for from the temperature independent current (I by calibrating resistor 110CR) in obtain temperature independent reference electric current (ITIREF).Temperature independent reference current circuit 234 is by calibrating resistor 110, transistor 222, transistor 224 and transmitting circuit 270 compositions.Other circuit elements can be used for temperature independent reference current circuit 234.
Some electric current softwares in Fig. 2A can be collectively known as the circuit with temperature proportional, described and temperature proportional Circuit be configured for providing by the electric current with temperature proportional of voltage modulated resistor 212.Specifically, voltage is adjusted The part for providing electric current to voltage modulated resistor 212 of circuit 232 processed can be used for the purpose.Those elements include IPTAT Source 201, operational amplifier 202, resistor RBGR206 and transistor 204,208 and 210.Other circuit elements can be used for With the circuit of temperature proportional.
The above is voltage modulation circuit 232 (also referred to as temperature dependent voltage generative circuit), reference voltage circuit 236 and the example of temperature independent reference current circuit 234.However, it is possible to use other circuit elements and configuration.
Fig. 2 B depict IPTATThe one embodiment of source 201, the IPTATSource can be used in Fig. 2A or Fig. 2 D circuit 106. IPTATSource 201 includes operational amplifier 240, PMOS transistor 248, PMOS transistor 250, PMOS transistor 252, RPTATResistance Device 242, diode 244 and diode 246.Source terminal of PMOS transistor 248,250 and 252 is connected respectively to voltage source (VPower supply).The drain electrode of PMOS transistor 248 is connected to the inverting input of operational amplifier 240.The drain electrode of PMOS transistor 250 It is connected to the non-inverting input of operational amplifier 240.The grid of PMOS transistor 248,250 and 252 is connected respectively to computing The output end of amplifier 240.
RPTATResistor 242 is connected between the non-inverting input of operational amplifier 240 and diode 246.Diode 246 are connected to RPTATBetween resistor 242 and ground.Diode 244 is connected to the inverting input and ground of operational amplifier 240 Between.Diode 244 and diode 246 have 1:N ratio.
IPTATElectric current flows through PMOS transistor 252.In one embodiment, the drain electrode of PMOS transistor 252 is connected to electricity Hinder device RBGR206 (referring to a Fig. 2A) terminal.In one embodiment, the drain electrode of PMOS transistor 252 is also connected to fortune Calculate the inverting input of amplifier 202 (referring to Fig. 2A).Note, resistor R is depicted in Fig. 2ABGR206 and operational amplifier 202。
IPTATSource 201 may be also used in Fig. 2 D circuit.In one embodiment, the drain electrode of PMOS transistor 252 connects It is connected to resistor RCT212 (referring to a Fig. 2 D) terminal.
Fig. 2 C1 depict the one embodiment of transmitting circuit 270, and the transmission electricity can be used when the circuit using Figure 1A Road.Transmitting circuit 270 can be used in Fig. 2A or Fig. 2 D circuit.Transmitting circuit 270 is by the I from transistor 224TIREFThere is provided Non-inverting input to comparator 108.Transmitting circuit 270 includes nmos pass transistor 262 and nmos pass transistor 260, and its is each Their source electrode is set to be connected to ground.Nmos pass transistor 262 and nmos pass transistor 260 are in current mirror configuration.Nmos pass transistor 262 Drain electrode be connected to the drain electrode of PMOS transistor 224, to receive the I from PMOS transistor 224TIREF.Nmos pass transistor 260 Drain electrode be connected to the non-inverting input of comparator 108, to provide I to calibration nodeTIREF。
Nmos pass transistor 262 and nmos pass transistor 260 can be identical size or can be different sizes.Cause This, the I at the non-inverting input of comparator 108TIREFVersion can be I with flowing through transistor 224TIREFVersion phase Same size, can be exaggerated, or can be reduced.Note, figure comparator 108 is also illustrated in Figure 1A, and in Fig. 2A Also illustrate transistor 224.
Fig. 2 C2 depict one embodiment of circuit, and the circuit is provided when the circuit using Figure 1B to calibration node ITIREF.This circuit can be used in Fig. 2A or Fig. 2 D circuit 106.In this embodiment, it is not necessary to transmitting circuit 270.
Fig. 2 D are the sketches of one embodiment of temperature independent reference current generating circuit, wherein, calibrating resistor on piece 110 have negative TCO.The circuit is similar to the circuit in Fig. 2A.Note, Fig. 2 D depict voltage modulation circuit 232 with The different embodiment of the voltage modulation circuit described in Fig. 2A.Difference is IPTATElectric current is provided directly to resistor 212. In Fig. 2 D circuit, the resistance of calibrating resistor 110 can reduce with the rise of temperature (for example, the TCO of resistance is on piece Negative).Voltage on piece on calibrating resistor 110 is used to keep constant, and this represents the electric current by calibrating resistor 110 on piece (ICR) will increase with the rise of temperature.In this embodiment, VMWith TCO to eliminate calibrating resistor 110 on piece Negative TCO.For example, in one example, VMWith positive TCO to eliminate the negative TCO of calibrating resistor 110 on piece. As temperature is raised, the resistance of calibrating resistor can reduce, but VMIt can increase, although so that temperature change, leads to The electric current for crossing calibrating resistor is constant.Note, Fig. 2 B IPTATSource 201 may be also used in Fig. 2 D circuit.Equally, come It can be used in from Fig. 2 C transmitting circuit 270 in Fig. 2 D circuit.
Fig. 3 describes using calibrating resistor on piece one embodiment of the process to perform impedance calibration.The process It can be realized by Figure 1A, Figure 1B, Fig. 2A, Fig. 2 B, Fig. 2 C1, Fig. 2 C2 and/or Fig. 2 D, but not limited to this.In one embodiment In, the process performs ZQ calibrations.
In step 302, reference voltage is supplied to the first terminal of calibrating resistor on piece.In one embodiment, join Potential circuit 236 is examined by reference voltage (VREF) it is supplied to the terminal of calibrating resistor 110 on piece.
In step 304, offset voltage is generated.Offset voltage is also referred to as modulation voltage.In one embodiment, Voltage modulation circuit 232 generates offset voltage.In one embodiment, generation offset voltage includes generation and absolute temperature (PTAT) proportional electric current, and offset voltage is generated based on PTAT current.In one embodiment, IPTATCurrent source 201 Generate IPTATElectric current.In one embodiment, based on IPTATThe electric current of electric current is provided to voltage modulated resistor 212, in computing Offset voltage is created at the inverting input of amplifier 216.
Within step 306, compensation (or modulation) voltage is provided to the Second terminal of calibrating resistor on piece 110.At one In embodiment, voltage modulation circuit 232 provides offset voltage to the Second terminal of calibrating resistor on piece 110.More specifically, fortune The non-inverting input for calculating amplifier 216 is connected to the relatively low terminal of calibrating resistor 110 on piece to provide VM.Note, computing The configuration of amplifier 216 and transistor 218 can be tended to force into the voltage at non-inverting input and operational amplifier Voltage at 216 inverting input is identical.Therefore, the electricity created at the terminal of unearthed voltage modulated resistor 212 Pressure can be provided to calibrating resistor 110 on piece.
In step 308, temperature independent reference electric current is provided to calibration node.In one embodiment, the calibration section Point is the calibration node at the non-inverting input of Figure 1A comparator 108.In one embodiment, the calibration node is figure Calibration node at the non-inverting input of 1B comparator 108.In one embodiment, temperature independent reference electric current generation electricity Road 106 provides temperature independent reference electric current (for example, I to calibration nodeTIREF).In one embodiment, temperature independent reference electricity Current circuit 234 is generated from the electric current (I by calibrating resistor 110 on pieceCR) ITIREF.In one embodiment, temperature without Close reference current and be based on reference voltage and target alignment resistance.For example, temperature independent reference electric current can meet equation 1.
In the step 310, provide calibration signal to cause variable impedance circuit to change its impedance to variable impedance circuit. In one embodiment, calibration logic 102 is to variable impedance circuit 104 output impedance code (DAC).Variable impedance circuit 104 is based on The value of impedance code changes its impedance.In one embodiment, variable impedance circuit 104 exports I to calibration nodeCAL.In addition, ICALAnd ITIREFIt is probably only notable electric current at calibration node.Therefore, ICALCan have and ITIREFIdentical size.Cause This, ICALV can be equal toREF/RT。
In step 312, to calibration voltage size and the size of reference voltage is compared.Comparator 108 be based on than Compared with result output token, as discussed above.
In a step 314, calibration signal is adjusted based on comparative result.In one embodiment, calibration logic 102 is based on mark The value of note adjusts impedance code (DAC).As has been discussed, this causes variable impedance circuit 104 to adjust its impedance.It can weigh Multiple step 310 reaches desired accuracy level to 314 until the impedance of variable impedance circuit is balanced with target resistance.At one In embodiment, linear search is performed by adjusting the impedance code of a unit every time.In one embodiment, perform and linearly search Rope.The search in addition to linear search and binary search can be performed.
Fig. 4 A depict one embodiment of Figure 1A variable impedance circuit 104.In one embodiment, variable impedance electricity Road 104a is the copy of output buffer.Therefore, variable impedance circuit 104 can be referred to as copy circuit.In one embodiment In, it is binary weighting pull-up copy.
Variable impedance circuit 104a includes transistor 402-0,402-1,402-2,402-3,402-4,402-5 and 402-6. In one embodiment, transistor 402 is p-channel transistor.One terminal of each transistor 402 is connected to supply voltage VPower supply.Another terminal of each transistor is connected to resistor 414.Resistor 414 is connected to calibration node.This refers to figure Calibration node in 1A.
Each in transistor 402 is by impedance code DAC_P<n:0>Position in one control its grid.Crystal Pipe 402-0 controls its grid by DAC_P_0, and DAC_P_0 refers to DAC_P<n:0>In least significant bit.Transistor 402-1 Its grid is controlled by DAC_P_1.Transistor 402-2 controls its grid by DAC_P_2.Transistor 402-3 controls it by DAC_P_3 Grid.Transistor 402-4 controls its grid by DAC_P_4.Transistor 402-5 controls its grid by DAC_P_5.Transistor 402- 6 control its grid by DAC_P_6, and DAC_P_6 refers to DAC_P<n:0>In highest significant position.Can be by the connection of grid Referred to as to the input of variable impedance circuit.It is conducting/cut-out that the value of impedance code, which can be used for selection which transistor 402, with Just control circuit 104a impedance.
Transistor can be by " binary weighting ", so that transistor 402-0 has weight " 1 ", transistor 402-1 tools There is weight " 2 ", transistor 402-2 has weight " 4 ", and transistor 402-3 has weight " 8 ", and transistor 402-4 has weight There is " 16 ", transistor 402-5 weight " 32 " and transistor 402-6 to have weight " 64 ".For weight, it is meant that transistor The influence of copy 404a impedance is pulled up to main binary weighting.
In one embodiment, transistor 402 has the ratio (W/L) of binary weighting channel width and length.For example, Binary weighting W/L can be 1x, 2x, 4x, 8x, 16x, 32x and 64x.Transistor W/L can also be referred to as transistor size.
In one embodiment, transistor 402 is realized by multiple transistors.It will be appreciated, therefore, that transistor 402 In each can represent one or more transistors.In addition, transistor for realizing transistor 402-0 to 402-6 Binary relationship is there may be between quantity.For example, it is possible to use single transistor realizes transistor 402-0, it is possible to use two Individual transistor realizes transistor 402-1, it is possible to use four transistors realize transistor 402-2 etc..In this illustration, Each for realizing in transistor can have identical W/L.
Fig. 4 B depict one embodiment of variable impedance circuit.This can be used in the calibration for being similar to and being described in Figure 1B In the calibration circuit of circuit.In this case, circuit 104b is binary weighting pull-up copy.Binary weighting pulls up copy 104b can replicate a part for output driver.Binary weighting pull-up copy 104b include transistor 422-0,422-1, 422-2,422-3,422-4,422-5 and 422-6.In one embodiment, transistor 422 is n-channel transistor.Each crystal One terminal of pipe 422 is connected to the voltage V that can be groundedSS.Another terminal of each transistor is connected to resistor 415. Resistor 415 is connected to calibration node.
Each in transistor 422 is by impedance code DAC_N<n:0>Position in one control its grid.Crystal Pipe 422-0 controls its grid by DAC_N_0, and DAC_N_0 refers to DAC_N<n:0>In least significant bit.Transistor 422-1 Its grid is controlled by DAC_N_1.Transistor 422-2 controls its grid by DAC_N_2.Transistor 422-3 controls it by DAC_N_3 Grid.Transistor 422-4 controls its grid by DAC_N_4.Transistor 422-5 controls its grid by DAC_N_5.Transistor 422- 6 control its grid by DAC_N_6, and DAC_N_6 refers to DAC_N<n:0>In highest significant position.Can be by the connection of grid Referred to as to variable impedance circuit 104b input.It is conducting/cut-out that the value of impedance code, which can be used for selection which transistor 402, , to control circuit 104b impedance.
Transistor can be by " binary weighting ", so that transistor 422-0 has weight " 1 ", transistor 422-1 tools There is weight " 2 ", transistor 422-2 has weight " 4 ", and transistor 422-3 has weight " 8 ", and transistor 422-4 has weight There is " 16 ", transistor 422-5 weight " 32 " and transistor 422-6 to have weight " 64 ".For weight, it is meant that transistor The influence of copy 424a impedance is pulled up to binary weighting.
In one embodiment, transistor 422 has the ratio (W/L) of binary weighting channel width and length.For example, Binary weighting W/L can be 1x, 2x, 4x, 8x, 16x, 32x and 64x.Transistor W/L can also be referred to as transistor size.
In one embodiment, binary weighting pull-up copy 414a transistor 422 is realized by multiple transistors.Cause This, it will be appreciated that, each in transistor 422 can represent one or more transistors.In addition, for realizing transistor Binary relationship is there may be between the quantity of 422-0 to 422-6 transistor.For example, it is possible to use single transistor is realized Transistor 422-0, it is possible to use two transistors realize transistor 422-1, it is possible to use four transistors realize crystal Pipe 422-2 etc..In this illustration, each for realizing in transistor can have identical W/L.
Note, the example in Fig. 4 A and Fig. 4 B is to be directed to the situation that wherein impedance code is seven.If impedance code be more than or Less than seven, then the quantity of the transistor in Fig. 4 A and Fig. 4 B can accordingly be changed.
The generation of temperature independent reference electric current is detailed further below.In one embodiment, for the unrelated ginseng of temperature The target for examining electric current is provided by equation 6.
ITIREF=VREF/RT (6)
In equation 6, RTIt is the target resistance being compared with the impedance of variable impedance circuit 104.For example, this can be The target resistance calibrated for ZQ.Reference voltage VREFAt the inverting input for referring to comparator 108 in Figure 1A or Figure 1B VREF.As described above, this can be supply voltage (VPower supply) half.It is conceptive, RTThe noninverting of comparator 108 can be considered as Target resistance between input and ground.Due to VREFCan be VPower supplyHalf, so the target of Figure 1A (or Figure 1B) circuit It is R that can be recited as the impedance calibration of variable impedance circuit 104T.More specifically, the target can be recited as regulation The impedance of variable impedance circuit 104 is equal to or is at least nearly to R until itT。
The size of the electric current of calibrating resistor 110 is equal to temperature independent reference electric current (I on by pieceTIREF) hypothesis Under, equation 7 is as follows：
(VREF-VM)/RD=VREF/RT (7)
In equation 7, VREF-VMRefer to the voltage on calibrating resistor 110 on piece.As discussed above, piece colonel Resistance (the R of quasi- resistor 110D) there is temperature coefficient.
In one embodiment, modulation voltage (VM) it is based on PTAT current.Equation 8A is according to from IPTATCurrent source 201 Other elements in PTAT current and Fig. 2A describe modulation voltage (VM).Wander back to, when calibrating resistor 110 has just on piece TCO when, Fig. 2A circuit can be used.
Modulation voltage (VM) with two parts in equation 8A.Each part includes the electricity of voltage modulated resistor 212 Hinder (RCT) it is multiplied by electric current.Wander back to, pass through the electric current (I of transistor 208CTAT) voltage modulated resistor 212 can be reflected to. Also wander back to, there can be two parts by the electric current of transistor 208.One of those parts can be by VBGP/RBGRProvide.This It is due to that resistor R is provided to by operational amplifier 202BGR206 VBGPInfluence.Other electric currents are IPTATElectric current.Cause This, in one embodiment, ICTATEqual to by VBGP/RBGRThe part provided subtracts IPTATElectric current (referring to equation 4).In equation 8A In, according to the two of the absolute value of the electric charge on Boltzmann constant (k), Kelvin's absolute temperature (T), electronics (q) and Fig. 2 B Pole pipe ratio (N) (referring to diode 244 and 246) expresses IPTATElectric current.In one embodiment, RPTATIn being Fig. 2A IPTATThe resistance of current source 201.In one embodiment, RPTATIt is the R in Fig. 2 BPTATThe resistance of resistor 242.
Equation 8B is according to from IPTATOther elements in the PTAT current and Fig. 2 D of current source 201 describe modulation voltage (VM).Wander back to, when calibrating resistor 110 has negative TCO on piece, Fig. 2 D circuit can be used.
In one embodiment, design modulation voltage (VM), so that passing through the electric current of calibrating resistor on piece 110 (ICR) temperature independent, as indicated by equation 9.
In view of the I for being zero relative to temperatureCRDerivative, the situations below in equation 10A and 10B goes for：
(10A) (works as VMWhen TCO is negative)
(10B) (works as VMWhen TCO is positive)
The following is the repetition of equation 7, modulation voltage (V is notedM) and piece on calibrating resistor (RD) temperature dependency：
The target of one embodiment is so that modulation voltage (VM) eliminate piece on calibrating resistor 110 TCO.This target Reflected by equation 12, express the situation of the temperature dependency for modulation voltage, to eliminate calibrating resistor on piece TCO.In equation 12, TCORDCan be it is relevant form calibrating resistor 110 on piece (a variety of) material (if using doping, Then after doping) resistivity temperature coefficient.In other words, TCORDIt can be the electricity about calibrating resistor on piece 110 The temperature coefficient of resistance.In one embodiment, TCORDIt is positive value.However, depending on factor, such as, making and electricity being calibrated on piece Hinder material, doped level, dopant material of device etc., TCORDIt can be negative value.Note, no matter calibrating resistor on piece TCO is positive or negative, and equation 12 can be set up.
Equation 13 gives design formula for one embodiment, wherein, about the modulation voltage (V of temperatureM) derivative It can be provided by equation 12.
In one embodiment, RPTATValue can be IPTATThe attribute of current source 201.In one embodiment, RPTATIt is R in Fig. 2 BPTATResistor 242.According to known RPTATValue, can be determined from equation 12 and 13 for RCTFor it is suitable Value.In the case of using Fig. 2A circuit, find for RCTFor after suitable value, can be from for example with for VMAnd Speech is adapted to horizontal equation 8A and determined for RBGRValue for be suitably worth.
Note, can be compensated with calibrating resistor on trim plate 110 for change in process.For example, such as chankings colonel Quasi- resistor 110 is formed by DOPOS doped polycrystalline silicon, and its resistance can depend on factor, e.g., the quantity and size of grain boundary, many Shape (length, width and height), doping concentration of crystal silicon etc..In one embodiment, calibrating resistor 110 on trim plate, So that under reference temperature, its resistance is equal to target resistance.
In one embodiment, due to supply voltage VPower supplyChange, voltage modulated resistor RCT212 resistance is variable 's.Fig. 5 shows one embodiment of circuit, and the circuit is used to change voltage modulated resistor R according to supply voltageCT 212 resistance.Supply voltage is provided to analog-digital converter (ADC) 502.ADC 502 is generated and supply voltage VPower supplyIt is big Small proportional data signal RS.Data signal RSIt is provided to voltage modulated resistor RCT212.Voltage modulated resistor RCT 212 are configured for being based on data signal RSTo change its resistance.
In certain embodiments, Impedance calibrating circuit 100 is a part for memory devices.Following discussion provides example The details of the structure of memory devices, the realization that the memory devices can be proposed is used for the technology for determining impedance code.
Fig. 6 A are the perspective views of 3D stack non-volatile memory devices.Memory devices 800 include substrate 801. On substrate or on be memory cell (non-volatile memory device) sample block BLK0 and BLK1.Equally on substrate It is to carry the outer peripheral areas 804 for the described piece of circuit used.Substrate 801 can also carry circuit and carrying under these blocks The one or more lower metal layers being patterned in conductive path form of the signal of circuit.The formation of these blocks is set in memory In standby intermediate region 802.In the upper area 803 of memory devices, one or more upper metallization layers are with conductive path Form is patterned to carry the signal of circuit.Each block includes the stack region of memory cell, the heap described in the stack region Folded alternating level represents wordline.In a kind of possible method, each block has a relative layering side, vertical contact from this Extend upwardly to upper metallization layer sideways to be formed to the connection of conductive path a bit.Although depict two blocks as an example, It is that can use the extra block upwardly extended in x directions and/or y side.If furthermore, it is noted that part is directly connected to or in succession Connect, then it is assumed that part is connection.
In a kind of possible method, the length of plane in the x direction represent to the signal path of wordline at one or The direction (word-line direction or SGD lines direction) extended in multiple upper metallization layers, and plane in y-direction width means The direction (bit line direction) extended to the signal path of bit line in one or more upper metallization layers.Z directions represent memory The height of equipment.
Fig. 6 B are the functional blocks of memory devices 800 (such as, Fig. 6 A 3D stacks non-volatile memory devices 800) Figure.Memory devices 800 can include one or more memory dices 808.Memory dice 808 includes memory cell Memory construction 826, such as, and array, control circuit 810 and the read/write circuits 828 of storage unit.In 3D configurations, Memory construction can include Fig. 8 A block BLK0 and BLK1.Memory construction 826 can via row decoder 824 by wordline with And addressed via column decoder 832 by bit line.Read/write circuits 828 include multiple sensing block SB1, SB2 ..., SBp (sensing circuit), and allow concurrently page of memory unit is read out or programmed.Generally, controller 822 and one Or multiple memory dices 808 are equally included in identical memory devices 800 (for example, removable storage card).At some In embodiment, a controller will be communicated with multiple memory dices.Order and data are via data/address bus 820 in main frame Transmitted between 840 and controller 822 and via line 818 between controller and one or more memory dices 808.One In individual embodiment, memory dice has I/O circuits 700.I/O circuits 700 can include output buffer.In one embodiment In, the ZQ calibrations of output buffer are performed using Fig. 1 circuit.
Memory construction 826 can be the two-dimensional structure or three of memory cell (for example, NAND flash unit) Tie up structure.Memory construction can include one or more arrays of the memory cell comprising 3D arrays.Memory construction can With including Kfc three dimensional memory structure, wherein, multiple memory hierarchies are formed above single substrate (such as, chip) and nothing Substrate in the middle of intervening.Memory construction can include any kind of nonvolatile memory, the nonvolatile memory Turned into one or more physical levels of the array of memory cell by one chip landform, the memory cell, which has, is arranged in silicon The active area of substrate.Memory construction can be in non-volatile memory devices, the non-volatile memory devices With the circuit associated with the operation of memory cell, no matter associated circuit substrate or within.
Control circuit 810 is cooperated with read/write circuits 828 to perform storage operation to memory construction 826, and Including state machine 812, on-chip address decoder 814 and power control module 816.State machine 812 provides storage operation Chip-scale is controlled.Parameter storage 813, which can be provided, to be used to store operating parameter.
On-chip address decoder 814 provides address used in main frame or Memory Controller and the institute of decoder 824 and 832 Address interface between the hardware address used.Power control module 816 is during storage operation to being supplied to wordline and position The power and voltage of line are controlled.It can include being used for driver, SGS the and SGD crystal of word line layer (WLL) during 3D is configured Pipe and source electrode line.In one approach, sensing block can include bit line driver.SGS transistors are the source terminals of NAND string The selection gridistor at place, and SGD transistor is the selection gridistor at the drain electrode end of NAND string.
In various embodiments, control circuit 810, state machine 812, decoder 814/824/832, power control module 816th, one or more of sensing block SB1, SB2 ..., SBp, read/write circuits 828 and controller 822 can be recognized For be at least one or more control circuit.
Piece outer controller 822 can include processor 822c and storage device (memory), such as, ROM822a and RAM 822b.Storage device includes the set that such as instructs of code, and processor 822c can be used to perform the set of the instruction with Functionality described here is provided.Alternatively or additionally, processor 822c can be accessed from memory construction (ratio Such as, the reservation region of the memory cell in one or more wordline) storage device 826a code.
In addition to NAND flash, other types of nonvolatile memory can also be used.
Semiconductor memory devices include volatile memory devices (such as dynamic random access memory (" DRAM ") or quiet State random access memory (" SRAM ")), non-volatile memory devices (such as resistive random access memory (" ReRAM "), Electrically Erasable Read Only Memory (" EEPROM "), flash memory (it can also be considered EEPROM subset), Ferroelectric RAM (" FRAM ") and magnetoresistive RAM (" MRAM ")) and be capable of storage information its His semiconductor element.Each type of memory devices can have different configurations.For example, flash memory device can be by It is configured to NAND or NOR configurations.
Memory devices can be formed by passive and/or active component with any combinations.Pass through the side of non-limiting example Formula, passive semiconductor memory component includes ReRAM equipment components, in certain embodiments, and the element includes such as antifuse Or the resistivity such as phase-change material switching memory element and (alternatively) such as diode or transistor actuation member.Further lead to The mode of non-limiting example is crossed, active semi-conductor memory component includes EEPROM and flash memory device element, one In a little embodiments, the element contains electric charge storage including such as floating boom, conductive nano-particles or charge storage dielectric material The element in region.
Multiple memory components are configured such that they are connected in series or so that each element is individually accessible 's.By way of non-limiting example, the flash memory device in NAND configurations (NAND flash) is generally comprised The memory component being connected in series.NAND string is the example of the set for the transistor being connected in series, the crystal being connected in series Pipe includes memory cell and selection gridistor.
NAND flash array is configured such that array is made up of multiple memory strings, wherein, string is by altogether The multiple memory components enjoyed single bit line and be accessed as group are constituted.Alternately, memory component can be configured To cause each element to be individually accessible (for example, NOR memory arrays).The configuration of NAND and NOR memories is example Property, and memory component can configure otherwise.
Semiconductor memery device in substrate and/or above it can be arranged at two or three dimensions (such as Two dimensional memory structure or three-dimensional memory structure) in.
In two dimensional memory structure, semiconductor memery device is arranged at single plane or single memory equipment level In.Generally, in two dimensional memory structure, memory component is arranged at the substrate for being arranged essentially parallel to support memory component Major surfaces and (for example, in x-y direction planes) in the plane that extends.Substrate can be formed above it or wherein The chip of memory element layer, or it can be that carrier substrates thereon are attached to after memory component is formed.As Non-limiting example, substrate can include such as silicon semiconductor.
Memory component can be arranged to oldered array in single memory equipment level, such as in multiple rows and/or In row.However, it is possible to arrange memory component in irregular or nonopiate configuration.Each storage element in memory component Part can have two or more electrodes or contact line, such as bit line and wordline.
3 D memory array is arranged so that memory component occupies multiple planes or multiple memory devices level, by This three dimensions (that is, on x directions, y directions and z directions, wherein, z directions are substantially perpendicular to and x and y directions are basic On parallel to substrate main surface) in formed structure.
As non-limiting example, three-dimensional memory structure can be vertically arranged to multiple two dimensional memory device levels Stacking.As another non-limiting example, 3 D memory array can be arranged to multiple vertical row (for example, basic On perpendicular to substrate main surface extend row, i.e. in y-direction), each column has multiple memory components.Can be in two dimension The row are arranged in configuration (for example, in an x-y plane), cause the three-dimensional arrangement of memory component, element is located at multiple vertical On the memory plane of stacking.Other configurations of the memory component in three dimensions can also constitute 3 D memory array.
By way of non-limiting example, in three dimensional NAND memory array, memory component can be coupling in Together, so as to the formation NAND string in single level (for example, x-y) memory devices level.Alternately, memory component can be with It is coupled together, to be developed across the vertical NAND string of multiple level memory device levels.It is contemplated that other three-dimensionals are matched somebody with somebody Put, wherein, some NAND strings include the memory component in single memory level, and other strings include and cross over multiple storage levels Memory component.3 D memory array can also be designed in NOR configurations and in ReRAM configurations.
Generally, it is square into one or more memory devices on a single substrate in monolithic three dimensional memory array Level.Alternatively, monolithic three dimensional memory array can also be one or more in single substrate with being at least partially situated at Memory layer.As non-limiting example, substrate can include such as silicon semiconductor.In monolithic three dimensional array, battle array is constituted The layer of each memory devices level of row is generally formed on the layer of the background memory device level of array.However, one chip three Tieing up the layer of the adjacent memory device level of memory array can be shared or there is intermediate layer between memory devices level.
Then, again, two-dimensional array can be formed separately and be then enclosed in together, to be formed with many The non-slice memory equipment of individual memory layer.For example, non-one chip stacked memory can be by independent grade slab Form storage level and then be stacked on storage level on top of each other to construct.Can be with organic semiconductor device or can be before stacking It is removed from memory devices level, but because memory devices grade primitively on a separate substrate it is square into, Produced memory array is not monolithic three dimensional memory array.In addition, multiple two dimensional memory arrays or three-dimensional storage Device array (one chip or non-one chip) can be formed on single piece to be then enclosed in together, to form stacked chips Memory devices.
The operation of memory component and usually require associated circuit with the communication of memory component.As unrestricted Property example, memory devices can have be used for control and drive memory component complete such as programming and reading function electricity Road.This associated circuit can be located at on memory component identical substrate and/or on single substrate.For example, It can be located on single controller piece and/or be located at and memory component for the controller that memory read-write is operated On identical substrate.
Fig. 7 depicts the viewgraph of cross-section of the block with the 3D non-volatile memory devices directly gone here and there.Described piece comprising more Individual non-volatile memory device.This is can to use an example in memory array in fig. 6b.Stack 777 and include conduction The alternating layer of (SGS, WL0-WL5 and SGD) layer and insulation (D0-D8) layer.Conductive layer can be tungsten, highly doped silicon etc..Insulating barrier It can be silicon nitride etc..The row of the memory cell corresponding with NAND string NSB0 to NSB5 are depicted in multiple-level stack.Heap Folded 777 include a part for substrate 801, the dielectric film 709 on substrate and source electrode line SLB0.NAND string NSB0 to NSB5 is each In different sub-blocks, but in the NAND string of common set.NSB0 has source terminal 603 and drain electrode end 701.Also retouch Gap 702 and other gaps are painted.Gap can be formed by the insulator of such as silica.It further depict one of bit line BLB0 Point.Dotted line depicts memory cell and selection grid.Memory cell is located in layer WL0-WL5.Grid is selected to be located at layer SGS In SGD.
In various embodiments, it is coupled to calibration node and can for supply the variable impedance proportional to input code Impedance device can include variable impedance circuit 104, variable impedance circuit 104a, variable impedance circuit 104b, multiple crystal Pipe 402, multiple transistors 422 and/or other hardware.Other embodiment can include being used for supplying it is proportional to input code can The similar or equivalent device of impedance.
In various embodiments, for modulate possess the voltage at the calibrating resistor of the resistance with positive temperature coefficient with Just the positive temperature coefficient of calibrating resistor is substantially eliminated to cause by the temperature independent voltage of the electric current of calibrating resistor Modulating device can include voltage modulation circuit 232, reference voltage circuit 236, IPTATSource 201, resistor 206 and 212, computing Amplifier 202 and 216 and transistor 204,208,210 and 218, operational amplifier 214, transistor 222 and/or other are hard Part.IPTATSource 201 can include operational amplifier 240, PMOS transistor 248, PMOS transistor 250, PMOS transistor 252, RPTATResistor 242, diode 244 and diode 246.Other embodiment can include possessing with positive temperature for modulation Voltage at the calibrating resistor of the resistance of coefficient is to substantially eliminate the positive temperature coefficient of calibrating resistor to cause process The temperature independent similar or equivalent device of the electric current of calibrating resistor.
In various embodiments, for providing temperature independent reference to calibration node based on the electric current by calibrating resistor The temperature independent reference electric current of electric current provides device can be including calibrating resistor on temperature independent reference current circuit 234, piece 110th, transistor 222 and 224, temperature independent reference current generating circuit 106, transmitting circuit (for example, current mirror) 279, crystal Pipe 262, transistor 260 and/or other hardware.Other embodiment can include be used for based on by calibrating resistor electric current to Calibrate the similar or equivalent device that node provides temperature independent reference electric current.
In various embodiments, for being compared to calibration voltage and reference voltage to judge that calibration voltage is less than also Comparator 108, operational amplifier and/or other hardware can be included by being greater than the comparison means of reference voltage.Other embodiment It can include being used to be compared to judge that calibration voltage is less than also being greater than reference voltage calibration voltage and reference voltage Similar or equivalent device.
In various embodiments, changed for being less than also being greater than reference voltage in response to calibration voltage to can variable resistance The input code modification device of the input code of anti-device can include calibration logic 102, processor 822c, state machine 812, be stored in Code, storage device 826a and/or other hardware in ROM 822a and RAM 822B.Other embodiment can include being used to respond It is less than also being greater than temperature independent reference electric current in the calibration voltage and changes defeated to the calibration current supply device Enter the similar or equivalent device of code.
Other embodiment disclosed herein includes a kind of device, and described device includes the dress of reference current generative circuit Put, the reference current generative circuit be configured for based on the electric current by the calibrating resistor on integrated circuit come Generate temperature independent reference electric current and for providing the temperature independent reference electric current to calibration node.Described device is further Including variable impedance circuit and comparator, the variable impedance circuit is coupled to calibration node, and comparator has and is coupled to Calibrate the first input end of node and be coupled to the second input of reference voltage.
In one embodiment, the described device in the last period further comprises reference voltage circuit, the reference voltage Circuit is configured for providing the voltage for being substantially equal to reference voltage to the first terminal of calibrating resistor.Described device is entered One step includes voltage modulation circuit, and the voltage modulation circuit is coupled to the Second terminal of the calibrating resistor, wherein, The voltage modulation circuit is configured for modulating voltage at the Second terminal of the calibrating resistor so as to basic The upper temperature coefficient for eliminating the calibrating resistor, wherein, the electric current by the calibrating resistor is temperature independent.Institute State device and further comprise temperature independent reference current circuit, the temperature independent reference current circuit is configured for from warp Temperature independent reference electric current is obtained in the temperature independent current for crossing calibrating resistor.
In one embodiment, the reference current generative circuit of the device described in the either segment in first two sections is configured to use It is substantially equal to the reference voltage divided by the variable impedance circuit in the temperature independent reference electric current to be generated as having The size for the target resistance (RT) being just calibrated to.
In one embodiment, the device described in the either segment in first three section further comprises logic, the logic by with Be set to for changed in response to the signal exported by the comparator the impedance of the variable impedance circuit so as to Perform ZQ calibrations.
One embodiment disclosed herein includes a kind of method, and methods described includes：To the first end of calibrating resistor Son supply reference voltage, the calibrating resistor possesses the resistance with positive temperature coefficient, wherein, the calibrating resistor is located at On integrated circuit；Offset voltage of the generation with negative temperature coefficient；Described mend is provided to the Second terminal of the calibrating resistor Voltage is repaid, wherein, the offset voltage substantially eliminates the positive temperature coefficient of the calibrating resistor, wherein, pass through institute Stating the electric current of calibrating resistor has temperature independent size；Temperature independent reference electric current, the temperature are provided to calibration node The electric current of the independent reference electric current reflection by the calibrating resistor is spent, wherein, the temperature independent reference electric current is based on Reference voltage and the target alignment resistance；There is provided calibration signal the variable impedance circuit is changed to variable impedance circuit Become its impedance；Calibration voltage at the calibration node is compared with the reference voltage；And based on to the calibration Result that voltage and the reference voltage are compared adjusts the calibration signal.
One embodiment disclosed herein includes non-volatile memory device, and the non-volatile memory device includes many Individual non-volatile memory device, reference current generative circuit, variable impedance circuit, comparator and calibration circuit.Reference current Generative circuit includes the calibrating resistor with the first terminal and Second terminal.The first terminal is coupled to offer first voltage Voltage source.The resistance of the calibrating resistor has positive temperature coefficient.The reference current generative circuit is configured for The second voltage at the Second terminal of the calibrating resistor is modulated to eliminate the positive temperature system of the calibrating resistor Number, so that temperature independent by the electric current of the calibrating resistor.The reference current generative circuit is configured to use In the electric current based on process calibrating resistor temperature independent reference electric current is provided to calibration node.The variable impedance circuit coupling Close the calibration node.The comparator has the first input end for being coupled to the calibration node and is coupled to offer ginseng Examine the second input of the node of voltage.The comparator is configured for calibrating the calibration electricity at node described in output indication Pressure is greater than also being less than the signal of reference voltage.The calibration circuit is configured for being greater than based on instruction calibration voltage The signal of reference voltage is also less than to change the impedance of variable impedance circuit.
One embodiment disclosed herein includes a kind of non-volatile memory device, the non-volatile memory device bag 3 D memory array is included, the 3 D memory array includes multiple non-volatile memory devices, calibrating resistor, with reference to electricity Flow generative circuit, variable impedance circuit and comparator.The calibrating resistor possesses the resistance with positive temperature coefficient, its In, the calibrating resistor has the first terminal for being coupled to the first reference voltage and the second reference voltage.The reference current Generative circuit is configured for offset voltage of the generation with negative temperature coefficient.The reference current generative circuit can be with It is configured for providing offset voltage to the Second terminal of calibrating resistor, wherein, due to the first reference voltage and compensation electricity Pressure, the electric current flowed in calibrating resistor is temperature independent.The reference current generative circuit is configured for base Come to provide temperature independent reference electric current to calibration node in the electric current flowed in calibrating resistor.The variable impedance circuit coupling Close the calibration node.The comparator has the first input end for being coupled to calibration node and is coupled to reference voltage Second input.The comparator is configured in response to the calibration voltage and described second at the calibration node The comparison of reference voltage and output signal.
It would be recognized by those skilled in the art that this technology is not limited to described two and three dimensions example arrangement, but cover All correlations covered in the spirit and scope of this technology as described herein and as will be understood by those of ordinary skill in the art Memory construction.The discussed in detail above of the present invention is provided for purposes of illustration and description.It is not intended to exhaustive or limitation The present invention arrives disclosed precise forms.It is possible according to many modifications and variations of teachings above.In order to best explain this The principle and its practical application of invention, have chosen described embodiment, so that those skilled in the art can be with each Embodiment and the present invention is most preferably utilized suitable for the various modifications of special-purpose expected.It is intended to allow the model of the present invention Enclose and be defined by the following claims.

Claims (20)

1. a kind of device, including：
Reference current generative circuit, the reference current generative circuit is configured to based on by the calibration on integrated circuit The electric current of resistor generates temperature independent reference electric current and provides the temperature independent reference electric current to calibration node；
Variable impedance circuit, the variable impedance circuit is coupled to the calibration node；And
Comparator, the comparator has the first input end for being coupled to the calibration node and is coupled to the of reference voltage Two inputs.
2. device as claimed in claim 1, wherein, the calibrating resistor has the first terminal and Second terminal, wherein, institute Stating the resistance of calibrating resistor has temperature coefficient, wherein, the reference current generative circuit includes：
Reference voltage circuit, the reference voltage circuit is configured to provide base to the first terminal of the calibrating resistor It is equal to the voltage of the reference voltage in sheet；
Voltage modulation circuit, the voltage modulation circuit is coupled to the Second terminal of the calibrating resistor, wherein, it is described Voltage modulation circuit is configured to modulate the voltage at the Second terminal of the calibrating resistor to substantially eliminate The temperature coefficient of calibrating resistor is stated, wherein, the electric current by the calibrating resistor is temperature independent；And
Temperature independent reference current circuit, the temperature independent reference current circuit is configured to from by the calibrating resistor The temperature independent current in obtain the temperature independent reference electric current.
3. device as claimed in claim 2, wherein, the temperature coefficient of the calibrating resistor is positive temperature coefficient, its In, the resistance of the calibrating resistor increases with the rise of temperature, wherein, the voltage modulation circuit is configured to Reduce the voltage at the Second terminal of the calibrating resistor with the rise of temperature.
4. device as claimed in claim 1, wherein, the calibrating resistor has the first terminal and Second terminal, wherein, institute Stating the resistance of calibrating resistor has temperature coefficient, wherein, the reference current generative circuit includes：
Reference voltage circuit, the reference voltage circuit is configured to provide base to the first terminal of the calibrating resistor It is equal to the voltage of the reference voltage in sheet；
Temperature dependent voltage generative circuit, the temperature dependent voltage generative circuit is coupled to described the of the calibrating resistor Two-terminal, wherein, the temperature dependent voltage generative circuit is configured at the Second terminal generate voltage, the voltage Temperature coefficient with the temperature coefficient for being configured to substantially eliminate the calibrating resistor；And
Temperature independent reference current circuit, the temperature independent reference current circuit is configured to be based on by the calibrating resistance The electric current of device provides the temperature independent reference electric current to the calibration node.
5. device as claimed in claim 4, wherein, the temperature coefficient of the calibrating resistor is positive temperature coefficient, its In, the resistance of the calibrating resistor increases with the rise of temperature, wherein, the voltage at the Second terminal The temperature coefficient be negative temperature coefficient, wherein, the voltage at the Second terminal of the calibrating resistor with The rise of temperature and reduce.
6. device as claimed in claim 4, wherein, the temperature dependent voltage generative circuit includes：
Voltage modulated resistor, the voltage modulated resistor is with the Second terminal for being coupled to the calibrating resistor Node；And
With the circuit of temperature proportional, described and temperature proportional circuit is configured to provide by the voltage modulated resistance The electric current with temperature proportional of device.
7. device as claimed in claim 6, wherein, it is described to be configured to set up the electric current with temperature proportional circuit With the size of temperature proportional, so as to the institute at the node being coupled in the Second terminal of the calibrating resistor State voltage to be modulated, so as to substantially eliminate the temperature coefficient of the calibrating resistor.
8. device as claimed in claim 1, wherein, the reference current generative circuit is configured to the unrelated ginseng of the temperature Examine electric current and be generated as having and be substantially equal to the target electricity that the reference voltage divided by the variable impedance circuit are just being calibrated to The size of resistance.
9. device as claimed in claim 1, wherein, the comparator is configured for calibrating at node described in output indication Voltage be greater than also being less than the signal of the reference voltage, and described device further comprises logic, the logic quilt It is configured to indicate the signal that the voltage at the calibration node is greater than also being less than the reference voltage And change the impedance of the variable impedance circuit.
10. device as claimed in claim 9, further comprises logic, the logic is configured in response to by the comparison Device output the signal and change the impedance of the variable impedance circuit so as to perform ZQ calibration.
11. device as claimed in claim 1, wherein, the calibrating resistor has the first terminal and Second terminal, wherein, The resistance of the calibrating resistor has negative temperature coefficient, wherein, the reference current generative circuit includes：
Reference voltage circuit, the reference voltage circuit is configured to provide base to the first terminal of the calibrating resistor It is equal to the voltage of the reference voltage in sheet；
Voltage modulation circuit, the voltage modulation circuit is coupled to the Second terminal of the calibrating resistor, wherein, it is described Voltage modulation circuit is configured to modulate the voltage at the Second terminal of the calibrating resistor to substantially eliminate The negative temperature coefficient of calibrating resistor is stated, wherein, the electric current by the calibrating resistor is temperature independent；And
Temperature independent reference current circuit, the temperature independent reference current circuit is configured to from by the calibrating resistor The temperature independent current in obtain the temperature independent reference electric current.
12. device as claimed in claim 1, further comprises：
3 D memory array, the 3 D memory array includes multiple non-volatile memory devices.
13. a kind of non-volatile memory device, including：
Multiple non-volatile memory devices；
Reference current generative circuit, the reference current generative circuit includes the calibrating resistance with the first terminal and Second terminal Device, wherein, the first terminal is coupled to the voltage source for providing first voltage, wherein, the resistance of the calibrating resistor has Positive temperature coefficient, wherein, the reference current generative circuit is configured to modulate the Second terminal of the calibrating resistor The second voltage at place is to eliminate the positive temperature coefficient of the calibrating resistor so that by the calibrating resistor Electric current it is temperature independent, wherein, the reference current generative circuit be configured to based on by the calibrating resistor institute State electric current and provide temperature independent reference electric current to calibration node；
Variable impedance circuit, the variable impedance circuit is coupled to the calibration node；
Comparator, the comparator has the first output end for being coupled to the calibration node and is coupled to offer reference voltage Node the second output end, wherein, the comparator be configured to described in output indication calibrate node at calibration voltage is Above or below the signal of the reference voltage；And
Circuit is calibrated, the calibration circuit is configured to be greater than also based on the calibration voltage at the instruction calibration node The signal of the reference voltage is less than to change the impedance of the variable impedance circuit.
14. non-volatile memory device as claimed in claim 13, wherein, the first voltage is equal to the ginseng in size Examine voltage.
15. non-volatile memory device as claimed in claim 13, wherein, the variable impedance circuit include input and Multiple transistors of the calibration node are coupled to, wherein, the variable impedance circuit is configured to selection transistor to repair Change the size of the calibration voltage, wherein, the variable impedance circuit is configured to the calibration node output equal to described The calibration electric current of temperature independent reference electric current.
16. non-volatile memory device as claimed in claim 13, wherein, the reference current generative circuit is further wrapped Include：
With PTAT (PTAT) circuit, the PTAT circuit is configured for generating PTAT current, wherein, it is described Reference current generative circuit is configured to modulate based on the PTAT current at the Second terminal of the calibrating resistor The second voltage.
17. non-volatile memory device as claimed in claim 16, wherein, the reference current generative circuit is further wrapped Include：
Voltage modulated resistor, the voltage modulated resistor is with the Second terminal for being coupled to the calibrating resistor Node；
Wherein, the reference current generative circuit is configured to provide to the voltage modulated resistor based on the PTAT current Electric current, to generate described in being coupled in the Second terminal of the calibrating resistor of the voltage modulated resistor Temperature dependent voltage on node, wherein, the reference current generative circuit is configured to described in the calibrating resistor Second terminal provides the temperature dependent voltage, to eliminate the positive temperature coefficient of the calibrating resistor.
18. a kind of method, including：
Reference voltage is supplied to the first terminal of calibrating resistor, the calibrating resistor possesses the electricity with positive temperature coefficient Resistance, wherein, the calibrating resistor is located on integrated circuit；
Offset voltage of the generation with negative temperature coefficient；
The offset voltage is provided to the Second terminal of the calibrating resistor, wherein, the offset voltage substantially eliminates institute The positive temperature coefficient of calibrating resistor is stated, wherein, there is the unrelated size of temperature by the electric current of the calibrating resistor；
Temperature independent reference electric current is provided to calibration node, the temperature independent reference electric current reflection passes through the calibrating resistor The electric current, wherein, the temperature independent reference electric current be based on the reference voltage and target alignment resistance；
Calibration signal is provided to cause the variable impedance circuit to change its impedance to variable impedance circuit, wherein, it is described variable Impedance circuit is equal to the calibration electric current of the temperature independent reference electric current to the calibration node output；
Calibration voltage at the calibration node is compared with the reference voltage；And
The calibration signal is adjusted based on the result being compared to the calibration voltage and the reference voltage.
19. method as claimed in claim 18, wherein, it is described to be based on comparing the calibration voltage with the reference voltage Compared with the result include to adjust the calibration signal：
Perform ZQ calibrations.
20. method as claimed in claim 18, wherein, the offset voltage of the generation with negative temperature coefficient includes：
Generation and the electric current of PTAT (PTAT)；And
The offset voltage is generated based on the PTAT current.
CN201710142405.2A 2016-03-28 2017-03-10 Temperature independent reference electric current for calibration generates Active CN107239092B (en)

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