CN107231154A - The shared pipeline stages circuit structure of multimode for low-power consumption assembly line ADC - Google Patents
The shared pipeline stages circuit structure of multimode for low-power consumption assembly line ADC Download PDFInfo
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- CN107231154A CN107231154A CN201710351187.3A CN201710351187A CN107231154A CN 107231154 A CN107231154 A CN 107231154A CN 201710351187 A CN201710351187 A CN 201710351187A CN 107231154 A CN107231154 A CN 107231154A
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- electric capacity
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- latch
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
- H03M1/145—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit the steps being performed sequentially in series-connected stages
Abstract
The invention discloses a kind of shared pipeline stages circuit structure of the multimode for low-power consumption assembly line ADC, wherein, the first multiplication digital-to-analogue unit MDAC1 and the electric capacity C of the second multiplication digital-to-analogue unit MDAC2 time-sharing multiplexs the 3rdf1, the 4th electric capacity Cf2With the first amplifier OPA；Sub_ADC1 and sub_ADC2 time-sharing multiplexs Latch1 and Latch2；When clock phase Φ 1 is high level, Cf1To datum Vdac2Sampled, Cf2As feedback capacity and OPA realize the subtracting each other of MDAC2, the amplification of remainder, redundancy function；When clock phase Φ 2 is high level, Cf1And Cf2The subtracting each other of MDAC1, remainder, redundancy enlarging function are realized as MDAC1 feedback capacity and OPA, meanwhile, Cf1And Cf2As MDAC2 sampling capacitance, MDAC2 sampling operation is completed；Latch1 and Latch2 realizes the comparison of sub_ADC1 input signals and reference threshold when clock phase Φ 1 is high level；When clock phase Φ 2 is high level, the comparison of sub_ADC2 input signals and reference threshold is realized.The present invention can reduce the power consumption of pipeline ADC, improve conversion accuracy.
Description
Technical field
The present invention relates to analog-digital converter field, a kind of more particularly to multimode for low-power consumption assembly line ADC is shared
Type pipeline stages circuit structure.
Background technology
With developing rapidly for semiconductor technology, A/D converter with high speed and high precision is widely used to digital communication, army
The fields such as thing radar.Production line analog-digital converter (Pipeline ADC), can be fine as one of ADC products of current main flow
The requirement for taking into account speed and precision.In production line analog-digital converter, single pipeline stages circuit as important component,
Determine the performance of whole production line analog-digital converter.
In traditional low-power consumption assembly line ADC, share to reduce power consumption using Op-amp sharing, electric capacity, but due to amplifier,
, there is memory effect and stability problem in the continuous work of electric capacity, cause the reduction of ADC precision, simultaneously as Op-amp sharing, electricity
Hold the speed that the shared switch introduced then limits ADC；Another solution is to use switched-OPAMP technology, but switched-OPAMP
There is the unlatching that problem is each clock phase amplifier, shut-off operation in the pipeline ADC of structure, can limit system speed.Meanwhile,
The different clocks phase opened, turned off to pipe is inputted, amplifier input capacitance is different, causes amplifier feedback factor, the change of gain.
The content of the invention
Technical problem：In order to overcome the deficiencies in the prior art, the present invention proposes a kind of fortune of three phase clock control
The shared pipeline stages circuit structure of multimode that shared, electric capacity is shared, comparator is shared is put, to reduce operation amplifier in circuit
The number of device and comparator, reduces system power dissipation.
Technical scheme：To achieve the above object, the technical solution adopted by the present invention is：
A kind of shared pipeline stages circuit structure of multimode suitable for low-power consumption assembly line ADC, including the first multiplication
ADC (sub_ADC1), second multiplication digital-to-analogue unit (MDAC2) ADC between the second level between digital-to-analogue unit (MDAC1), the first order
(sub_ADC2)；The first multiplication digital-to-analogue unit (MDAC1) and the electricity of second multiplication digital-to-analogue unit (MDAC2) time-sharing multiplex the 3rd
Hold (Cf1), the 4th electric capacity (Cf2) and the first amplifier (OPA)；ADC (sub_ADC1) ADC between the second level between the first order
(sub_ADC2) Latch (Latch1) of time-sharing multiplex the first and the 2nd Latch (Latch2)；
When clock phase Φ 1 is high level, the 3rd electric capacity (Cf1) to datum Vdac2Sampled, the 4th electric capacity
(Cf2) modular unit of the second multiplication digital-to-analogue unit (MDAC2) is used as with first amplifier (OPA) as feedback capacity, realize
The subtracting each other of second multiplication digital-to-analogue unit (MDAC2), the function of remainder, redundancy amplification；It is described when clock phase Φ 2 is high level
3rd electric capacity (Cf1) and the 4th electric capacity (Cf2) it is used as feedback capacity and the described first fortune of the first multiplication digital-to-analogue unit (MDAC1)
Put (OPA) and realize the subtracting each other of the first multiplication digital-to-analogue unit (MDAC1), remainder, redundancy enlarging function together, meanwhile, the 3rd electric capacity
(Cf1) and the 4th electric capacity (Cf2) as the sampling capacitance of the second multiplication digital-to-analogue unit (MDAC2), complete the second multiplication digital-to-analogue unit
(MDAC2) sampling operation；When clock phase Φ a are high level, the 3rd electric capacity (Cf1) and the 4th electric capacity (Cf2), first
Amplifier (OPA) carries out reset operation, to eliminate memory effect；
First Latch (Latch1) and the 2nd Latch (Latch2) are used as the when clock phase Φ 1 is high level
ADC (sub_ADC1) comparator, realizes the comparison of input signal and reference threshold between one-level；When clock phase Φ 2 is high level,
As ADC between the second level (sub_ADC2) comparator, the comparison of input signal and reference threshold is realized；It is in clock phase Φ a1
During high level, reset operation is carried out；
There is high level in the clock phase Φ a, the clock phase Φ a1 are in clock phase before the arrival of the rising edges of clock phase Φ 2
All there is high level before arriving in Φ 1, the rising edges of clock phase Φ 2.
In a specific embodiment, the first multiplication digital-to-analogue unit (MDAC1) includes the first electric capacity (Cs1), second electricity
Hold (Cs2), the 3rd electric capacity (Cf1), the 4th electric capacity (Cf2), first switch (S1), second switch (S2), the 5th switch (S5), the tenth
Six switches (S16), the 17th switch (S17), the 22nd switch (S22), the 23rd switch (S23), the 24th switch
(S24), the 25th switch (S25), the first coding circuit (Decoder1), thirty-twomo close (S32), the 33rd switch
And the first amplifier (OPA) (S33)；
The second multiplication digital-to-analogue unit (MDAC2) includes the 3rd electric capacity (Cf1), the 4th electric capacity (Cf2), the 8th switch
(S8), the 13rd switch (S13), the 14th switch (S14), the 15th switch (S15), the 22nd switch (S22), second are compiled
Code circuit (Decoder2), the first amplifier (OPA)；
Wherein, the first electric capacity (Cs1) right pole plate and the second electric capacity (Cs2) right pole plate is connected, and switch (S5) upper end with the 5th
And the 25th switch (S25) left end point be connected, left pole plate connects first switch (S1) right endpoint and the 24th switch (S24)
Right endpoint；First switch (S1) left end point and input signal VinIt is connected and is connected with second switch (S2)；24th switch
(S24) left side is connected with ground level；Second electric capacity (Cs2) left side with the right side of second switch (S2), the 23rd switch (S23) is right
Side is connected, and datum V is met on the left of the 23rd switch (S23)dac1；3rd electric capacity (Cf1) and the 4th electric capacity (Cf2) left side and the
Sixteenmo is closed on the upside of (S16) and is connected on the right side of the 25th switch (S25), and is connected with the first amplifier (OPA) negative input end；The
Sixteenmo, which is closed, to be connected with ground level and is connected with the first amplifier (OPA) positive input terminal on the downside of (S16)；3rd electric capacity (Cf1) right side with
It is connected on the left of 22nd switch (S22) and on the left of the 15th switch (S15), the 4th electric capacity (Cf2) right side with the 22nd switch
(S22) it is connected on the left of right side and the 17th switch (S17) upside and the 8th switch (S8), while being exported with the first amplifier (OPA)
End is connected；The state of the switch (S23) of first coding circuit (Decoder1) output end control the 23rd；First coding circuit
(Decoder1) working condition closes (S32) control by the 33rd switch (S33), thirty-twomo；
Connect on the right side of 8th switch (S8) and meet datum V on the right side of third level input, the 15th switch (S15)dac2, the
15 switch (S15) controls terminate the second coding circuit (Decoder2) output, the second coding circuit (Decoder2) by
13rd switch (S13) and the 14th switch (S14) control；
First switch (S1), second switch (S2), the 8th switch (S8), the 13rd switch (S13) and the 14th switch
(S14) controlled by clock phase Φ 1, the 22nd switch (S22) clock phase Φ 1 inversion clock control, the 24th switch
(S24), the 25th switch (S25), the 33rd switch (S33) and thirty-twomo close (S32) and controlled by clock phase Φ 2,
Sixteenmo closes (S16) and the 17th switch (S17) by clock phase ΦaControl, the 5th switch (S5) is controlled by clock phase Φ 1E；
Wherein, clock phase Φ 1E trailing edge shifts to an earlier date than the trailing edges of clock phase Φ 1.
In a specific embodiment, ADC (sub_ADC1) includes the 3rd switch (S3), the 4th switch between the first order
(S4), the 6th switch (S6), the 7th switch (S7), eighteenmo close (S18), the 19th switch (S19), the 20th switch
(S20), the 21st switch (S21), the second sixteenmo close (S26), the 27th switch (S27), the 5th electric capacity (Csc11),
Six electric capacity (Csc12), the first Latch (Latch1) and the 2nd Latch (Latch2)；
ADC (sub_ADC2) includes the 9th switch (S9), the tenth switch (S10), the 11st switch between the second level
(S11), the 12nd switch (S12), the second eighteenmo close (S28), the 29th switch (S29), the 30th switch (S30), the
31 switches (S31), the 7th electric capacity (Csc21), the 8th electric capacity (Csc22), the first Latch (Latch1) and the 2nd Latch
(Latch2)；
5th electric capacity (Csc11) left side on the upside of on the right side of the 3rd switch (S3) and eighteenmo pass (S18) with being connected, the 18th
Switch side joint threshold voltage vt h1 under (S18)；It is connected on the left of 3rd switch (S3) with the left of the 4th switch (S4), and connects input letter
Number；5th electric capacity (Csc11) on the right side of connect the upside of the 6th switch (S6), and with preventing big device 1 (pre1) input to be connected, in advance
Prevent that big (pre1) output end of device 1 is closed with the second sixteenmo on the left of (S26) to be connected, the second sixteenmo closes and connects first on the right side of (S26)
Latch (Latch1) input, the first Latch (Latch1) is resetted by the 20th switch (S20) control；6th electric capacity (Csc12)
Left side is connected with the right side of the 4th switch (S4) and on the upside of the 19th switch (S19), side joint threshold voltage under the 19th switch (S19)
Vth2；6th electric capacity (Csc12) on the right side of connect the upside of the 7th switch (S7), and with preventing big device 2 (pre2) input to be connected,
Prevent big (pre2) output end of device 2 to switch with the 27th on the left of (S27) to be connected, second is connect on the right side of the 27th switch (S27)
Latch (Latch2) input, the 2nd Latch (Latch2) is resetted by the 21st switch (S21) control；
Second eighteenmo closes to switch with the 29th on the right side of (S28) to be connected on the right side of (S29), and connects the first amplifier (OPA)
Output end, the second eighteenmo is closed switchs (S10) upside and the 7th electric capacity (C with the tenth on the left of (S28)sc21) right side be connected, the 7th
Electric capacity (Csc21) left side on the right side of the 30th switch (S30) upside and the 12nd switch (S12) with being connected, the 12nd switch (S12)
Left side connects the first Latch (Latch1) input；With the 9th switch (S9) upside and the 8th on the left of 29th switch (S29)
Electric capacity (Csc22) right side be connected, the 8th electric capacity (Csc22) left side is switched with the 31st on the upside of (S31) and the 11st switchs (S11)
Right side is connected, and the 2nd Latch (Latch2) input is connect on the left of the 11st switch (S11)；
3rd switch (S3), the 4th switch (S4), the 9th switch (S9), the tenth switch (S10), the 11st switch (S11)
Controlled with the 12nd switch (S12) by clock phase Φ 1, the second sixteenmo closes (S26), the 27th switch (S27), the 28th
Switch (S28) and the 29th switch (S29) are controlled by clock phase Φ 2, and eighteenmo closes (S18) and the 19th switch (S19)
By clock phase Φ a control, the 6th switch (S6) and the 7th switch (S7) by clock phase Φ 1E control, the 30th switch (S30) and
31st switch (S31) is controlled by clock phase Φ 2E, and the 20th switch (S20) and the 21st switch (S21) are by clock phase
Φ a1 are controlled；Wherein, clock phase Φ 1E trailing edge shifts to an earlier date than the trailing edges of clock phase Φ 1, during clock phase Φ 2E trailing edge ratio
The trailing edges of clock phase Φ 2 shift to an earlier date.
Beneficial effect：Op-amp sharing, the electricity for the three phase clock control suitable for low-power consumption assembly line ADC that the present invention is designed
Hold the shared shared pipeline stages circuit structure of multimode of shared, comparator, by the introducing of three phase clock, realize first
MDAC (MDAC1) between sample path and the first order ADC (sub_ADC1) sample path match completely, eliminate aperture error, and solve
Certainly the memory effect problem in Op-amp sharing and the shared design of electric capacity, improves system accuracy.Meanwhile, the reality of multimode shared structure
Now so that operational amplifier number and comparator number halve in preceding two-stage pipeline stages circuit, system power dissipation is reduced, is realized
Low power dissipation design, it is adaptable to low-power consumption assembly line ADC.
Brief description of the drawings
Fig. 1 is the circuit diagram of the embodiment of the present invention；
Fig. 2 be the embodiment of the present invention in three phase clock circuit diagram；
Fig. 3 is the working timing figure of embodiment of the present invention when clock phase Φ 1 is high level；
Fig. 4 is the working timing figure of embodiment of the present invention when clock phase Φ a are high level；
Fig. 5 is the working timing figure of embodiment of the present invention when clock phase Φ 2 is high level.
Embodiment
Below in conjunction with the accompanying drawings and embodiment, detailed description technical scheme.
A kind of shared pipeline stages circuit knot of multimode for low-power consumption assembly line ADC disclosed in the embodiment of the present invention
Structure, ADC (sub_ADC1), the second multiplication digital-to-analogue unit (MDAC2), between the first multiplication digital-to-analogue unit (MDAC1), the first order
ADC (sub_ADC2) is constituted between two grades.Wherein, the first multiplication digital-to-analogue unit (MDAC1) and the second multiplication digital-to-analogue unit (MDAC2)
Electric capacity (the C of time-sharing multiplex the 3rdf1), the 4th electric capacity (Cf2) and the first amplifier (OPA)；ADC (sub_ADC1) and second between the first order
The Latch (Latch1) and the 2nd Latch (Latch2) of ADC (sub_ADC2) time-sharing multiplex the first between level, passes through three phase clock
The time-sharing multiplex of shared device is realized in control.When the first clock phase Φ 1 is high level, the 3rd electric capacity (Cf1) to datum
Vdac2Sampled, the 4th electric capacity (Cf2) as feedback capacity and the first amplifier (OPA) it is used as the second multiplication digital-to-analogue unit
(MDAC2) modular unit, realizes the subtracting each other of the second multiplication digital-to-analogue unit (MDAC2), the function of remainder, redundancy amplification；
When two clock phase Φ 2 are high level, the 3rd electric capacity (Cf1) and the 4th electric capacity (Cf2) it is used as the first multiplication digital-to-analogue unit (MDAC1)
Feedback capacity the subtracting each other of the first multiplication digital-to-analogue unit (MDAC1), the amplification of remainder, redundancy are realized together with the first amplifier (OPA)
Function, meanwhile, the 3rd electric capacity (Cf1) and the 4th electric capacity (Cf2) as the sampling capacitance of the second multiplication digital-to-analogue unit (MDAC2), it is complete
Into the sampling operation of the second multiplication digital-to-analogue unit (MDAC2)；First Latch (Latch1) and the 2nd Latch (Latch2) is
When one clock phase Φ 1 is high level, as ADC between the first order (sub_ADC1) comparator, input signal and reference threshold are realized
Comparison；When second clock phase Φ 2 is high level, as ADC between the second level (sub_ADC2) comparator, input letter is realized
Comparison number with reference threshold；Shared device carries out reset operation under the control of the 3rd clock phase, to eliminate memory effect.
During Fig. 1 is the circuit structure diagram of a specific embodiment of the invention, such as Fig. 1, the first multiplication digital-to-analogue unit (MDAC1) includes first
Electric capacity (Cs1), the second electric capacity (Cs2), the 3rd electric capacity (Cf1), the 4th electric capacity (Cf2), first switch (S1), second switch (S2),
Five switches (S5), sixteenmo close (S16), the 17th switch (S17), the 22nd switch (S22), the 23rd switch
(S23), the 24th switch (S24), the 25th switch (S25), the first coding circuit (Decoder1), thirty-twomo are closed
(S32), the 33rd switch (S33), the first amplifier (OPA).Wherein, the first electric capacity (Cs1) right pole plate and the second electric capacity (Cs2)
Right pole plate is connected, and is connected with the 5th switch (S5) upper end and the 25th switch (S25) left end point, and left pole plate connects first switch
(S1) right endpoint of right endpoint and the 24th switch (S24).First switch (S1) left end point and input signal VinBe connected and with
Second switch (S2) is connected.It is connected on the left of 24th switch (S24) with ground level.Second electric capacity (Cs2) left side and second switch
(S2) it is connected on the right side of right side, the 23rd switch (S23), V is met on the left of the 23rd switch (S23)dac1.3rd electric capacity (Cf1) and
4th electric capacity (Cf2) left side with sixteenmo close (S16) on the upside of and the 25th switch (S25) right side be connected, and with the first amplifier
(OPA) negative input end is connected.Sixteenmo close (S16) on the downside of be connected with ground level and with the first amplifier (OPA) positive input terminal phase
Even.3rd electric capacity (Cf1) right side on the left of the 22nd switch (S22) left side and the 15th switch (S15) with being connected, the 4th electric capacity
(Cf2) right side on the left of the 22nd switch (S22) right side and the 17th switch (S17) upside and the 8th switch (S8) with being connected, together
When be connected with the first amplifier (OPA) output end.The switch (S23) of first coding circuit (Decoder1) output end control the 23rd
State.First coding circuit (Decoder1) working condition closes (S32) control by the 33rd switch (S33), thirty-twomo
System, and switch opposite side is connected respectively at the first Latch (Latch1), the 2nd Latch (Latch2).
ADC (sub_ADC1) includes the 3rd switch (S3), the 4th switch (S4), the 6th switch (S6), the 7th between the first order
Switch (S7), eighteenmo and close (S18), the 19th switch (S19), the 20th switch (S20), the 21st switch (S21), the
Two sixteenmos close (S26), the 27th switch (S27), the 5th electric capacity (Csc11), the 6th electric capacity (Csc12), the first Latch
(Latch1), the 2nd Latch (Latch2).
Wherein, the 5th electric capacity (Csc11) left side on the upside of eighteenmo pass (S18) on the right side of the 3rd switch (S3) with being connected, the tenth
Side joint threshold voltage V under eight switches (S18)th1.It is connected on the left of 3rd switch (S3) with the left of the 4th switch (S4), and connects input
Signal.5th electric capacity (Csc11) on the right side of connect the upside of the 6th switch (S6), and with preventing big device 1 (pre1) input to be connected,
Prevent big (pre1) output end of device 1 to close with the second sixteenmo on the left of (S26) to be connected, the second sixteenmo closes and connects first on the right side of (S26)
Latch (Latch1) input, the first Latch (Latch1) is resetted by the 20th switch (S20) control.
6th electric capacity (Csc12) left side on the upside of the 19th switch (S19) on the right side of the 4th switch (S4) with being connected, the 19th opens
Close side joint threshold voltage V under (S19)th2.6th electric capacity (Csc12) on the right side of connect the upside of the 7th switch (S7), it is and big with prevention
Device 2 (pre2) input is connected, and prevents big (pre2) output end of device 2 with being connected on the left of the 27th switch (S27), and the 27th
The 2nd Latch (Latch2) input is connect on the right side of switch (S27), the 2nd Latch (Latch2) is resetted by the 21st switch
(S21) control.
Second multiplication digital-to-analogue unit (MDAC2) includes the 3rd electric capacity (Cf1), the 4th electric capacity (Cf2), the 8th switch (S8), the
13 switches (S13), the 14th switch (S14), the 15th switch (S15), the 22nd switch (S22), the second coding circuit
(Decoder2), the first amplifier (OPA).
Wherein, the 3rd electric capacity (Cf1), the 4th electric capacity (Cf2), the first amplifier (OPA) and the first multiplication digital-to-analogue unit
(MDAC1) share, and connected mode is identical.Third level input, the right side of the 15th switch (S15) are connect on the right side of 8th switch (S8)
Side joint datum Vdac2, the output of control the second coding circuit of termination (Decoder2) of the 15th switch (S15), second compiles
Code circuit (Decoder2) connects on the left of the 13rd switch (S13) and the 14th switch (S14) control, the 13rd switch (S13)
2nd Latch (Latch2) output and with thirty-twomo close (S32) on the left of be connected, the 14th switch (S14) left side and
First Latch (Latch1) outputs are connected, and with being connected on the left of the 33rd (S33).
Between the second level ADC (sub_ADC2) include the 9th switch (S9), the tenth switch (S10), the 11st switch (S11),
12nd switch (S12), the second eighteenmo close (S28), the 29th switch (S29), the 30th switch (S30), the 31st
Switch (S31), the 7th electric capacity (Csc21), the 8th electric capacity (Csc22), the first Latch (Latch1), the 2nd Latch (Latch2).
Wherein, the first Latch (Latch1), the 2nd Latch (Latch2) ADC (sub_ADC1) between the first order are shared.
Second eighteenmo closes to switch with the 29th on the right side of (S28) to be connected on the right side of (S29), and connects the first amplifier (OPA) output end, the
Two eighteenmos are closed switchs (S10) upside and the 7th electric capacity (C with the tenth on the left of (S28)sc21) right side be connected, the 7th electric capacity (Csc21)
Left side is connected with the upside of the 30th switch (S30) and on the right side of the 12nd switch (S12), and first is connect on the left of the 12nd switch (S12)
Latch (Latch1) input.With the 9th switch (S9) upside and the 8th electric capacity (C on the left of 29th switch (S29)sc22)
Right side is connected, the 8th electric capacity (Csc22) left side is switched with the 31st on the upside of (S31) and the 11st switch (S11) right side is connected,
The 2nd Latch (Latch2) input is connect on the left of 11st switch (S11).
Fig. 2 is the circuit diagram for the three phase clock used in the embodiment of the present invention, wherein, Φ 1, Φa1, Φ 2 be three phase clock,
ΦaOnly there is high level before the arrival of the rising edges of Φ 2, it is therefore an objective to for amplifier, the reset of electric capacity, Φa1In Φ 1, the rising edges of Φ 2
All there is high level before arriving, it is therefore an objective to which, for Latch1, Latch2 reset, Φ 1E trailing edge is than the trailing edges of Φ 1 slightly
In advance, Φ 2E trailing edge slightly shifts to an earlier date than the trailing edges of Φ 2, it is therefore an objective to realize lower step sampling, timely to reduce electric charge injection
The influence of clock feedthrough effect.For Φ 1 inversion clock phase.
In circuit shown in Fig. 1, S1~S4 is switched, S8~S14 is controlled by clock phase Φ 1, S5~S7 is switched, by clock phase Φ
1E is controlled, and switch S16~S19 is by clock phase ΦaControl, S20, S21 are by clock phase Φa1Control, S22 is anti-by clock phase Φ's 1
Phase clockControl, switch S24~S29, S32, S33 are controlled by clock phase Φ 2, and switch S30, S31 is controlled by clock phase Φ 2E
System.
The course of work of the above-mentioned shared pipeline stages circuit structure of multimode：
(1) when sampling phase Φ 1, switch S1~S15 closures, the sampling capacitance C of the first multiplication digital-to-analogue unit (MDAC1)s1、
Csc2ADC (sub_ADC1) the sampling capacitance C between the first ordersc11、Csc11Simultaneously to input signal VinSampled, under Φ 1E
Drop is along when arriving, and switch S5~S7 is turned off in advance, completes lower step sampling, can reduce the electric charge injection introduced by switch and clock
Feedthrough effect.Meanwhile, ADC (sub_ADC2) between Latch1, Latch2 and the logic coding circuit Decoder2 compositions second level is obtained
To the digital code and the digital controlled signal of the second multiplication digital-to-analogue unit (MDAC2) of second level pipeline stages, Cf1With datum
Vdac2It is connected, Cf2As feedback capacity, constitute the second multiplication digital-to-analogue unit (MDAC2) with operational amplifier and complete second level flowing water
The amplification of line level redundant signals.Datum Vdac2ADC (sub_ADC2) the numeral output control between clock phase Φ 1 and the second level
System, it is different according to this level production line level input signal amplitude, it is respectively-Vref、Vcm、Vref。
(2) when Φ a are high level, switch S16~S22 is closed, ADC (sub_ADC1) sampling capacitance between the first order
Csc11、Csc12To comparative threshold voltage VThi, (i=1,2)Sampled, and completed through pre-amplification stage to difference voltage (Vin-
VThi, (i=1,2)) amplification, now, amplifier and electric capacity Cf1、Cf2Carry out reset operation, it is therefore an objective to eliminate the influence of memory effect,
Latch1, Latch2 are resetted in Φ a1 clock phases.
(3) when the clocks of Φ 2 are mutually high, switch S22~S33 is closed, Latch1, Latch2 and logic coding circuit
ADC (sub_ADC1) between the Decoder1 composition first order, exports the digital code and the first multiplication digital-to-analogue list of first order pipeline stages
The digital controlled signal of first (MDAC1), electric capacity Cs1It is connected with common mode electrical level, Cs2With datum Vdac1It is connected, Cf1、Cf2To be anti-
Feed holds, and constituting the first multiplication digital-to-analogue unit (MDAC1) with operational amplifier completes the amplification of first order pipeline stages redundant signals,
Meanwhile, Cf1、Cf2As the sampling capacitance of the second multiplication digital-to-analogue unit (MDAC2), ADC (sub_ADC2) samples between the second level
Electric capacity together, realizes second level pipeline stages sampling operation.Wherein, datum Vdac1By clock phase Φ's 2 and sub_ADC1
Numeral output is controlled, according to input signal VinAmplitude is different, is respectively-Vref、Vcm、Vref。
The foregoing is only the present invention better embodiment, protection scope of the present invention not using above-mentioned embodiment as
Limit, as long as equivalent modification that those of ordinary skill in the art are made according to disclosed content or change, should all include power
In protection domain described in sharp claim.
Claims (3)
1. the shared pipeline stages circuit structure of multimode for low-power consumption assembly line ADC, it is characterised in that multiply including first
Method digital-to-analogue unit（MDAC1）, ADC between the first order（sub_ADC1）, the second multiplication digital-to-analogue unit（MDAC2）The ADC between the second level
（sub_ADC2）；The first multiplication digital-to-analogue unit（MDAC1）With the second multiplication digital-to-analogue unit（MDAC2）The electricity of time-sharing multiplex the 3rd
Hold（Cf1）, the 4th electric capacity（Cf2）With the first amplifier（OPA）；ADC between the first order（sub_ADC1）The ADC between the second level
（sub_ADC2）The Latch of time-sharing multiplex the first（Latch1）With the 2nd Latch（Latch2）；
When clock phase Φ 1 is high level, the 3rd electric capacity（Cf1）To datum Vdac2Sampled, the 4th electric capacity（Cf2）
It is used as feedback capacity and first amplifier（OPA）It is used as the second multiplication digital-to-analogue unit（MDAC2）Modular unit, realize second
Multiplication digital-to-analogue unit（MDAC2）Subtract each other, remainder, redundancy amplification function；When clock phase Φ 2 is high level, the described 3rd
Electric capacity（Cf1）With the 4th electric capacity（Cf2）It is used as the first multiplication digital-to-analogue unit（MDAC1）Feedback capacity and first amplifier
（OPA）The first multiplication digital-to-analogue unit is realized together（MDAC1）Subtract each other, remainder, redundancy enlarging function, meanwhile, the 3rd electric capacity
（Cf1）With the 4th electric capacity（Cf2）It is used as the second multiplication digital-to-analogue unit（MDAC2）Sampling capacitance, complete the second multiplication digital-to-analogue unit
（MDAC2）Sampling operation；When clock phase Φ a are high level, the 3rd electric capacity（Cf1）With the 4th electric capacity（Cf2）, first
Amplifier（OPA）Reset operation is carried out, to eliminate memory effect；
First Latch（Latch1）With the 2nd Latch（Latch2）When clock phase Φ 1 is high level, the first order is used as
Between ADC（sub_ADC1）Comparator, realizes the comparison of input signal and reference threshold；When clock phase Φ 2 is high level, as
ADC between the second level（sub_ADC2）Comparator, realize the comparison of input signal and reference threshold；It is high electricity in clock phase Φ a1
Usually, reset operation is carried out；
There is high level before the arrival of the rising edges of clock phase Φ 2 in the clock phase Φ a, the clock phase Φ a1 clock phase Φ 1,
All there is high level before arriving in the rising edges of clock phase Φ 2.
2. the shared pipeline stages circuit structure of the multimode according to claim 1 for low-power consumption assembly line ADC, its
It is characterised by, the first multiplication digital-to-analogue unit（MDAC1）Including the first electric capacity（Cs1）, the second electric capacity（Cs2）, the 3rd electric capacity
（Cf1）, the 4th electric capacity（Cf2）, first switch（S1）, second switch（S2）, the 5th switch（S5）, sixteenmo close（S16）,
17 switches（S17）, the 22nd switch（S22）, the 23rd switch（S23）, the 24th switch（S24）, the 25th
Switch（S25）, the first coding circuit（Decoder1）, thirty-twomo pass（S32）, the 33rd switch（S33）With the first fortune
Put（OPA）；
The second multiplication digital-to-analogue unit（MDAC2）Including the 3rd electric capacity（Cf1）, the 4th electric capacity（Cf2）, the 8th switch（S8）,
13 switches（S13）, the 14th switch（S14）, the 15th switch（S15）, the 22nd switch（S22）, the second coding circuit
（Decoder2）, the first amplifier（OPA）；
Wherein, the first electric capacity（Cs1）Right pole plate and the second electric capacity（Cs2）Right pole plate is connected, and is switched with the 5th（S5）Upper end and
25 switches（S25）Left end point is connected, and left pole plate connects first switch（S1）Right endpoint and the 24th switch（S24）Right-hand member
Point；First switch（S1）Left end point and input signal VinIt is connected and and second switch（S2）It is connected；24th switch（S24）It is left
Side is connected with ground level；Second electric capacity（Cs2）Left side and second switch（S2）Right side, the 23rd switch（S23）Right side is connected,
23rd switch（S23）Left side meets datum Vdac1；3rd electric capacity（Cf1）With the 4th electric capacity（Cf2）Left side and sixteenmo
Close（S16）Upside and the 25th switch（S25）Right side be connected, and with the first amplifier（OPA）Negative input end is connected；Sixteenmo
Close（S16）Downside be connected with ground level and with the first amplifier（OPA）Positive input terminal is connected；3rd electric capacity（Cf1）Right side and the 20th
Two switches（S22）Left side and the 15th switch（S15）Left side is connected, the 4th electric capacity（Cf2）Right side and the 22nd switch（S22）
Right side and the 17th switch（S17）Upside and the 8th switch（S8）Left side be connected, while with the first amplifier（OPA）Output end phase
Even；First coding circuit（Decoder1）Output end control the 23rd is switched（S23）State；First coding circuit
（Decoder1）Working condition is by the 33rd switch（S33）, thirty-twomo close（S32）Control；
8th switch（S8）Right side connect the third level input, the 15th switch（S15）Right side meet datum Vdac2, the 15th
Switch（S15）Control terminate the second coding circuit（Decoder2）Output, the second coding circuit（Decoder2）By the tenth
Three switches（S13）With the 14th switch（S14）Control；
First switch（S1）, second switch（S2）, the 8th switch（S8）, the 13rd switch（S13）With the 14th switch（S14）By
Clock phase Φ 1 is controlled, the 22nd switch（S22）Clock phase Φ 1 inversion clock control, the 24th switch（S24）, second
15 switches（S25）, the 33rd switch（S33）Closed with thirty-twomo（S32）Controlled by clock phase Φ 2, sixteenmo is closed
（S16）With the 17th switch（S17）By clock phase ΦaControl, the 5th switch（S5）Controlled by clock phase Φ 1E；Wherein, clock
Phase Φ 1E trailing edge shifts to an earlier date than the trailing edges of clock phase Φ 1.
3. the shared pipeline stages circuit of a kind of multimode suitable for low-power consumption assembly line ADC according to claim 1
Structure, it is characterised in that ADC between the first order（sub_ADC1）Including the 3rd switch（S3）, the 4th switch（S4）, the 6th open
Close（S6）, the 7th switch（S7）, eighteenmo close（S18）, the 19th switch（S19）, the 20th switch（S20）, the 21st
Switch（S21）, the second sixteenmo close（S26）, the 27th switch（S27）, the 5th electric capacity（Csc11）, the 6th electric capacity（Csc12）, the
One Latch（Latch1）With the 2nd Latch（Latch2）；
ADC between the second level（sub_ADC2）Including the 9th switch（S9）, the tenth switch（S10）, the 11st switch（S11）、
12nd switch（S12）, the second eighteenmo close（S28）, the 29th switch（S29）, the 30th switch（S30）, the 31st
Switch（S31）, the 7th electric capacity（Csc21）, the 8th electric capacity（Csc22）, the first Latch（Latch1）With the 2nd Latch（Latch2）；
5th electric capacity（Csc11）Left side and the 3rd switch（S3）Right side and eighteenmo are closed（S18）Upside is connected, and eighteenmo is closed
（S18）Lower side joint threshold voltage Vth1；3rd switch（S3）Left side and the 4th switch（S4）Left side is connected, and connects input signal；The
Five electric capacity（Csc11）Right side connect the 6th switch（S6）Upside, and with preventing big device 1（pre1）Input is connected, and prevents big device
1（pre1）Output end is closed with the second sixteenmo（S26）Left side is connected, and the second sixteenmo is closed（S26）Right side meets the first Latch
（Latch1）Input, the first Latch（Latch1）Reset by the 20th switch（S20）Control；6th electric capacity（Csc12）Left side
With the 4th switch（S4）Right side and the 19th switch（S19）Upside is connected, the 19th switch（S19）Lower side joint threshold voltage Vth2；
6th electric capacity（Csc12）Right side connect the 7th switch（S7）Upside, and with preventing big device 2（pre2）Input is connected, and prevention is big
Device 2（pre2）Output end and the 27th switch（S27）Left side is connected, the 27th switch（S27）Right side meets the 2nd Latch
（Latch2）Input, the 2nd Latch（Latch2）Reset by the 21st switch（S21）Control；
Second eighteenmo is closed（S28）Right side and the 29th switch（S29）Right side is connected, and connects the first amplifier（OPA）Output
End, the second eighteenmo is closed（S28）Left side and the tenth switch（S10）Upside and the 7th electric capacity（Csc21）Right side is connected, the 7th electric capacity
（Csc21）Left side and the 30th switch（S30）Upside and the 12nd switch（S12）Right side is connected, the 12nd switch（S12）Left side
Meet the first Latch（Latch1）Input；29th switch（S29）Left side and the 9th switch（S9）Upside and the 8th electric capacity
（Csc22）Right side is connected, the 8th electric capacity（Csc22）Left side and the 31st switch（S31）Upside and the 11st switch（S11）Right side
It is connected, the 11st switch（S11）Left side meets the 2nd Latch（Latch2）Input；
3rd switch（S3）, the 4th switch（S4）, the 9th switch（S9）, the tenth switch（S10）, the 11st switch（S11）With
12 switches（S12）Controlled by clock phase Φ 1, the second sixteenmo is closed（S26）, the 27th switch（S27）, the second eighteenmo close
（S28）With the 29th switch（S29）Controlled by clock phase Φ 2, eighteenmo is closed（S18）With the 19th switch（S19）By when
Clock phase Φ a are controlled, the 6th switch（S6）With the 7th switch（S7）Controlled by clock phase Φ 1E, the 30th switch（S30）With the 3rd
11 switches（S31）Controlled by clock phase Φ 2E, the 20th switch（S20）With the 21st switch（S21）By clock phase Φ a1
Control；Wherein, clock phase Φ 1E trailing edge shifts to an earlier date than the trailing edges of clock phase Φ 1, and clock phase Φ 2E trailing edge is than clock phase
The trailing edges of Φ 2 shift to an earlier date.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101895295A (en) * | 2010-07-09 | 2010-11-24 | 复旦大学 | Operational amplifier-shared low-power consumption production line analog-digital converter |
| US7924204B2 (en) * | 2008-10-07 | 2011-04-12 | Himax Media Solutions, Inc. | Stage-resolution scalable opamp-sharing technique for pipelined/cyclic ADC |
| JP2014022963A (en) * | 2012-07-19 | 2014-02-03 | Renesas Electronics Corp | Semiconductor integrated circuit having a/d converter, and a/d conversion method |
| CN204145422U (en) * | 2014-09-23 | 2015-02-04 | 无锡华大国奇科技有限公司 | Based on the operational transconductance amplifier of self adaptation tail current |
| CN104604139A (en) * | 2012-08-22 | 2015-05-06 | 赫梯特微波公司 | Methods and apparatus for calibrating stages in pipeline analog-to-digital converters |
| CN104796146A (en) * | 2015-04-27 | 2015-07-22 | 西安电子科技大学 | Memory effect eliminable low-power analog-digital converter |
| CN104811206A (en) * | 2014-01-29 | 2015-07-29 | 美国亚德诺半导体公司 | Multi-input analog-to-digital converter |
| CN104993831A (en) * | 2015-07-31 | 2015-10-21 | 中国科学院电子学研究所 | Time-interleaving Pipeline-SAR type ADC circuit |
| US20150381192A1 (en) * | 2014-06-27 | 2015-12-31 | Renesas Electronics Corporation | Semiconductor device |
-
2017
- 2017-05-18 CN CN201710351187.3A patent/CN107231154B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7924204B2 (en) * | 2008-10-07 | 2011-04-12 | Himax Media Solutions, Inc. | Stage-resolution scalable opamp-sharing technique for pipelined/cyclic ADC |
| CN101895295A (en) * | 2010-07-09 | 2010-11-24 | 复旦大学 | Operational amplifier-shared low-power consumption production line analog-digital converter |
| JP2014022963A (en) * | 2012-07-19 | 2014-02-03 | Renesas Electronics Corp | Semiconductor integrated circuit having a/d converter, and a/d conversion method |
| CN104604139A (en) * | 2012-08-22 | 2015-05-06 | 赫梯特微波公司 | Methods and apparatus for calibrating stages in pipeline analog-to-digital converters |
| CN104811206A (en) * | 2014-01-29 | 2015-07-29 | 美国亚德诺半导体公司 | Multi-input analog-to-digital converter |
| US20150381192A1 (en) * | 2014-06-27 | 2015-12-31 | Renesas Electronics Corporation | Semiconductor device |
| CN204145422U (en) * | 2014-09-23 | 2015-02-04 | 无锡华大国奇科技有限公司 | Based on the operational transconductance amplifier of self adaptation tail current |
| CN104796146A (en) * | 2015-04-27 | 2015-07-22 | 西安电子科技大学 | Memory effect eliminable low-power analog-digital converter |
| CN104993831A (en) * | 2015-07-31 | 2015-10-21 | 中国科学院电子学研究所 | Time-interleaving Pipeline-SAR type ADC circuit |
Non-Patent Citations (3)
| Title |
|---|
| BYUNG-MOO MIN,ET AL: "A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC", 《IEEE JOURNAL OF SOLID-STATE CIRCUITS》 * |
| J. A. DÍAZ-MADRID, ET AL: "Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing", 《EDAA 2009》 * |
| 万富强等: "一种改进运放共享结构的11位流水线ADC设计", 《微电子学与计算机》 * |
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