CN107222888A - A kind of RRU antiblockings implementation method and device, RRU - Google Patents
A kind of RRU antiblockings implementation method and device, RRU Download PDFInfo
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- CN107222888A CN107222888A CN201610165780.4A CN201610165780A CN107222888A CN 107222888 A CN107222888 A CN 107222888A CN 201610165780 A CN201610165780 A CN 201610165780A CN 107222888 A CN107222888 A CN 107222888A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W28/00—Network traffic management; Network resource management
- H04W28/02—Traffic management, e.g. flow control or congestion control
- H04W28/0289—Congestion control
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
- H04W52/04—TPC
- H04W52/52—TPC using AGC [Automatic Gain Control] circuits or amplifiers
Abstract
The invention discloses a kind of RRU antiblockings implementation method and device, RRU, the block resistance to improve RRU device alleviates obstruction interference, it is ensured that RRU receives link normal work.This method includes：When receiving the interrupt signal of FPGA transmissions, determine that signal jam occurs for RRU receives link；Gain to the receives link of the RRU is adjusted control.
Description
Technical field
The present invention relates to communication technical field, more particularly to a kind of Remote Radio Unit (Remote Radio
Unit, RRU) antiblocking implementation method and device, RRU.
Background technology
In current time-division Long Term Evolution (time division long term evolution, TD-LTE) system,
Particularly in the F-band of system, the serious situation of the receives link generally existing signal jam of RRU device,
So that uplink can not normal work, the normal perception of influence user.
Therefore, how RRU block resistance is optimized, with alleviate obstruction interference be it is current urgently
The problem of solution.
The content of the invention
The embodiments of the invention provide a kind of RRU antiblockings implementation method and device, RRU, to improve
The block resistance of RRU device, alleviates obstruction interference, it is ensured that RRU receives link normal work.
A kind of RRU antiblockings implementation method provided in an embodiment of the present invention, including：
Sent out when receiving field programmable gate array (Field Programmable Gate Array, FPGA)
During the interrupt signal sent, determine that signal jam occurs for RRU receives link；
Gain to the receives link of the RRU is adjusted control.
This method provided in an embodiment of the present invention, can be true when receiving the interrupt signal of FPGA transmissions
Signal jam occurs for the receives link for determining RRU, and then is adjusted control to the gain of RRU receives link
System, so as to alleviate obstruction interference, improves the block resistance of RRU device, it is ensured that RRU reception
Link can normal work, and then lifted user perceive.
It is preferred that the gain to the receives link of the RRU is adjusted control, specifically include：
Read from the FPGA by the FPGA in ascending time slot, to the sampled data of predetermined number
The maximum power value that power is determined after being counted, the sampled data is the FPGA to analog-digital converter
(Analog to Digital Converter, ADC) send signal sampled after data；
According to the maximum power value, it is determined that needing the gain to the receives link of the RRU to be adjusted
Yield value, and indicate gain of the gain regulation module according to the yield value to signal in the receives link
It is adjusted.
So as to according to the maximum power value read from FPGA, it is determined that needing the reception to the RRU
The yield value that the gain of link is adjusted, and indicate the gain regulation module in the receives link according to this
Gain of the yield value to signal is adjusted, and has been reached the purpose for alleviating obstruction interference, has been improved RRU and set
Standby block resistance, it is ensured that RRU receives link being capable of normal work.
It is preferred that according to the maximum power value, it is determined that needing the gain to the receives link of the RRU
The yield value being adjusted, and indicate the gain regulation module in the receives link according to the yield value to letter
Number gain be adjusted, specifically include：
According to the maximum power value and default scaled power value, it is determined that needing the signal to analog link
The first yield value that gain is adjusted, and need to be adjusted the signal gain of digital link second
Yield value；
By sending gain regulation module of first yield value to the analog link, the simulation is indicated
The gain of signal is lowered the first yield value by the gain regulation module of link, and is increased by sending described second
Benefit is worth the gain regulation module to the digital link, indicates the gain regulation module of the digital link and will believe
Number gain raise the second yield value.
So as to, by determining first yield value, and instruction simulation link gain regulation module by signal
Gain lower the first yield value so that in receives link ADC input power reduction so that ADC
Do not occur saturation, reached the purpose for alleviating obstruction interference.Meanwhile, second yield value is determined, and refer to
Show that the gain of signal is raised the second yield value by the gain regulation module of digital link so that RRU entirely connects
The gain for receiving link keeps constant.That is, by the gain adjusting method, ensureing that RRU is whole
On the premise of the gain of receives link keeps constant so that ADC input power reduction in receives link,
Improve the block resistance of RRU device, it is ensured that RRU receives link being capable of normal work.
It is preferred that in descending time slot, sending Gain tuning mould of first yield value to the analog link
Block, and send gain regulation module of second yield value to the digital link.
So as to, the first yield value and the second yield value are sent in descending time slot, and then by the increasing of analog link
Beneficial adjusting module according to the first yield value, and digital link gain regulation module according to the second yield value,
The gain to link is adjusted respectively, and the gain of link can be avoided to produce mutation.
It is preferred that according to the maximum power value and default scaled power value, it is determined that needing to analog chain
The first yield value that the signal gain on road is adjusted, is specifically included：
According to the maximum power value and default scaled power value, determine to be directed to signal using equation below
Obstruction needs the yield value PGC_bc being adjusted to the signal gain of analog link：
PGC_bc=PGC_bc'+ (P-P0)
Wherein, PGC_bc' represents the yield value that the last signal gain to the analog link is adjusted, P
Represent the maximum power value, P0Represent the default scaled power value；
By the PGC_bc, with it is default the need for the basic value that is adjusted to the signal gain of analog link
PGC0It is added, obtains first yield value.
It is preferred that according to the maximum power value and default scaled power value, it is necessary to digital link
The second yield value that signal gain is adjusted, is specifically included：
By the PGC_bc, with it is default the need for logarithm word link the basic value that is adjusted of signal gain
AGC0It is added, obtains second yield value.
It is preferred that this method also includes：
When be not received by FPGA transmission interrupt signal when, periodically read from the FPGA by
The FPGA is in ascending time slot, the maximum determined after being counted to the power of the sampled data of predetermined number
Performance number, the sampled data is after the FPGA samples to the analog-digital converter ADC signals sent
Data；
When the maximum power value read from the FPGA is less than default scaled power value, and the maximum
When the absolute value of the difference of performance number and default scaled power value is more than default threshold value, to the RRU
The gain of receives link be adjusted control.
So as to reach the purpose that the gain to RRU receives links is reduced, it is ensured that in receives link
ADC input powers are maintained in default scope, lift upstream sensitivity.
It is preferred that the maximum power value read from the FPGA is less than default scaled power value, and
When the absolute value of the difference of the maximum power value and default scaled power value is more than default thresholding, to described
The gain of RRU receives link is adjusted control, specifically includes：
According to the maximum power value and default scaled power value, it is determined that needing the signal increasing to analog link
The 3rd yield value that benefit is adjusted, and need the 4th increasing that is adjusted to the signal gain of digital link
Benefit value；
By sending gain regulation module of the 3rd yield value to the analog link, the simulation is indicated
The gain of signal is raised the 3rd yield value by the gain regulation module of link, and by sending the 4th increasing
Benefit is worth the gain regulation module to the digital link, indicates the gain regulation module of the digital link and will believe
Number gain lower the 4th yield value.
It is preferred that according to the maximum power value and default scaled power value, determining to need using equation below
The 3rd yield value to be adjusted to the signal gain of analog link：
PGC_bc=PGC_bc'+ (P-P0)+3
Wherein, PGC_bc' represents the yield value that the last signal gain to the analog link is adjusted,
P represents the maximum power value, P0Represent the default scaled power value.
It is preferred that the 4th yield value is equal to the 3rd yield value.
The embodiments of the invention provide another RRU antiblockings implementation method, this method includes：
FPGA is sampled to the ADC signals sent, and sampled data is detected, determines RRU
Receives link whether occur signal jam；
When it is determined that the receives link of the RRU produces signal jam, interrupt signal is exported to processor,
Control is adjusted to the gain of the receives link of the RRU by processor.
This method provided in an embodiment of the present invention, the ADC signals sent are sampled by FPGA and
Detection, determines whether RRU receives link occurs signal jam, and it is determined that the reception chain of the RRU
When road produces signal jam, interrupt signal is exported to processor, by reception chain of the processor to the RRU
The gain on road is adjusted control, so as to alleviate obstruction interference, improves the resistance to blocking of RRU device
Can, it is ensured that RRU receives link can normal work, and then lifted user perceive.
It is preferred that the FPGA samples to the ADC signals sent, and sampled data is examined
Survey, determine whether RRU receives link produces signal jam, specifically include：
The FPGA is in ascending time slot, after being counted to the power of the sampled data of predetermined number
Determine maximum power value；
The maximum power value is compared by the FPGA with default scaled power value, when it is determined that described
When maximum power value is more than the default scaled power value, determine that the receives link of the RRU is believed
Number obstruction.
Device is realized the embodiments of the invention provide a kind of RRU antiblockings, the device includes：
Determining unit, for when receiving the interrupt signal of FPGA transmissions, determining RRU reception chain
Signal jam occurs for road；
Control unit, the gain for the receives link to the RRU is adjusted control.
By the device, obstruction interference can be alleviated, the block resistance of RRU device is improved, it is ensured that RRU
Receives link can normal work, and then lifted user perceive.
It is preferred that described control unit specifically for：
Read from the FPGA by the FPGA in ascending time slot, to the sampled data of predetermined number
The maximum power value that power is determined after being counted, the sampled data is the FPGA to analog-digital converter
ADC send signal sampled after data；
According to the maximum power value, it is determined that needing the gain to the receives link of the RRU to be adjusted
Yield value, and indicate gain of the gain regulation module according to the yield value to signal in the receives link
It is adjusted.
It is preferred that described control unit is according to the maximum power value, it is determined that needing to meet the RRU
Receive the yield value that is adjusted of gain of link, and indicate the gain regulation module in the receives link according to
When gain of the yield value to signal is adjusted, specifically for：
According to the maximum power value and default scaled power value, it is determined that needing the signal to analog link
The first yield value that gain is adjusted, and need to be adjusted the signal gain of digital link second
Yield value；
By sending gain regulation module of first yield value to the analog link, the simulation is indicated
The gain of signal is lowered the first yield value by the gain regulation module of link, and is increased by sending described second
Benefit is worth the gain regulation module to the digital link, indicates the gain regulation module of the digital link and will believe
Number gain raise the second yield value.
It is preferred that described control unit is in descending time slot, first yield value is sent to the analog link
Gain regulation module, and send the gain regulation module of second yield value to the digital link.
It is preferred that described control unit is according to the maximum power value and default scaled power value, it is determined that
When needing the first yield value being adjusted to the signal gain of analog link, specifically for：
According to the maximum power value and default scaled power value, determine to be directed to signal using equation below
Obstruction needs the yield value PGC_bc being adjusted to the signal gain of analog link：
PGC_bc=PGC_bc'+ (P-P0)
Wherein, PGC_bc' represents the yield value that the last signal gain to the analog link is adjusted, P
Represent the maximum power value, P0Represent the default scaled power value；
By the PGC_bc, with it is default the need for the basic value that is adjusted to the signal gain of analog link
PGC0It is added, obtains first yield value.
It is preferred that described control unit according to the maximum power value and default scaled power value, it is necessary to
The second yield value that signal gain to digital link is adjusted, is specifically included：
By the PGC_bc, with it is default the need for logarithm word link the basic value that is adjusted of signal gain
AGC0It is added, obtains second yield value.
It is preferred that the determining unit is additionally operable to：
When be not received by FPGA transmission interrupt signal when, periodically read from the FPGA by
The FPGA is in ascending time slot, the maximum determined after being counted to the power of the sampled data of predetermined number
Performance number, the sampled data is the data after the FPGA samples to the ADC signals sent；
When the determining unit determines that the maximum power value read from the FPGA is less than default calibration work(
Rate value, and the absolute value of the difference of the maximum power value and default scaled power value is more than default threshold value
When, described control unit is additionally operable to：Gain to the receives link of the RRU is adjusted control.
It is preferred that being preset when the determining unit determines that the maximum power value read from the FPGA is less than
Scaled power value, and the difference of the maximum power value and default scaled power value absolute value be more than it is default
Thresholding when, gain of the described control unit in the following way to the receives link of the RRU is adjusted
Whole control：
According to the maximum power value and default scaled power value, it is determined that needing the signal increasing to analog link
The 3rd yield value that benefit is adjusted, and need the 4th increasing that is adjusted to the signal gain of digital link
Benefit value；
By sending gain regulation module of the 3rd yield value to the analog link, the simulation is indicated
The gain of signal is raised the 3rd yield value by the gain regulation module of link, and by sending the 4th increasing
Benefit is worth the gain regulation module to the digital link, indicates the gain regulation module of the digital link and will believe
Number gain lower the 4th yield value.
It is preferred that described control unit is according to the maximum power value and default scaled power value, using such as
Lower formula determines the 3rd yield value for needing to be adjusted the signal gain of analog link：
PGC_bc=PGC_bc'+ (P-P0)+3
Wherein, PGC_bc' represents the yield value that the last signal gain to the analog link is adjusted,
P represents the maximum power value, P0Represent the default scaled power value.
It is preferred that the 4th yield value is equal to the 3rd yield value.
Device is realized the embodiments of the invention provide another RRU antiblockings, the device includes：
Determining unit, for being sampled to the signal that ADC is sent, and is detected to sampled data,
Determine whether RRU receives link occurs signal jam；
Output unit, for when it is determined that the receives link of the RRU produces signal jam, output to be interrupted
Signal is adjusted control by processor to processor to the gain of the receives link of the RRU.
By the device, sample detecting is carried out to the signal that ADC is sent, determining RRU receives link is
No generation signal jam, and when it is determined that the receives link of the RRU produces signal jam, output is interrupted
Signal is adjusted control by processor to processor to the gain of the receives link of the RRU, can be with
Alleviate obstruction interference, improve the block resistance of RRU device, it is ensured that RRU receives link can be normal
Work, and then lift user's perception.
It is preferred that determining unit in the device specifically for：
In ascending time slot, maximum work is determined after being counted to the power of the sampled data of predetermined number
Rate value；
The maximum power value is compared with default scaled power value, when it is determined that the maximum power value
During more than the default scaled power value, determine that signal jam occurs for the receives link of the RRU.
Device is realized in a kind of RRU provided in an embodiment of the present invention, including above two RRU antiblockings.
Brief description of the drawings
Fig. 1 is that block diagram is realized in a kind of RRU receives links provided in an embodiment of the present invention and its antiblocking；
Fig. 2 is a kind of schematic flow sheet of RRU antiblockings implementation method provided in an embodiment of the present invention；
Fig. 3 is the schematic flow sheet of another RRU antiblockings implementation method provided in an embodiment of the present invention；
Fig. 4 is the structural representation that device is realized in a kind of RRU antiblockings provided in an embodiment of the present invention；
Fig. 5 is the structural representation that device is realized in another RRU antiblockings provided in an embodiment of the present invention.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, below in conjunction with accompanying drawing and reality
Example is applied, the present invention will be described in further detail.It should be appreciated that specific embodiment described herein is only
Only to explain the present invention, it is not intended to limit the present invention.
Fig. 1 is that block diagram is realized in a kind of RRU receives links provided in an embodiment of the present invention and its antiblocking.
Frequency mixer (Mixer), wave filter (LC), digital variable gain amplifier (Digital in Fig. 1
Variable Gain Amplifier, DVGA), it can be understood as it is analog link；In ADC and FPGA
Internal each functional module, it can be understood as be digital link.Wherein, the functional module inside FPGA includes
But it is not limited to：Digital Down Convert (Digital Down Converter, DDC) module, compensation automatic gain
Control (Automatic Generation Control, AGC) module, output AGC modules, ADC signal
Power detection module, power threshold judge module etc..Processor is connected with DVGA and FPGA respectively
Connect.
In this embodiment, for LTE system, compensation AGC modules can be arranged on after FIR filtering,
Now the module gain adjustment range can arrive 15dB for -1, and acquiescence can be -1dB；For time division synchronous
CDMA (Time Division-Synchronization Code Division Multiple Access,
TD-SCDMA) system, compensation AGC modules can be arranged on to be carried out before 3 sampling extractions to signal,
Now the module gain adjustment range can be 4-20dB, and acquiescence can be 4dB.
Also, in this embodiment, the signal gain of output AGC modules output could be arranged to fix 6dB,
It is placed on after FIR filtering, cut position is realized after FIR filter.
Further, it is to be appreciated that each functional module in the RRU receives links shown in Fig. 1 is
Main functional modules in RRU, certainly also include for example low-noise amplifier (Low Noise Amplifier,
Other functional modules such as LNA).
RRU antiblocking implementation methods are as follows：
FPGA receives the signal of ADC outputs, the signal exported by ADC power detection modules to ADC
Sampled and detected, the maximum power value of statistic sampling data；Power threshold judge module judges the maximum
Whether performance number is more than default scaled power value, when it is determined that the maximum power value is more than default scaled power
During value, determine that signal jam occurs for RRU receives link, and export interrupt signal to processor.Processing
Device is received after the interrupt signal of FPGA transmissions, determines that signal jam occurs for RRU receives link；Place
Reason device reads the maximum power value from FPGA, according to the maximum power value and default scaled power
Value determines the first yield value for needing to be adjusted the signal gain of analog link, and needs to digital chain
The second yield value that the signal gain on road is adjusted；First yield value is sent to DVGA (this by processor
The DVGA of this in embodiment is the gain regulation module of analog link), indicate DVGA by under the gain of signal
The first yield value is adjusted, and the compensation AGC modules (benefit of this in the present embodiment is given by sending the second yield value
Repay the gain regulation module that AGC modules are digital link), indicate compensation AGC modules by the gain of signal
Raise the second yield value.Entered simultaneously by the gain of the analog link to RRU and the gain of digital link
Row adjustment, so that on the premise of the gain for ensureing the whole receives links of RRU keeps constant so that receive
Saturation does not occur for the input power reduction of the ADC in link, ADC, so as to reach alleviation obstruction interference
Purpose, improve RRU block resistances, it is ensured that RRU receives link normal work.
Therefore, referring to Fig. 2, a kind of RRU antiblockings implementation method provided in an embodiment of the present invention, including with
Lower step：
S101, when receive FPGA transmission interrupt signal when, determine that RRU receives link is believed
Number obstruction；
S102, the gain to the receives link of the RRU are adjusted control.
It is preferred that in step S102, the gain to the receives link of the RRU is adjusted control, tool
Body includes：
Read from the FPGA by the FPGA in ascending time slot, to the sampled data of predetermined number
The maximum power value that power is determined after being counted, the sampled data is the FPGA to analog-digital converter
ADC send signal sampled after data；
Here, FPGA is in ascending time slot, after being counted to the power of the sampled data of predetermined number really
Determine maximum power value, for example can be FPGA in ascending time slot, every 4096 sampled points carry out power
Statistics, determines the performance number of maximum from 4096 sampled points respectively corresponding power.
According to the maximum power value, it is determined that needing the gain to the receives link of the RRU to be adjusted
Yield value, and indicate gain of the gain regulation module according to the yield value to signal in the receives link
It is adjusted.
It is preferred that according to the maximum power value, it is determined that needing the gain to the receives link of the RRU
The yield value being adjusted, and indicate the gain regulation module in the receives link according to the yield value to letter
Number gain be adjusted, specifically include：
According to the maximum power value and default scaled power value, it is determined that needing the signal to analog link
The first yield value that gain is adjusted, and need to be adjusted the signal gain of digital link second
Yield value；
Wherein, the default scaled power value, can set different scaled powers according to RRU difference
Value, certainly, different RRU set identical scaled power to be worth also possible, the embodiment of the present invention pair
This is not construed as limiting.
By sending gain regulation module of first yield value to the analog link, the simulation is indicated
The gain of signal is lowered the first yield value by the gain regulation module of link, and is increased by sending described second
Benefit is worth the gain regulation module to the digital link, indicates the gain regulation module of the digital link and will believe
Number gain raise the second yield value.
Wherein, the gain regulation module of the analog link, for example, can be DVGA, or may be programmed
Gain control (Programd Gain Control, PGC) module etc..The gain of the digital link is adjusted
Mould preparation block, such as can be the compensation AGC modules in FPGA.
In specific implementation, for example, can be in the gain for sending first yield value to the analog link
While adjusting module, carry one and indicate message, gain of the instruction message to indicate the analog link
The gain of signal is lowered the first yield value by adjusting module, and is sending second yield value to the number
While the gain regulation module of word link, carry one and indicate message, the instruction message is to indicate the number
The gain of signal is raised the second yield value by the gain regulation module of word link.In another example, can be according to advance
The form of agreement, sends gain regulation module of first yield value to the analog link, so that described
The gain regulation module of analog link is received after first yield value, it is possible to according to first yield value
Form, it is determined that the gain of signal is lowered into the first yield value, and according to the form made an appointment, sends institute
Gain regulation module of second yield value to the digital link is stated, so that the Gain tuning of the digital link
Module is received after second yield value, it is possible to according to the form of second yield value, it is determined that by signal
The second yield value is raised in gain.
Furthermore, it is necessary to explanation, pre-sets the scope that the gain to analog link is adjusted, and
The scope that gain to digital link is adjusted.For example, the scope that the gain to analog link is adjusted
0-15dB can be set to；It is (right that the scope that gain to digital link is adjusted can be set to -1 to 15dB
Answer LTE system), or 4-20dB (correspondence TD-SCDMA system).When first finally determined increases
When benefit value is more than default maximum adjusting range, the first yield value is set to the corresponding gain of maximum adjusting range
Value, such as when the first yield value is more than 15dB, 15dB is set to by the first yield value；When finally determined
When two yield values are more than default maximum adjusting range, the second yield value is set to maximum adjusting range corresponding
When yield value, such as the second yield value are more than 15dB, the second yield value is set to 15dB (correspondence LTE
System).
It is preferred that in descending time slot, sending Gain tuning mould of first yield value to the analog link
Block, and send gain regulation module of second yield value to the digital link.
It is preferred that according to the maximum power value and default scaled power value, it is determined that needing to analog chain
The first yield value that the signal gain on road is adjusted, is specifically included：
According to the maximum power value and default scaled power value, determine to be directed to signal using equation below
Obstruction needs the yield value PGC_bc being adjusted to the signal gain of analog link：
PGC_bc=PGC_bc'+ (P-P0) (1)
Wherein, PGC_bc' represents the yield value that the last signal gain to the analog link is adjusted, its
Initial value can be set to 0；P represents the maximum power value；P0Represent the default scaled power value；
By the PGC_bc, with it is default the need for the basic value that is adjusted to the signal gain of analog link
PGC0It is added, obtains first yield value.
Wherein, it is above-mentioned it is default the need for the basic value PGC that is adjusted to the signal gain of analog link0,
It is the gain adjustment value of acquiescence, for example, can is that the signal of analog link is increased the need for being calculated by temperature compensation
The yield value that benefit is adjusted.
It is preferred that according to the maximum power value and default scaled power value, it is necessary to digital link
The second yield value that signal gain is adjusted, is specifically included：
By the PGC_bc, with it is default the need for logarithm word link the basic value that is adjusted of signal gain
AGC0It is added, obtains second yield value.
Wherein, basic value AGC0It is the gain adjustment value of acquiescence, for LTE system, AGC0For example may be used
- 1dB is thought, for TD-SCDMA system, AGC0For example can be 4dB.
If that is, the gain of analog link to be lowered to certain yield value, correspondingly, just by digital chain
Certain yield value is raised in the gain on road, to cause the RRU gain of whole receives link to keep constant.
It is preferred that this method also includes：
When be not received by FPGA transmission interrupt signal when, periodically read from the FPGA by
The FPGA is in ascending time slot, the maximum determined after being counted to the power of the sampled data of predetermined number
Performance number, the sampled data is after the FPGA samples to the analog-digital converter ADC signals sent
Data；
Here, the cycle of maximum power value is read from FPGA, can be set according to actual needs, example
Such as can be 100ms.
When the maximum power value read from the FPGA is less than default scaled power value, and the maximum
When the absolute value of the difference of performance number and default scaled power value is more than default threshold value, to the RRU
The gain of receives link be adjusted control.
Due to after the interrupt signal of FPGA transmissions is received, using the above method to RRU receives links
Gain adjusted, therefore, be subsequently not received by FPGA transmission interrupt signal when, the cycle
Property read the maximum power value counted by FPGA from FPGA, and be less than in the maximum power value default
Scaled power value, and the difference of the maximum power value and default scaled power value absolute value be more than it is default
Threshold value when, the gain to the receives link of the RRU is adjusted again, to reduce receives link
Yield value, it is ensured that upstream sensitivity.
Wherein, default threshold value, can sets itself according to actual needs, for example can be by the threshold value
It is set to 5dB.So as to be less than default scaled power value P in maximum power value P0Under conditions of：Work as P
With P0Difference absolute value be more than 5dB (such as P-P0=-8dB) when, the gain to receives link is adjusted
It is whole, as P and P0Difference absolute value be less than 5dB (such as P-P0=-3dB) when, not to receives link
Gain be adjusted.That is so that peak power P remains at P0With (P0- 5) between.
It is preferred that working as the maximum power value read from the FPGA is less than default scaled power value, and
And the absolute value of the difference of the maximum power value and default scaled power value be more than default thresholding when, using such as
Gain of the under type to the receives link of the RRU is adjusted control：
According to the maximum power value and default scaled power value, it is determined that needing the signal increasing to analog link
The 3rd yield value that benefit is adjusted, and need the 4th increasing that is adjusted to the signal gain of digital link
Benefit value；
By sending gain regulation module of the 3rd yield value to the analog link, the simulation is indicated
The gain of signal is raised the 3rd yield value by the gain regulation module of link, and by sending the 4th increasing
Benefit is worth the gain regulation module to the digital link, indicates the gain regulation module of the digital link and will believe
Number gain lower the 4th yield value.
It is preferred that according to the maximum power value and default scaled power value, it is determined that needing to analog link
Signal gain be adjusted three yield values when, equation below can be used：
PGC_bc=PGC_bc'+ (P-P0)+3 (2)
Wherein, PGC_bc' represents the yield value that the last signal gain to the analog link is adjusted,
P represents the maximum power value, P0Represent the default scaled power value.
Also, it is preferred that need the 4th yield value being adjusted to the signal gain of digital link to be equal to institute
State the 3rd yield value for needing to be adjusted the signal gain of analog link.
In specific implementation, for example, can be in the gain for sending the 3rd yield value to the analog link
While adjusting module, carry one and indicate message, gain of the instruction message to indicate the analog link
The gain of signal is raised the 3rd yield value by adjusting module, and is sending the 4th yield value to the number
While the gain regulation module of word link, carry one and indicate message, the instruction message is to indicate the number
The gain of signal is lowered the 4th yield value by the gain regulation module of word link.In another example, can be according to advance
The form of agreement, sends gain regulation module of the 3rd yield value to the analog link, so that described
The gain regulation module of analog link is received after the 3rd yield value, it is possible to according to the 3rd yield value
Form, it is determined that the gain of signal is raised into the 3rd yield value, and according to the form made an appointment, sends institute
Gain regulation module of the 4th yield value to the digital link is stated, so that the Gain tuning of the digital link
Module is received after the 4th yield value, it is possible to according to the form of the 4th yield value, it is determined that by signal
The 4th yield value is lowered in gain.
Referring to Fig. 3, the embodiments of the invention provide another RRU antiblockings implementation method, this method includes
Following steps：
S201, FPGA are sampled to the ADC signals sent, and sampled data is detected, really
Whether the receives link for determining RRU occurs signal jam；
S202, when it is determined that the RRU receives link produce signal jam when, export interrupt signal to locate
Device is managed, control is adjusted to the gain of the receives link of the RRU by processor.
It is preferred that the FPGA samples to the ADC signals sent, and sampled data is examined
Survey, determine whether RRU receives link produces signal jam, specifically include：
The FPGA is in ascending time slot, after being counted to the power of the sampled data of predetermined number
Determine maximum power value；
For example, it may be FPGA is in ascending time slot, every 4096 sampled points carry out power statistic, from
The performance number of maximum is determined in the corresponding power of 4096 sampled points.
The maximum power value is compared by the FPGA with default scaled power value, when it is determined that described
When maximum power value is more than the default scaled power value, determine that the receives link of the RRU is believed
Number obstruction.
Above-mentioned default scaled power value, can set different scaled power values according to RRU difference, when
So, different RRU setting identicals scaled power value is also possible, and the embodiment of the present invention is not made to this
Limit.
Referring to Fig. 4, device is realized the embodiments of the invention provide a kind of RRU antiblockings, including：
Determining unit 11, for when receiving the interrupt signal of FPGA transmissions, determining RRU reception
Signal jam occurs for link；
Control unit 12, the gain for the receives link to the RRU is adjusted control.
The device that the RRU antiblockings are realized for example can be processor.
It is preferred that described control unit 12 specifically for：
Read from the FPGA by the FPGA in ascending time slot, to the sampled data of predetermined number
The maximum power value that power is determined after being counted, the sampled data is the FPGA to analog-digital converter
ADC send signal sampled after data；
Here, FPGA is in ascending time slot, after being counted to the power of the sampled data of predetermined number really
Determine maximum power value, for example can be FPGA in ascending time slot, every 4096 sampled points carry out power
Statistics, determines the performance number of maximum from the corresponding power of 4096 sampled points.
According to the maximum power value, it is determined that needing the gain to the receives link of the RRU to be adjusted
Yield value, and indicate gain of the gain regulation module according to the yield value to signal in the receives link
It is adjusted.
It is preferred that described control unit 12 is according to the maximum power value, it is determined that needing to the RRU's
The yield value that the gain of receives link is adjusted, and indicate the gain regulation module root in the receives link
When being adjusted according to the yield value to the gain of signal, specifically for：
According to the maximum power value and default scaled power value, it is determined that needing the signal to analog link
The first yield value that gain is adjusted, and need to be adjusted the signal gain of digital link second
Yield value；
By sending gain regulation module of first yield value to the analog link, the simulation is indicated
The gain of signal is lowered the first yield value by the gain regulation module of link, and is increased by sending described second
Benefit is worth the gain regulation module to the digital link, indicates the gain regulation module of the digital link and will believe
Number gain raise the second yield value.
In specific implementation, for example, can be that control unit 12 is sending first yield value to the mould
While intending the gain regulation module of link, carry one and indicate message, the instruction message is to indicate the mould
The gain of signal is lowered the first yield value, and control unit 12 in hair by the gain regulation module for intending link
Send second yield value give the digital link gain regulation module while, carry one indicate message,
The instruction message is to indicate that the gain regulation module of the digital link increases the gain up-regulation second of signal
Benefit value.In another example, control unit 12 can send first yield value according to the form made an appointment
To the gain regulation module of the analog link, so that the gain regulation module of the analog link receives this
After first yield value, it is possible to according to the form of first yield value, it is determined that the gain of signal is lowered into first
Yield value, and control unit 12 is according to the form made an appointment, and sends second yield value to described
The gain regulation module of digital link, so that the gain regulation module of the digital link receives second increasing
After benefit value, it is possible to according to the form of second yield value, it is determined that the gain of signal is raised into the second yield value.
It is preferred that described control unit 12 is in descending time slot, first yield value is sent to the simulation
The gain regulation module of link, and send Gain tuning mould of second yield value to the digital link
Block.
It is preferred that described control unit 12 is according to the maximum power value and default scaled power value,
It is determined that when needing the first yield value being adjusted to the signal gain of analog link, specifically for：
According to the maximum power value and default scaled power value, determine to be directed to signal using equation below
Obstruction needs the yield value PGC_bc being adjusted to the signal gain of analog link：
PGC_bc=PGC_bc'+ (P-P0)
Wherein, PGC_bc' represents the yield value that the last signal gain to the analog link is adjusted, P
Represent the maximum power value, P0Represent the default scaled power value；
By the PGC_bc, with it is default the need for the basic value that is adjusted to the signal gain of analog link
PGC0It is added, obtains first yield value.
Wherein, it is above-mentioned it is default the need for the basic value PGC that is adjusted to the signal gain of analog link0,
It is the gain adjustment value of acquiescence, for example, can is that the signal of analog link is increased the need for being calculated by temperature compensation
The yield value that benefit is adjusted.
It is preferred that described control unit 12 is according to the maximum power value and default scaled power value,
The second yield value being adjusted to the signal gain of digital link is needed, is specifically included：
By the PGC_bc, with it is default the need for logarithm word link the basic value that is adjusted of signal gain
AGC0It is added, obtains second yield value.
Wherein, basic value AGC0It is the gain adjustment value of acquiescence, for LTE system, AGC0For example may be used
- 1dB is thought, for TD-SCDMA system, AGC0For example can be 4dB.
It is preferred that the determining unit 11 is additionally operable to：
When be not received by FPGA transmission interrupt signal when, periodically read from the FPGA by
The FPGA is in ascending time slot, the maximum determined after being counted to the power of the sampled data of predetermined number
Performance number, the sampled data is after the FPGA samples to the analog-digital converter ADC signals sent
Data；
When the determining unit 11 determines the maximum power value read from the FPGA less than default fixed
Performance number is marked, and the absolute value of the difference of the maximum power value and default scaled power value is more than default door
During limit value, described control unit 12 is additionally operable to：Gain to the receives link of the RRU is adjusted control
System.
It is preferred that when the determining unit 11 determines that the maximum power value read from the FPGA is less than
Default scaled power value, and the absolute value of the difference of the maximum power value and default scaled power value is more than
During default thresholding, the gain of described control unit 12 in the following way to the receives link of the RRU
It is adjusted control：
According to the maximum power value and default scaled power value, it is determined that needing the signal increasing to analog link
The 3rd yield value that benefit is adjusted, and need the 4th increasing that is adjusted to the signal gain of digital link
Benefit value；
By sending gain regulation module of the 3rd yield value to the analog link, the simulation is indicated
The gain of signal is raised the 3rd yield value by the gain regulation module of link, and by sending the 4th increasing
Benefit is worth the gain regulation module to the digital link, indicates the gain regulation module of the digital link and will believe
Number gain lower the 4th yield value.
In specific implementation, for example, can be that control unit 12 is sending the 3rd yield value to the mould
While intending the gain regulation module of link, carry one and indicate message, the instruction message is to indicate the mould
The gain of signal is raised the 3rd yield value, and control unit 12 in hair by the gain regulation module for intending link
Send the 4th yield value give the digital link gain regulation module while, carry one indicate message,
Gain regulation module gain downward fourth increasing by signal of the instruction message to indicate the digital link
Benefit value.In another example, control unit 12 can send the 3rd yield value according to the form made an appointment
To the gain regulation module of the analog link, so that the gain regulation module of the analog link receives this
After 3rd yield value, it is possible to according to the form of the 3rd yield value, it is determined that the gain of signal is raised into the 3rd
Yield value, and control unit 12 is according to the form made an appointment, and sends the 4th yield value to described
The gain regulation module of digital link, so that the gain regulation module of the digital link receives the 4th increasing
After benefit value, it is possible to according to the form of the 4th yield value, it is determined that the gain of signal is lowered into the 4th yield value.
It is preferred that described control unit 12 is adopted according to the maximum power value and default scaled power value
The 3rd yield value for needing to be adjusted the signal gain of analog link is determined with equation below：
PGC_bc=PGC_bc'+ (P-P0)+3
Wherein, PGC_bc' represents the yield value that the last signal gain to the analog link is adjusted,
P represents the maximum power value, P0Represent the default scaled power value.
It is preferred that the 4th yield value is equal to the 3rd yield value.
Referring to Fig. 5, device is realized the embodiments of the invention provide another RRU antiblockings, the device includes：
Determining unit 21, for being sampled to the analog-digital converter ADC signals sent, and to hits
According to being detected, determine whether RRU receives link occurs signal jam；
Output unit 22, for when it is determined that the RRU receives link produce signal jam when, in output
Break signal is adjusted control by processor to processor to the gain of the receives link of the RRU.
The RRU antiblockings realize that device for example can be FPGA.
It is preferred that the determining unit 21 specifically for：
In ascending time slot, maximum work is determined after being counted to the power of the sampled data of predetermined number
Rate value；
The maximum power value is compared with default scaled power value, when it is determined that the maximum power value
During more than the default scaled power value, determine that signal jam occurs for the receives link of the RRU.
The embodiment of the present invention additionally provides a kind of RRU, and it is real that the RRU includes above two RRU antiblockings
Existing device.Certainly, the RRU can also include other functional modules in addition to including above two device.
In the embodiment of the present invention, above-mentioned each functional unit can be realized by entity devices such as hardware processors.
It should be understood by those skilled in the art that, embodiments of the invention can be provided as method, system or meter
Calculation machine program product.Therefore, the present invention can be using complete hardware embodiment, complete software embodiment or knot
The form of embodiment in terms of conjunction software and hardware.Wherein wrapped one or more moreover, the present invention can be used
Containing computer usable program code computer-usable storage medium (include but is not limited to magnetic disk storage and
Optical memory etc.) on the form of computer program product implemented.
The present invention is with reference to the production of method according to embodiments of the present invention, equipment (system) and computer program
The flow chart and/or block diagram of product is described.It should be understood that can by computer program instructions implementation process figure and
/ or each flow and/or square frame in block diagram and the flow in flow chart and/or block diagram and/
Or the combination of square frame.These computer program instructions can be provided to all-purpose computer, special-purpose computer, insertion
Formula processor or the processor of other programmable data processing devices are to produce a machine so that pass through and calculate
The instruction of the computing device of machine or other programmable data processing devices is produced for realizing in flow chart one
The device for the function of being specified in individual flow or multiple flows and/or one square frame of block diagram or multiple square frames.
These computer program instructions, which may be alternatively stored in, can guide computer or the processing of other programmable datas to set
In the standby computer-readable memory worked in a specific way so that be stored in the computer-readable memory
Instruction produce include the manufacture of command device, the command device realization in one flow or multiple of flow chart
The function of being specified in one square frame of flow and/or block diagram or multiple square frames.
These computer program instructions can be also loaded into computer or other programmable data processing devices, made
Obtain and perform series of operation steps on computer or other programmable devices to produce computer implemented place
Reason, so that the instruction performed on computer or other programmable devices is provided for realizing in flow chart one
The step of function of being specified in flow or multiple flows and/or one square frame of block diagram or multiple square frames.
Obviously, those skilled in the art can carry out various changes and modification without departing from this hair to the present invention
Bright spirit and scope.So, if the present invention these modifications and variations belong to the claims in the present invention and
Within the scope of its equivalent technologies, then the present invention is also intended to comprising including these changes and modification.
Claims (25)
1. a kind of radio frequency remote unit RRU antiblocking implementation method, it is characterised in that this method includes：
When receiving the interrupt signal of field-programmables array FPGA transmissions, RRU reception is determined
Signal jam occurs for link；
Gain to the receives link of the RRU is adjusted control.
2. according to the method described in claim 1, it is characterised in that to the receives link of the RRU
Gain is adjusted control, specifically includes：
Read from the FPGA by the FPGA in ascending time slot, to the sampled data of predetermined number
The maximum power value that power is determined after being counted, the sampled data is the FPGA to analog-digital converter
ADC send signal sampled after data；
According to the maximum power value, it is determined that needing the gain to the receives link of the RRU to be adjusted
Yield value, and indicate gain of the gain regulation module according to the yield value to signal in the receives link
It is adjusted.
3. method according to claim 2, it is characterised in that according to the maximum power value, really
The yield value that the fixed gain needed to the receives link of the RRU is adjusted, and indicate the reception chain
Gain regulation module in road is adjusted according to the yield value to the gain of signal, is specifically included：
According to the maximum power value and default scaled power value, it is determined that needing the signal to analog link
The first yield value that gain is adjusted, and need to be adjusted the signal gain of digital link second
Yield value；
By sending gain regulation module of first yield value to the analog link, the simulation is indicated
The gain of signal is lowered the first yield value by the gain regulation module of link, and is increased by sending described second
Benefit is worth the gain regulation module to the digital link, indicates the gain regulation module of the digital link and will believe
Number gain raise the second yield value.
4. method according to claim 3, it is characterised in that in descending time slot, described the is sent
One yield value gives the gain regulation module of the analog link, and sends second yield value to the number
The gain regulation module of word link.
5. method according to claim 3, it is characterised in that according to the maximum power value and
Default scaled power value, it is determined that the first yield value being adjusted to the signal gain of analog link is needed,
Specifically include：
According to the maximum power value and default scaled power value, determine to be directed to signal using equation below
Obstruction needs the yield value PGC_bc being adjusted to the signal gain of analog link：
PGC_bc=PGC_bc'+ (P-P0)
Wherein, PGC_bc' represents the yield value that the last signal gain to the analog link is adjusted, P
Represent the maximum power value, P0Represent the default scaled power value；
By the PGC_bc, with it is default the need for the basic value that is adjusted to the signal gain of analog link
PGC0It is added, obtains first yield value.
6. method according to claim 5, it is characterised in that according to the maximum power value and
Default scaled power value is, it is necessary to the second yield value that the signal gain to digital link is adjusted, specifically
Including：
By the PGC_bc, with it is default the need for logarithm word link the basic value that is adjusted of signal gain
AGC0It is added, obtains second yield value.
7. according to the method described in claim 1, it is characterised in that this method also includes：
When be not received by FPGA transmission interrupt signal when, periodically read from the FPGA by
The FPGA is in ascending time slot, the maximum determined after being counted to the power of the sampled data of predetermined number
Performance number, the sampled data is after the FPGA samples to the analog-digital converter ADC signals sent
Data；
When the maximum power value read from the FPGA is less than default scaled power value, and the maximum
When the absolute value of the difference of performance number and default scaled power value is more than default threshold value, to the RRU
The gain of receives link be adjusted control.
8. method according to claim 7, it is characterised in that when what is read from the FPGA
Maximum power value is less than default scaled power value, and the maximum power value and default scaled power value it
When the absolute value of difference is more than default thresholding, the gain to the receives link of the RRU is adjusted control,
Specifically include：
According to the maximum power value and default scaled power value, it is determined that needing the signal increasing to analog link
The 3rd yield value that benefit is adjusted, and need the 4th increasing that is adjusted to the signal gain of digital link
Benefit value；
By sending gain regulation module of the 3rd yield value to the analog link, the simulation is indicated
The gain of signal is raised the 3rd yield value by the gain regulation module of link, and by sending the 4th increasing
Benefit is worth the gain regulation module to the digital link, indicates the gain regulation module of the digital link and will believe
Number gain lower the 4th yield value.
9. method according to claim 8, it is characterised in that according to the maximum power value and in advance
If scaled power value, determine to need to be adjusted the signal gain of analog link using equation below the
Three yield values：
PGC_bc=PGC_bc'+ (P-P0)+3
Wherein, PGC_bc' represents the yield value that the last signal gain to the analog link is adjusted, P
Represent the maximum power value, P0Represent the default scaled power value.
10. method according to claim 8 or claim 9, it is characterised in that the 4th yield value is equal to
3rd yield value.
11. a kind of radio frequency remote unit RRU antiblocking implementation method, it is characterised in that this method includes：
Field-programmables array FPGA samples to the analog-digital converter ADC signals sent, and right
Sampled data is detected, determines whether RRU receives link occurs signal jam；
When it is determined that the receives link of the RRU produces signal jam, interrupt signal is exported to processor,
Control is adjusted to the gain of the receives link of the RRU by processor.
12. method according to claim 11, it is characterised in that the FPGA is sent to ADC
Signal sampled, and sampled data is detected, determines whether RRU receives link produces letter
Number obstruction, specifically include：
The FPGA is in ascending time slot, after being counted to the power of the sampled data of predetermined number
Determine maximum power value；
The maximum power value is compared by the FPGA with default scaled power value, when it is determined that described
When maximum power value is more than the default scaled power value, determine that the receives link of the RRU is believed
Number obstruction.
13. device is realized in a kind of radio frequency remote unit RRU antiblocking, it is characterised in that the device includes：
Determining unit, for when receive field-programmables array FPGA transmission interrupt signal when, really
Signal jam occurs for the receives link for determining RRU；
Control unit, the gain for the receives link to the RRU is adjusted control.
14. device according to claim 13, it is characterised in that described control unit specifically for：
Read from the FPGA by the FPGA in ascending time slot, to the sampled data of predetermined number
The maximum power value that power is determined after being counted, the sampled data is the FPGA to analog-digital converter
ADC send signal sampled after data；
According to the maximum power value, it is determined that needing the gain to the receives link of the RRU to be adjusted
Yield value, and indicate gain of the gain regulation module according to the yield value to signal in the receives link
It is adjusted.
15. device according to claim 14, it is characterised in that described control unit is according to described
Maximum power value, it is determined that the yield value that the gain to the receives link of the RRU is adjusted is needed, and
When indicating that the gain regulation module in the receives link is adjusted according to the yield value to the gain of signal,
Specifically for：
According to the maximum power value and default scaled power value, it is determined that needing the signal to analog link
The first yield value that gain is adjusted, and need to be adjusted the signal gain of digital link second
Yield value；
By sending gain regulation module of first yield value to the analog link, the simulation is indicated
The gain of signal is lowered the first yield value by the gain regulation module of link, and is increased by sending described second
Benefit is worth the gain regulation module to the digital link, indicates the gain regulation module of the digital link and will believe
Number gain raise the second yield value.
16. device according to claim 15, it is characterised in that described control unit is when descending
Gap, sends gain regulation module of first yield value to the analog link, and send described second
Yield value gives the gain regulation module of the digital link.
17. device according to claim 15, it is characterised in that described control unit is according to described
Maximum power value and default scaled power value, it is determined that needing to be adjusted the signal gain of analog link
The first yield value when, specifically for：
According to the maximum power value and default scaled power value, determine to be directed to signal using equation below
Obstruction needs the yield value PGC_bc being adjusted to the signal gain of analog link：
PGC_bc=PGC_bc'+ (P-P0)
Wherein, PGC_bc' represents the yield value that the last signal gain to the analog link is adjusted, P
Represent the maximum power value, P0Represent the default scaled power value；
By the PGC_bc, with it is default the need for the basic value that is adjusted to the signal gain of analog link
PGC0It is added, obtains first yield value.
18. device according to claim 17, it is characterised in that described control unit is according to described
Maximum power value and default scaled power value, it is necessary to the signal gain to digital link be adjusted
Two yield values, are specifically included：
By the PGC_bc, with it is default the need for logarithm word link the basic value that is adjusted of signal gain
AGC0It is added, obtains second yield value.
19. device according to claim 13, it is characterised in that the determining unit is additionally operable to：
When be not received by FPGA transmission interrupt signal when, periodically read from the FPGA by
The FPGA is in ascending time slot, the maximum determined after being counted to the power of the sampled data of predetermined number
Performance number, the sampled data is after the FPGA samples to the analog-digital converter ADC signals sent
Data；
When the determining unit determines that the maximum power value read from the FPGA is less than default calibration work(
Rate value, and the absolute value of the difference of the maximum power value and default scaled power value is more than default threshold value
When, described control unit is additionally operable to：Gain to the receives link of the RRU is adjusted control.
20. device according to claim 19, it is characterised in that when the determining unit determine from
The maximum power value read in the FPGA be less than default scaled power value, and the maximum power value with
When the absolute value of the difference of default scaled power value is more than default thresholding, described control unit uses such as lower section
Gain of the formula to the receives link of the RRU is adjusted control：
According to the maximum power value and default scaled power value, it is determined that needing the signal increasing to analog link
The 3rd yield value that benefit is adjusted, and need the 4th increasing that is adjusted to the signal gain of digital link
Benefit value；
By sending gain regulation module of the 3rd yield value to the analog link, the simulation is indicated
The gain of signal is raised the 3rd yield value by the gain regulation module of link, and by sending the 4th increasing
Benefit is worth the gain regulation module to the digital link, indicates the gain regulation module of the digital link and will believe
Number gain lower the 4th yield value.
21. device according to claim 20, it is characterised in that described control unit according to this most
High-power value and default scaled power value, determine to need the signal increasing to analog link using equation below
The 3rd yield value that benefit is adjusted：
PGC_bc=PGC_bc'+ (P-P0)+3
Wherein, PGC_bc' represents the yield value that the last signal gain to the analog link is adjusted,
P represents the maximum power value, P0Represent the default scaled power value.
22. the device according to claim 20 or 21, it is characterised in that described 4th yield value etc.
In the 3rd yield value.
23. device is realized in a kind of radio frequency remote unit RRU antiblocking, it is characterised in that the device includes：
Determining unit, for being sampled to the analog-digital converter ADC signals sent, and to sampled data
Detected, determine whether RRU receives link occurs signal jam；
Output unit, for when it is determined that the receives link of the RRU produces signal jam, output to be interrupted
Signal is adjusted control by processor to processor to the gain of the receives link of the RRU.
24. device according to claim 23, it is characterised in that the determining unit specifically for：
In ascending time slot, maximum work is determined after being counted to the power of the sampled data of predetermined number
Rate value；
The maximum power value is compared with default scaled power value, when it is determined that the maximum power value
During more than the default scaled power value, determine that signal jam occurs for the receives link of the RRU.
25. a kind of radio frequency remote unit RRU, it is characterised in that the device includes claim 13~22
Device described in any claim, and the device described in claim 23 or 24.
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| CN201610165780.4A CN107222888A (en) | 2016-03-22 | 2016-03-22 | A kind of RRU antiblockings implementation method and device, RRU |
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| CN116600377A (en) * | 2023-07-17 | 2023-08-15 | 南京典格通信科技有限公司 | Uplink receiving gain control method based on remote radio unit |
| CN116600377B (en) * | 2023-07-17 | 2023-10-03 | 南京典格通信科技有限公司 | Uplink receiving gain control method based on remote radio unit |
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Application publication date: 20170929 |