CN107222256B

CN107222256B - FPGA-based SRIO optical fiber link online re-linking realization method

Info

Publication number: CN107222256B
Application number: CN201710523987.9A
Authority: CN
Inventors: 赵峰; 邹林辰; 吴彬
Original assignee: Leihua Electronic Technology Research Institute Aviation Industry Corp of China
Current assignee: Leihua Electronic Technology Research Institute Aviation Industry Corp of China
Priority date: 2017-06-30
Filing date: 2017-06-30
Publication date: 2019-12-17
Anticipated expiration: 2037-06-30
Also published as: CN107222256A

Abstract

The invention provides a method for realizing SRIO optical fiber link on-line re-linking based on an FPGA, and relates to the technical field of communication. The method monitors the connection and disconnection of the optical fiber link between the radar and the recorder at any moment, and controls the FPGA logic to reset the link to try to reestablish the optical fiber link no matter what reason the link is disconnected. In the monitoring process, the rising edge of the port _ initialized is detected by using the delay state of the port _ initialized or the link _ initialized of the SRIO is detected to be 0, if the condition is true, the link reconnection is carried out, otherwise, the rising edge of the port _ initialized and the value of the link _ initialized are continuously monitored. By the method, the on-off condition of the SRIO optical fiber link can be judged quickly, and the link can be established quickly.

Description

FPGA-based SRIO optical fiber link online re-linking realization method

Technical Field

the invention relates to the technical field of communication, in particular to an FPGA-based SRIO optical fiber link online re-linking implementation method.

background

the SRIO is a serial RapidIO technology, the RapidIO technology is a high-speed interconnection technology which is high in performance, high in reliability, low in time delay and low in pin number and is based on message exchange, the high-speed interconnection technology comprises parallel RapidIO technology and serial RapidIO technology, a parallel interface mainly faces to interconnection of 8-bit or 16-bit parallel links of a high-performance microprocessor, a network processor and a high-performance backboard, and the transmission distance of the parallel interface is limited. The serial interface generally realizes high-speed serial interconnection between a high-performance DSP, an FPGA, a microprocessor or a backboard in a 1x, 2x or 4x mode, and a serial RapidIO technology (SRIO) is widely applied due to the characteristics of longer transmission distance, higher reliability and less pin number.

The FPGA is a programmable logic device, has programmable flexibility which other integrated circuit chips do not have, and has abundant I/O pins, short development period and high reliability. A Serial RapidIO core of Xilinx company can conveniently realize an interface protocol of SRIO on an FPGA device, wherein a Serial RapidIO Gen2v3.2 version IP core supported by Virtex-7 series devices can realize single-channel data transmission of 6.25Gbps at most. A GTX transceiver of SerialRapidIO IP core bottom layer hardware based on an FPGA supports interface modes of various bit widths of 1x, 2x and 4x, and in Virtex-7 series devices, an SRIO IP core is realized by using a latest AXI4 interface protocol. The complete Serial RapidIO endpoint IP core discovery scheme includes four parts: a Serial RapidIO physical layer protocol IP core (PHY), a logic (I/O) and transport layer IP core (LOG), a data buffering IP core, and associated logic to control clock, reset, and configuration information.

An optical fiber link between a radar and a recorder has an establishing process, and when the radar and the recorder are powered on and an optical fiber ST or LC interface between the radar and the recorder is connected, if an SRIO module does not perform effective reset, the link establishment can be failed. In addition, if the SRIO optical fiber link is established and the link is disconnected due to some burst reasons, the data transmission may also fail if the SRIO optical fiber link is reestablished without monitoring the state of the SRIO optical fiber link in the FPGA and performing effective reset.

disclosure of Invention

In order to solve the above problems, the present invention provides a method for implementing SRIO optical fiber link on-line re-linking based on FPGA. The method aims to monitor the connection and disconnection of the optical fiber link between the radar and the recorder at any moment, and if the link is disconnected, the FPGA logic is controlled to perform link reset to try to reestablish the optical fiber link.

The implementation method mainly comprises the following steps:

Step one, acquiring a port _ initialized variable value and a link _ initialized variable value on an SRIO link in a period;

Step two, if the port _ initialized variable value is in a rising edge or the link _ initialized variable value is 0, continuing to execute the step three, otherwise, returning to the step one, and re-taking the value in the next period, wherein the rising edge refers to that the port _ initialized variable value is in a rising trend in the continuous period;

Step three, starting a timer, and timing for 4 seconds;

Step four, starting a reset instruction, and effectively keeping the reset for 2 seconds;

And step five, after the resetting is finished, waiting for 2 seconds, then returning to the step one, and repeatedly executing the process.

Preferably, in the first step, the clock frequency of the period is 200 Mhz.

Preferably, in the second step, the determining that the port _ initialized variable is at a rising edge includes: detecting a port _ initialized variable value for the first time; delaying for one period, and detecting the value of the port _ initialized variable for the second time; the second detection value is greater than the first detection value.

By the method, the clock period is used as the minimum time interval, the detection of the two variables in the link is continuously carried out to judge whether the SRIO link needs to be reconnected, and when the SRIO link needs to be reconnected, the reconnection step is started to realize link reset to try to reestablish the optical fiber link.

The invention can be applied to the on-line re-linking of the SRIO optical fiber link based on the FPGA between the radar and the recorder, and can be popularized to the on-line re-linking of any SRIO link based on the FPGA.

Drawings

Fig. 1 is a flowchart of a preferred embodiment of an implementation method for SRIO optical fiber link online re-linking based on FPGA according to the present invention.

Fig. 2 is a block diagram of an SRIO optical fiber link structure between a radar signal processing board and a recorder.

DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION

In order to make the implementation objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be described in more detail below with reference to the accompanying drawings in the embodiments of the present invention. In the drawings, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The described embodiments are only some, but not all embodiments of the invention. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

The invention discloses a method for realizing SRIO (remote sensing input/output) optical fiber link online re-linking based on an FPGA (field programmable gate array), which aims to monitor the on-off of an optical fiber link between a radar and a recorder at any moment and control FPGA logic to perform link resetting to try to reestablish the optical fiber link no matter what reason the link is disconnected.

The RapidIO interconnection architecture is a point-to-point packet switching technology, supports interconnection and communication between chips and between boards, and has a data transmission rate of 1Gbps to 60 Gbps. The RapidIO interconnection system structure is divided into three layers, namely a logic layer, a transmission layer and a physical layer. The logic layer specification is positioned at the highest layer, defines all operation protocols and packet formats and provides necessary information for initiating and completing transactions by an end device; the transmission layer specification is positioned in the middle layer of the protocol layer, and the layer defines the address space, the addressing mechanism and the routing information for packet switching of RapidIO; the physical layer specification is at the bottom level and includes details of the device level interface such as packet transport mechanisms, flow control, electrical parameters, and low level error management.

Fig. 2 is a block diagram of an SRIO optical fiber link structure between a radar signal processing board and a recorder according to the present invention. In the field of radar signal processing, data is typically transmitted between a radar signal processing board and a recorder via an optical fiber link. Firstly, data are packaged and sent to a four-path parallel light receiving and transmitting integrated module by an FPGA (field programmable gate array) on a radar signal processing board according to an SRIO (serial read input output) protocol, an optical module converts an electric signal into an optical signal and sends the optical signal to an optical fiber link, the optical fiber is connected with a recorder through four paths of ST (system test) or LC (liquid crystal) receiving and transmitting interfaces, and the data are transmitted to the recorder through the optical fiber, converted into digital signals through inverse transformation and stored.

Calling the SRIO IP core of the FPGA, and when the link is established, the method has the following characteristics: if the link is disconnected, port _ initialized is a vertical jump or link _ initialized is 0 (for example, disconnection of the right optical fiber ST or LC interface from the recorder interface in fig. 2 may cause vertical jump of port initialization, and link _ initialized is 0, and even if the interface is reconnected, the state may be maintained, and if the disconnection state of the SRIO optical fiber link is not monitored in the FPGA and is effectively reset, the link is reestablished, and data transmission failure may also be caused), and with this feature, the present technology detects these two signals on a logic algorithm of the FPGA, and performs SRIO link reset, so that the SRIO link decision step includes the following specific steps:

step three, starting a timer, and timing for 4 seconds;

in this embodiment, in the first step, the detection is performed once every clock cycle, and the clock frequency is 200 Mhz.

in this embodiment, in the second step, the determining that the port _ initialized variable is on a rising edge includes: detecting a port _ initialized variable value for the first time; delaying for one period, and detecting the value of the port _ initialized variable for the second time; the second detection value is greater than the first detection value. For example, steps one through two may be modified as: delaying the port _ initialized of the SRIO by 1 clock cycle, and entering an initial state; in the initial state, the counter is cleared, the reset signal is set to 0, and the next step is carried out; and judging the state, detecting the rising edge of the port _ initialized or detecting that the link _ initialized of the SRIO is 0 by using the delay state of the port _ initialized, if the condition is true, entering the next step, and if not, continuously monitoring the rising edge of the port _ initialized or the link _ initialized is 0.

In the technical scheme, the time required by reestablishing the SRIO link is considered, so that the reset signal is restored to 0, namely after the SRIO link is failed, the next detection judgment state of the port _ initialized and link _ initialized signals is kept for 2 seconds. The heavy chain connection implementation method takes 8 seconds and comprises a waiting state, a resetting state and a holding state, wherein the resetting signal is set to be 1 and is valid, and the resetting signal is set to be 0 and is invalid. Referring to fig. 1 specifically, in the standby state, after the counter counts 4 seconds, the reset signal is set to 1, and the next step is performed; resetting the state, after the counter counts for 2 seconds, setting a reset signal to be 0, and entering the next step; keeping the state, after the counter counts for 2 seconds, ensuring that the reset is completed, reestablishing the link, jumping back to the monitoring steps of the two variables, and continuously monitoring the link state.

finally, it should be pointed out that: the above examples are only for illustrating the technical solutions of the present invention, and are not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. an implementation method for SRIO optical fiber link online re-linking based on FPGA is characterized by comprising the following steps:

Step two, if the port _ initialized variable value is in an ascending stage or the link _ initialized variable value is 0, continuing to execute the step three, otherwise, returning to the step one to re-take the value in the next period, wherein the ascending stage means that the port _ initialized variable value is in an ascending trend in the continuous period;

Step three, starting a timer, and timing for 4 seconds;

2. the method for implementing SRIO fiber link on-line re-linking based on FPGA of claim 1, wherein in the first step, a clock frequency of a cycle is 200 Mhz.

3. The method for implementing SRIO fiber link on-line re-linking based on FPGA of claim 1, wherein in the second step, the determining that the port _ initialized variable is in the ascending phase includes: detecting a port _ initialized variable value for the first time; delaying for one period, and detecting the value of the port _ initialized variable for the second time; the second detection value is greater than the first detection value.