CN107222194A - A kind of SVG and TSC mixing reactive-load compensation level controllers and its control method - Google Patents
A kind of SVG and TSC mixing reactive-load compensation level controllers and its control method Download PDFInfo
- Publication number
- CN107222194A CN107222194A CN201710376179.4A CN201710376179A CN107222194A CN 107222194 A CN107222194 A CN 107222194A CN 201710376179 A CN201710376179 A CN 201710376179A CN 107222194 A CN107222194 A CN 107222194A
- Authority
- CN
- China
- Prior art keywords
- tsc
- driving
- latch
- svg
- buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
- H03K19/017536—Interface arrangements using opto-electronic devices
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Control Of Electrical Variables (AREA)
Abstract
The invention discloses a kind of SVG and TSC mixing reactive-load compensation level controllers and its control method, SVG controller MCU I/O ports are connected with latch arrays, latch arrays are connected with Darlington type optocoupler array, and Darlington type optocoupler array exports multiple in the TSC switchings level signal of MCU I/O ports and is connected with TSC.More Automatic level control is realized in the I/O ports that the present invention has occupancy MCU less, and has the advantages that strong integrated level height, driving force, strong applicability, cost performance are high, expansible.
Description
Technical field
The invention belongs to the technical field of Automatic level control, and in particular to a kind of SVG and TSC mixing reactive-load compensation level controls
Device processed and its control method.
Background technology
As the change in distribution system is frequent, impact inductive load extensive application, especially mash welder, steel rolling
The load that the reactive power pace of change such as machine, stamping machine is fast, the duration is short, amplitude of variation is big, causes power distribution system voltage to fall
Fall, flickering, power factor reduction is easily caused the sensitiveness load misoperation such as accurate production equipment, laboratory apparatus, or even can not be just
Normal production work, therefore it is required that reactive power compensator quick, stepless, can be compensated continuously.Consideration based on cost, it is existing
Compensated usually using static reacance generator (SVG) with the mode that multigroup thyristor series capacitor (TSC) is combined, TSC
Device grading compensation systematic steady state reactive requirement, the idle need of transient state that the SVG device of low capacity is mended to compensate TSC grading compensations to owe
Ask.In order to it is quick, stepless, continuously compensate, need coordination rapidly and efficiently to control between SVG and TSC.
To solve the above problems, existing processing mode mainly has:
Communicated between SVG and TSC using RS485, but this communication mode speed is slower.
Automatic level control mode is used between SVG and TSC, this needs more Automatic level control port, it is therefore desirable to I/O ports
More MCU or use FPGA expansion I/Os port so that control device is complicated, and cost is higher.
The content of the invention
The technical problems to be solved by the invention are that there is provided one kind occupancy MCU is less for above-mentioned the deficiencies in the prior art
I/O ports realize more Automatic level control, and with integrated level is high, driving force is strong, strong applicability, cost performance are high, can
SVG and TSC the mixing reactive-load compensation level controller and its control method of extension.
A kind of SVG and TSC mixing reactive-load compensation level controllers, SVG controller MCU I/O ports are with latching
Device array is connected, and latch arrays are connected with Darlington type optocoupler array, and Darlington type optocoupler array exports multiple in MCU I/
The TSC switchings level signal of O port is simultaneously connected with TSC.
For optimization above-mentioned technical proposal, the concrete measure taken also includes:
Driving buffer circuit is set between above-mentioned MCU and latch arrays, and MCU is connected with driving buffer circuit, driving buffering
Circuit is connected with latch arrays.
Above-mentioned SVG controller MCU includes I/O port power input VCC, I/O port earth terminal GND, output TSC
Switching level controling signal I/O port S0 ~ S7 and latch enable signal I/O port S8 ~ S15, wherein, the input of I/O port powers
End VCC meets power supply VCC1, I/O port earth terminal GND ground connection GND1, output TSC switching level controling signal I/O port S0 ~ S7
Respectively to input 1A1 ~ 1A4,2A1 ~ 2A4 for the first driving/buffer U2 for driving buffer circuit, latch and enable signal I/O
Port S8 ~ S15 is respectively to input 1A1 ~ 1A4,2A1 ~ 2A4 for the second driving/buffer U3 for driving buffer circuit.
Above-mentioned driving buffer circuit is used to strengthen the driving force of MCU I/O ports, and driving buffer circuit includes first
Driving/buffer U2, the second driving/buffer U3 and pull down resistor R129 ~ R144, the first driving/buffer U2 are 8
Driven in phase/buffer, the second driving/buffer U3 is 8 anti-driven in phase/buffers, the first driving/buffer U2, the
Two drivings/buffer U3 power input VCC meets power supply VCC1, and output Enable Pin and earth terminal GND are grounded GND1,
Pull down resistor R129 ~ R136 be parallel to respectively the first driving/buffer U2 input 1A1 ~ 1A4,2A1 ~ 2A4 and GND1 it
Between, pull down resistor R137 ~ R144 is parallel to the second driving/buffer U3 input 1A1 ~ 1A4,2A1 ~ 2A4 and GND1 respectively
Between.
Above-mentioned latch arrays are used to be multiplexed SVG controllers MCU I/O ports, non-comprising 8 states output of eight tunnel 3
Transparent latch U4 ~ U11 is inverted, latch U4 ~ U11 power input VCC connects power supply VCC1, output Enable Pin and ground connection
End GND is grounded GND1, and signal input part D0 ~ D7 is in parallel respectively and is connected to the U2 of driving buffer circuit output end
1Y1 ~ 1Y4,2Y1 ~ 2Y4, latch output end 1Y1 ~ 1Y4,2Y1 ~ 2Y4 that Enable Pin is connected to the U3 of driving buffer circuit.
Above-mentioned Darlington type optocoupler array includes current-limiting resistance R1 ~ R128 and Darlington type optocoupler U12 ~ U76, current limliting
Resistance R1 ~ R64 one end is connected to latch U4 ~ U11 output end Q0 ~ Q7, and the other end is connected to Darlington type light
Coupling U12 ~ U76 anode input, Darlington type optocoupler U12 ~ U76 negative electrode input is grounded GND1, and colelctor electrode connects electricity
Source VCC2, emitter stage is connected to current-limiting resistance R65 ~ R128 one end, and current-limiting resistance R65 ~ R128 other end and TSC connect
Connect and export final TSC switching level signals.
A kind of SVG and TSC mixing reactive-load compensation level control methods, are comprised the following steps:
Step 1:Static reacance generator SVG controllers MCU sets low signal S0 ~ S7, juxtaposition low signal S8 ~ S15, and then puts again
High RST S8 ~ S15, the latch for enabling all latch enables input so that all latch are output as low level signal, enter
And all Darlington type optocouplers are off state, so that all TSC are initially into excision state;
Step 2:MCU sends first group of 8 switching signal S0 ~ S7, juxtaposition low signal S8, the latch for the first latch U4 that fail
Input is enabled, high RST S8 is and then put again, the latch for enabling first latch U4 enables input, and then by switching signal S0
~ S7 is latched in first latch U4 output end so that corresponding 8 Darlington type optocouplers according to signal S0 ~ S7 conducting or
Person turns off, and level controling signal is provided, so as to be precisely controlled corresponding each TSC switching state.
The present invention compared with prior art, without increase MCU I/O ports on the basis of, by latch arrays with
The cooperation of Darlington type optocoupler array, by exponentially adding Automatic level control port.But MCU is in itself without enough drivings
Ability drives latch arrays, therefore, is used to strengthen the driving energy of MCU I/O ports invention increases driving buffer circuit
Power, enables latch arrays normal operation.The present invention has advantage and effect:Using less device, MCU is taken less
I/O ports realize more Automatic level control, and with integrated level is high, driving force is strong, strong applicability, cost performance are high, can
The characteristics of extension.
Brief description of the drawings
Fig. 1 is the circuit diagram of the present invention.
Embodiment
Embodiments of the invention are described in further detail below in conjunction with accompanying drawing.
A kind of SVG and TSC mixing reactive-load compensation level controllers of the present invention, can be placed in inside SVG, such as Fig. 1 institutes
Show, include SVG controllers MCU, driving buffer circuit, latch arrays, Darlington type optocoupler array.SVG controllers MCU is with driving
Dynamic buffer circuit connection, driving buffer circuit is connected with latch arrays, and latch arrays are connected with Darlington type optocoupler array.
SVG controllers MCU I/O port power inputs VCC connects power supply VCC1, I/O port earth terminal GND ground connection
GND1, exports TSC switching level controling signals(It is designated as S0 ~ S7)I/O ports are respectively to the input for the U2 for driving buffer circuit
1A1 ~ 1A4,2A1 ~ 2A4, latch and enable signal(It is designated as S8 ~ S15)I/O ports are respectively to the input for the U3 for driving buffer circuit
1A1~1A4、2A1~2A4。
The driving force of buffer circuit enhancing MCU I/O ports is driven, comprising 8 driven in phase with ternary output/
Buffer U2,8 bit Inverting drivings/buffer U3, pull down resistor R129 ~ R144 with ternary output.Driving/buffer U2,
U3 power input VCC meets power supply VCC1, and output Enable Pin and earth terminal GND are grounded GND1.Pull down resistor R129 ~
R136 is parallel to U2 input 1A1 ~ 1A4,2A1 ~ between 2A4 and GND1 respectively.Pull down resistor R137 ~ R144 is parallel to respectively
U3 input 1A1 ~ 1A4,2A1 ~ between 2A4 and GND1.
Latch arrays are used for the I/O ports for being multiplexed SVG controllers MCU, and the non-inverted comprising 8 state outputs of eight tunnel 3 is saturating
Bright latch U4 ~ U11.Latch U4 ~ U11 power input VCC meets power supply VCC1, output Enable Pin and earth terminal GND
Be grounded GND1, signal input part D0 ~ D7 it is in parallel respectively and be connected to the U2 of driving buffer circuit output end 1Y1 ~
1Y4,2Y1 ~ 2Y4, latch output end 1Y1 ~ 1Y4,2Y1 ~ 2Y4 that Enable Pin is connected to the U3 of driving buffer circuit.
Darlington type optocoupler array can export larger driving current compared with common optical coupler, device is had stronger driving
Ability, and for isolating SVG controller power sources so that the level magnitude of output signal can be supplied according to being actually needed for TSC
Electricity, makes SVG go for the TSC of varying level signal, includes current-limiting resistance R1 ~ R128, Darlington type optocoupler U12 ~ U76.
Current-limiting resistance R1 ~ R64 one end is connected to latch U4 ~ U11 output end Q0 ~ Q7, and the other end is connected to Darlington
Type optocoupler U12 ~ U76 anode input.Darlington type optocoupler U12 ~ U76 negative electrode input is grounded GND1, and colelctor electrode is equal
Power supply VCC2 is met, emitter stage is connected to current-limiting resistance R65 ~ R128 one end, and the current-limiting resistance R65 ~ R128 other end is defeated
Go out final TSC switching level signals.
Based on said apparatus, control method is comprised the following steps:
Step 1:Static reacance generator SVG controllers MCU sets low signal S0 ~ S7, juxtaposition low signal S8 ~ S15, and then puts again
High RST S8 ~ S15, the latch for enabling all latch enables input so that all latch are output as low level signal, enter
And all Darlington type optocouplers are off state, so that all TSC are initially into excision state;
Step 2:MCU sends first group of 8 switching signal S0 ~ S7, juxtaposition low signal S8, the latch for the first latch U4 that fail
Input is enabled, high RST S8 is and then put again, the latch for enabling first latch U4 enables input, and then by switching signal S0
~ S7 is latched in first latch U4 output end so that corresponding 8 Darlington type optocouplers according to signal S0 ~ S7 conducting or
Person turns off, and level controling signal is provided, so as to be precisely controlled corresponding each TSC switching state.
Above-mentioned steps 2 are equally used for other latch, corresponding each TSC switching state can be precisely controlled.
Level controller can take MCU 16 pins, export 64 level controling signals, significantly improved level
Control signal fan-out capability, but it is not limited to this according to the present invention program.
It the above is only the preferred embodiment of the present invention, protection scope of the present invention is not limited merely to above-described embodiment,
All technical schemes belonged under thinking of the present invention belong to protection scope of the present invention.It should be pointed out that for the art
For those of ordinary skill, some improvements and modifications without departing from the principles of the present invention should be regarded as the protection of the present invention
Scope.
Claims (7)
1. a kind of SVG and TSC mixing reactive-load compensation level controllers, it is characterized in that:SVG controller MCU I/O ports
Be connected with latch arrays, latch arrays are connected with Darlington type optocoupler array, Darlington type optocoupler array export multiple in
The TSC switchings level signal of MCU I/O ports is simultaneously connected with TSC.
2. a kind of SVG according to claim 1 and TSC mixing reactive-load compensation level controllers, it is characterized in that:MCU
Driving buffer circuit is set between latch arrays, and MCU is connected with driving buffer circuit, driving buffer circuit and latch battle array
Row connection.
3. a kind of SVG according to claim 2 and TSC mixing reactive-load compensation level controllers, it is characterized in that:It is described
SVG controller MCU include I/O port power input VCC, I/O port earth terminal GND, output TSC switching Automatic level controls
Signal I/O ports S0 ~ S7 and latch enable signal I/O port S8 ~ S15, wherein, I/O port power inputs VCC connects power supply
VCC1, I/O port earth terminal GND are grounded GND1, and output TSC switching level controling signal I/O port S0 ~ S7 is slow to driving respectively
The first driving/buffer U2 of circuit input 1A1 ~ 1A4,2A1 ~ 2A4 is rushed, latches and enables signal I/O port S8 ~ S15 points
Not to input 1A1 ~ 1A4,2A1 ~ 2A4 for the second driving/buffer U3 for driving buffer circuit.
4. a kind of SVG according to claim 3 and TSC mixing reactive-load compensation level controllers, it is characterized in that:It is described
Driving buffer circuit be used to strengthening the driving force of MCU I/O ports, described driving buffer circuit include the first driving/
Buffer U2, the second driving/buffer U3 and pull down resistor R129 ~ R144, described the first driving/buffer U2 are 8
Driven in phase/buffer, the second driving/buffer U3 is 8 anti-driven in phase/buffers, described the first driving/buffer
U2, the second driving/buffer U3 power input VCC meet power supply VCC1, and output Enable Pin and earth terminal GND are grounded
GND1, pull down resistor R129 ~ R136 be parallel to respectively the first driving/buffer U2 input 1A1 ~ 1A4,2A1 ~ 2A4 with
Between GND1, pull down resistor R137 ~ R144 is parallel to the second driving/buffer U3 input 1A1 ~ 1A4,2A1 ~ 2A4 respectively
Between GND1.
5. a kind of SVG according to claim 4 and TSC mixing reactive-load compensation level controllers, it is characterized in that:It is described
Latch arrays be used to be multiplexed SVG controllers MCU I/O ports, the non-inverted for including 8 states outputs of eight tunnel 3 is transparent to latch
Device U4 ~ U11, latch U4 ~ U11 power input VCC meet power supply VCC1, and output Enable Pin and earth terminal GND are grounded
GND1, signal input part D0 ~ D7 it is in parallel respectively and be connected to the U2 of driving buffer circuit output end 1Y1 ~ 1Y4,2Y1 ~
2Y4, latches output end 1Y1 ~ 1Y4,2Y1 ~ 2Y4 that Enable Pin is connected to the U3 of driving buffer circuit.
6. a kind of SVG according to claim 5 and TSC mixing reactive-load compensation level controllers, it is characterized in that:It is described
Darlington type optocoupler array include current-limiting resistance R1 ~ R128 and Darlington type optocoupler U12 ~ U76, current-limiting resistance R1 ~ R64 mono-
End is connected to latch U4 ~ U11 output end Q0 ~ Q7, and the other end is connected to Darlington type optocoupler U12 ~ U76 sun
Pole input, Darlington type optocoupler U12 ~ U76 negative electrode input is grounded GND1, and colelctor electrode meets power supply VCC2, emitter stage
Current-limiting resistance R65 ~ R128 one end is connected to, the current-limiting resistance R65 ~ R128 other end is connected with TSC and exports final
TSC switching level signals.
7. a kind of SVG and TSC mixing reactive-load compensation level control methods, it is characterized in that:Comprise the following steps:
Step 1:Static reacance generator SVG controllers MCU sets low signal S0 ~ S7, juxtaposition low signal S8 ~ S15, and then puts again
High RST S8 ~ S15, the latch for enabling all latch enables input so that all latch are output as low level signal, enter
And all Darlington type optocouplers are off state, so that all TSC are initially into excision state;
Step 2:MCU sends first group of 8 switching signal S0 ~ S7, juxtaposition low signal S8, the latch for the first latch U4 that fail
Input is enabled, high RST S8 is and then put again, the latch for enabling first latch U4 enables input, and then by switching signal S0
~ S7 is latched in first latch U4 output end so that corresponding 8 Darlington type optocouplers according to signal S0 ~ S7 conducting or
Person turns off, and level controling signal is provided, so as to be precisely controlled corresponding each TSC switching state.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710376179.4A CN107222194A (en) | 2017-05-25 | 2017-05-25 | A kind of SVG and TSC mixing reactive-load compensation level controllers and its control method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710376179.4A CN107222194A (en) | 2017-05-25 | 2017-05-25 | A kind of SVG and TSC mixing reactive-load compensation level controllers and its control method |
Publications (1)
Publication Number | Publication Date |
---|---|
CN107222194A true CN107222194A (en) | 2017-09-29 |
Family
ID=59945127
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710376179.4A Pending CN107222194A (en) | 2017-05-25 | 2017-05-25 | A kind of SVG and TSC mixing reactive-load compensation level controllers and its control method |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN107222194A (en) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6886089B2 (en) * | 2002-11-15 | 2005-04-26 | Silicon Labs Cp, Inc. | Method and apparatus for accessing paged memory with indirect addressing |
CN101769701A (en) * | 2008-12-31 | 2010-07-07 | 吉林市北华航天科技有限公司 | Multifunctional remote electronic ignition system |
CN102289905A (en) * | 2011-07-26 | 2011-12-21 | 北京联合大学 | Screen window anti-theft alarm system |
CN202084939U (en) * | 2011-05-24 | 2011-12-21 | 山东蓝天电能科技有限公司 | Intelligent comprehensive electric power compensation device |
CN203690935U (en) * | 2013-12-27 | 2014-07-02 | 天津瑞灵石油设备股份有限公司 | Novel TSC reactive compensation controller |
-
2017
- 2017-05-25 CN CN201710376179.4A patent/CN107222194A/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6886089B2 (en) * | 2002-11-15 | 2005-04-26 | Silicon Labs Cp, Inc. | Method and apparatus for accessing paged memory with indirect addressing |
CN101769701A (en) * | 2008-12-31 | 2010-07-07 | 吉林市北华航天科技有限公司 | Multifunctional remote electronic ignition system |
CN202084939U (en) * | 2011-05-24 | 2011-12-21 | 山东蓝天电能科技有限公司 | Intelligent comprehensive electric power compensation device |
CN102289905A (en) * | 2011-07-26 | 2011-12-21 | 北京联合大学 | Screen window anti-theft alarm system |
CN203690935U (en) * | 2013-12-27 | 2014-07-02 | 天津瑞灵石油设备股份有限公司 | Novel TSC reactive compensation controller |
Non-Patent Citations (2)
Title |
---|
温才等: "晶格结构三维模型"LED 光立方"的设计与制作", 《大学物理实验》 * |
王思宇: "组合式无功补偿控制策略研究", 《中国优秀硕士学位论文全文数据库 工程科技Ⅱ辑》 * |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN204832440U (en) | IGBT connection in series -parallel test system | |
CN102288899B (en) | Precise constant-current constant-voltage applying test circuit | |
CN105429441B (en) | IGBT closed loop initiative driving circuit and its driving method | |
CN104639169B (en) | A kind of two steps conversion successive approximation modulus converting circuit structure | |
CN104967292B (en) | A kind of active pressure equalizing control method of IGBT series valves section | |
CN205123689U (en) | Current mode linear power amplifier | |
CN106253842A (en) | Photovoltaic cell connection in series-parallel automatic switch-over circuit and method | |
CN107222194A (en) | A kind of SVG and TSC mixing reactive-load compensation level controllers and its control method | |
CN106300964A (en) | Independent charge and discharge sequential single-inductance double-output switch converters method for controlling frequency conversion and device thereof | |
CN102158114B (en) | Method and device for measuring and controlling a four-quadrant cascaded high voltage transducer power unit | |
CN102707707B (en) | Test system and test method of microwave control device | |
CN206178101U (en) | A adjustable surge load test device for electromagnetic relay | |
CN108134527A (en) | A kind of Modularized multi-level converter sub-module method for equalizing voltage for optimizing switching frequency | |
CN104714443A (en) | Polycrystalline silicon reduction power regulation power source and electrical control system thereof | |
CN204270190U (en) | A kind of control circuit of rudder system instruction current | |
CN107633798A (en) | Electric potential transfer circuit and display panel | |
CN206283408U (en) | A kind of isolated form high-precision current Balance route component | |
CN206619123U (en) | A kind of control system of mosaic display screen | |
CN204442212U (en) | There is the motor drive of motor stall setting | |
CN105281566A (en) | Three-level direct-current chopper circuit topology for space | |
CN107505975B (en) | MPPT (maximum power point tracking) analog control chip for solar power generation | |
CN104007333A (en) | High-voltage frequency converter power unit monitoring apparatus | |
CN212932853U (en) | Double-pulse test system based on ARM processor | |
CN208459488U (en) | A kind of feeder automation tester | |
CN109217873A (en) | Common-mode voltage generation device and successive approximation register type analog-to-digital converter |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170929 |
|
RJ01 | Rejection of invention patent application after publication |