CN107222188A - A kind of clock circuit, chip and electronic equipment - Google Patents
A kind of clock circuit, chip and electronic equipment Download PDFInfo
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- CN107222188A CN107222188A CN201710393375.2A CN201710393375A CN107222188A CN 107222188 A CN107222188 A CN 107222188A CN 201710393375 A CN201710393375 A CN 201710393375A CN 107222188 A CN107222188 A CN 107222188A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
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- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention relates to technical field of integrated circuits, more particularly to a kind of clock circuit, chip and electronic equipment.The clock circuit includes：First capacitor cell, within first 1/2 clock cycle, receives external power source and is charged；Second capacitor cell, within second 1/2 clock cycle of clock cycle, receives external power source and is charged；First RC circuits, within second 1/2 clock cycle of clock cycle, the first capacitor cell discharges the first RC circuits, so that the first RC circuits export the first charging voltage in first node；2nd RC circuits, within first 1/2 clock cycle, the second capacitor cell discharges the 2nd RC circuits, so that the 2nd RC circuits export the second charging voltage in first node；Comparison circuit, the first charging voltage or the second charging voltage are compared with reference voltage, export clock energizing signal；Clocked processing circuits, for according to clock energizing signal, exporting clock signal.
Description
Technical field
The present invention relates to technical field of integrated circuits, more particularly to a kind of clock circuit, chip and electronic equipment.
Background technology
Clock circuit has as the important module in microprocessor chip, its performance quality to microprocessor chip
Significance.
Conventional clock circuit uses RC clock circuits, and RC clock circuits are more classical because of its structure, in integrated circuits by
Extensive use.
Inventor has found that conventional clock circuit at least has problems with during the present invention is realized：Conventional clock
Circuit is limited by internal resistance, capacitance accuracy, power supply and temperature, causes conventional clock circuit can not be operated in the work of Width funtion
In the range of work.
The content of the invention
One purpose of the embodiment of the present invention aims to provide a kind of clock circuit, chip and electronic equipment, which solves biography
System clock circuit can not be operated in the technical problem in the working range of Width funtion.
In order to solve the above technical problems, the embodiment of the present invention provides following technical scheme：
In a first aspect, the embodiment of the present invention discloses a kind of clock circuit, the clock circuit includes：First electric capacity list
Member, is charged within 1/2 clock cycle, receiving external power source；Second capacitor cell, in the clock cycle
In another 1/2 clock cycle, receive the external power source and charged；First RC circuits, another the 1/2 of the clock cycle
In clock cycle, first capacitor cell discharges the first RC circuits, so that the first RC circuits are first
Node exports the first charging voltage；2nd RC circuits, described within 1/2 clock cycle, second capacitor cell is to described
2nd RC circuits are discharged, so that the 2nd RC circuits export the second charging voltage in the first node；Comparison circuit,
It is connected to the first node, and the comparison circuit is used for first charging voltage or second charging voltage and base
Quasi- voltage ratio is compared with output clock energizing signal；Clocked processing circuits, it is connected with the output end of the comparison circuit, when described
Clock process circuit is used to, according to the clock energizing signal, export clock signal.
Optionally, the first RC circuits share same resistance with the 2nd RC circuits.
Optionally, when first capacitor cell discharges the first RC circuits, the 2nd RC circuits of switching are extremely
Discharge condition.
Optionally, when second capacitor cell discharges the 2nd RC circuits, the first RC circuits of switching are extremely
Discharge condition.
Optionally, first charging voltage is identical with second charging voltage.
Optionally, the clock circuit includes five first switches and five second switches, each first switch and second
Switch all includes input, output end and control end；First capacitor cell includes the first electric capacity, first first switch
Input is used to be connected with the external power source, and the output end of first first switch is connected with one end of first electric capacity,
The other end ground connection of first electric capacity, the control end of first first switch is used to receive the first control signal.
Optionally, second capacitor cell includes the second electric capacity；The input of first second switch be used for it is described
External power source is connected, and the output end of first second switch is connected with one end of second electric capacity, second electric capacity it is another
One end is grounded, and the control end of second first switch is used to receive the second control signal.
Optionally, the first RC circuits include first resistor and the 3rd electric capacity；The input of second first switch with
One end connection of second electric capacity, the output end of second first switch is connected to the 3rd node, second first switch
Control end is used to receive first control signal；One end of the input of second second switch and first electric capacity connects
Connect, the output end of second second switch is connected to the 3rd node, and the control end of second second switch is used to receive institute
State the second control signal；One end of the first resistor is connected to the 3rd node, the other end connection of the first resistor
To Section Point；The input of 3rd second switch is connected to the Section Point, and the output end of the 3rd second switch connects
One end of the 3rd electric capacity is connected to, the other end of the 3rd electric capacity, the control end of the 3rd second switch is used to receive institute
State the second control signal；3rd first switch is in parallel with the 3rd electric capacity；The input and the 3rd of 4th second switch
The output end connection of individual second switch, the output end of the 4th second switch is connected to the first node, and the 4th second is opened
The control end of pass is used to receive second control signal.
Optionally, the 2nd RC circuits include the 4th electric capacity, and share first electricity with the first RC circuits
Resistance；The input of 4th first switch is connected to the Section Point, and the output end of the 4th first switch is respectively with the 5th
The input of individual first switch is connected with one end of the 4th electric capacity, and the output end of the 5th first switch is connected to described
The control end of one node, the control end of the 4th first switch and the 5th first switch is all used to receive the first control letter
Number；5th second switch is in parallel with the 4th electric capacity.
Optionally, the comparison circuit includes transport and placing device, second resistance and 3rd resistor, the homophase input of the transport and placing device
End is connected to the first node, the inverting input of the transport and placing device respectively with one end of the second resistance and the described 3rd
One end connection of resistance, the other end ground connection of the second resistance, the another of the 3rd resistor is connected to the external power source.
Optionally, the clocked processing circuits include d type flip flop, the first phase inverter and the second phase inverter, the d type flip flop
CK ends be connected with the output end of the transport and placing device, the D ends of the d type flip flop are connected to non-Q ends, the Q ends of the d type flip flop with
The input connection of first phase inverter, the output end of first phase inverter is connected to the input of second phase inverter
End；The output end of first phase inverter is used to export first control signal, and the output end of second phase inverter is used for
Export second control signal.
In second aspect, the embodiment of the present invention provides a kind of chip, and the chip includes the clock circuit of any of the above-described.
In the third aspect, the embodiment of the present invention provides a kind of electronic equipment, and the electronic equipment includes any of the above-described
Clock circuit.
In each embodiment of the invention, the first capacitor cell receives external power source within 1/2 clock cycle and charged,
2nd RC circuits are within 1/2 clock cycle, and the second capacitor cell discharges the 2nd RC circuits, so that the 2nd RC circuits are
One node exports the second charging voltage.Further, the second capacitor cell is received within another 1/2 clock cycle of clock cycle
External power source is charged, and the first RC circuits are within another 1/2 clock cycle of clock cycle, and the first capacitor cell is to the first RC
Circuit is discharged, so that the first RC circuits export the first charging voltage in first node.Comparison circuit is by the first charging voltage
Or second charging voltage compared with reference voltage, export clock energizing signal, clocked processing circuits are defeated according to clock energizing signal
Go out clock signal.Therefore, the clock frequency of the clock circuit is only relevant with electric capacity, resistance, and therefore, the clock circuit can adapt to
Wide-voltage range.
Brief description of the drawings
One or more embodiments are illustrative by the picture in corresponding accompanying drawing, these exemplary theorys
The element with same reference numbers label is expressed as similar element in the bright restriction not constituted to embodiment, accompanying drawing, removes
Composition is not limited the non-figure having in special statement, accompanying drawing.
Fig. 1 is that the embodiment of the present invention provides a kind of theory diagram of clock circuit；
Fig. 1 a are that another embodiment of the present invention provides a kind of theory diagram of clock circuit；
Fig. 2 is that the embodiment of the present invention provides a kind of timing diagram of clock circuit；
Fig. 3 is that another embodiment of the present invention provides a kind of structural representation of clock circuit；
Fig. 4 a are that another embodiment of the present invention provides one kind within first 1/2 clock cycle, the charging of the first electric capacity, the 3rd
The schematic diagram of electric capacity electric discharge；
Fig. 4 b are that the embodiment of the present invention provides one kind within first 1/2 clock cycle, and the second electric capacity fills to the 4th electric capacity
The schematic diagram of electricity；
Fig. 5 a are that another embodiment of the present invention provides one kind within second 1/2 clock cycle, the charging of the second electric capacity, the 4th
The schematic diagram of electric capacity electric discharge；
Fig. 5 b are that the embodiment of the present invention provides one kind within second 1/2 clock cycle, and the first electric capacity fills to the 3rd electric capacity
The schematic diagram of electricity；
Fig. 6 is the timing diagram that another embodiment of the present invention provides another clock circuit.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that specific embodiment described herein is only to explain the present invention, not
For limiting the present invention.
Referring to Fig. 1, Fig. 1, which is the embodiment of the present invention, provides a kind of structural representation of clock circuit.As shown in figure 1, should
Clock circuit 100 is used for all kinds of integrated chips, and it can export the clock signal with a clock cycle, for example, the clock
It with dutycycle 50% is that high level, dutycycle 50% are low level square-wave signal that signal, which is,.Therefore, a clock signal by
Level composition corresponding to two 1/2 clock cycle.Chip is under the regulation and control of clock signal, without any confusion according to writing logic
Normal work.The chip can be general processor, digital signal processor (DSP), application specific integrated circuit (ASI C), scene
Programmable gate array (FPGA), single-chip microcomputer, ARM (Acorn RISC Machine) or other PLDs, discrete gate
Or any combinations of transistor logic, discrete nextport hardware component NextPort or these parts.Further, the chip can also be any tradition
Processor, controller, microcontroller or state machine.Processor can also be implemented as the combination of computing device, for example, DSP and
Combination, multi-microprocessor, one or more microprocessors combination DSP core or any other this configuration of microprocessor.
Referring again to Fig. 1, the clock circuit 100 includes：First capacitor cell 11, the second capacitor cell 12, the first RC electricity
Road 13, the 2nd RC circuits 14, comparison circuit 15 and clocked processing circuits 16, the input and external power source of the first capacitor cell 11
17 connections, the output end of the first capacitor cell 11 is connected with the input of the first RC circuits 13, the input of the second capacitor cell 12
End is connected with external power source 17, and the output end of the second capacitor cell 12 is connected with the input of the 2nd RC circuits 14, the first RC electricity
The output end on road 13 and the output end of the 2nd RC circuits 14 are all connected to first node 101, the input connection of comparison circuit 15
To first node 101, clocked processing circuits 16 are connected with the output end of comparison circuit 15.
Also referring to Fig. 1 and Fig. 2, within first 1/2 clock cycle, the first capacitor cell 11 receives external power source 17
Charged.Also, the 2nd RC circuits 14 are within 1/2 clock cycle, the second 12 pair the 2nd of capacitor cell RC circuits 14 are carried out
Electric discharge, so that the 2nd RC circuits 14 export the second charging voltage Vramp2 in first node 101.
Within second 1/2 clock cycle of the clock cycle, the second capacitor cell 12 receives external power source 17 and filled
Electricity.Also, the first RC circuits 13 are within second 1/2 clock cycle of the clock cycle, the first 11 pair the first of capacitor cell RC
Circuit 13 is discharged, so that the first RC circuits 13 export the first charging voltage Vramp1 in first node 101.
In certain embodiments, external control signal can control filling for the first capacitor cell 11 or the second capacitor cell 12
Electric time or discharge time, for example：First capacitor cell 11 is included by switch and electric capacity, and the electric capacity is connected with switch, outside control
Signal processed is by controlling switch to control the charge and discharge of electric capacity.Wherein, the external control signal can be selected at one
Sent in 1/2 clock cycle in clock cycle.
Because the first capacitor cell 11 charges electricity within first 1/2 clock cycle, then, the first of the clock cycle
When in individual 1/2 clock cycle, the first capacitor cell 11 can discharge the first RC circuits 13.Wherein, in the first electric capacity list
When first 11 pair of the first RC circuit 13 discharges, the 2nd RC circuits 14 can be switched to discharge condition, so that the 2nd RC circuits
14 both end voltage is reduced to zero potential, so that all in second 1/2 clock of same clock cycle for the 2nd RC circuits 14
Charging is carried out in phase to prepare.The charging voltage curve map of first RC circuits 13 is as shown in Fig. 2 the first charging of the first RC circuits 13
Resistance and electric capacity that voltage Vramp1 is depended in the first RC circuits 13.
Further, because the second capacitor cell 12 charges electricity within second 1/2 clock cycle, then, in the clock
When in second 1/2 clock cycle in cycle, the second capacitor cell 12 can discharge the 2nd RC circuits 14.Wherein, exist
When second 12 pair the 2nd of capacitor cell RC circuits 14 discharge, the first RC circuits 13 can be switched to discharge condition, so that
The both end voltage of first RC circuits 13 is reduced to zero potential, so as to be the first RC circuits 13 at first of next clock cycle
Charging is carried out in 1/2 clock cycle to prepare.The charging voltage curve map of 2nd RC circuits 14 is as shown in Fig. 2 the 2nd RC circuits 14
The second charging voltage Vramp2 depend on the 2nd RC circuits 14 in resistance and electric capacity.
In certain embodiments, when the first RC circuits 13 are identical with the structure of the 2nd RC circuits 14, the first charging voltage
Vramp1 is identical with the second charging voltage Vramp2.Further, when being located at first 1/2 due to the first charging voltage Vramp1
In the clock cycle, the second charging voltage Vramp2 was located in second 1/2 clock cycle, and the clock circuit is in same clock
Different 1/2 clock cycle in cycle are sequentially output the first charging voltage Vramp1 and the second charging voltage Vramp2, therefore, pass through
First charging voltage Vramp1 and the second charging voltage Vramp2 are sequentially ingressed into comparison circuit 15, just can be realized with two
The clock signal output of 1/2 clock cycle.
As it was previously stated, the power supply that the first capacitor cell 11 can directly receive external power source 17 with the second capacitor cell 12 is entered
Row charging, the size without accurate control charging current.Treat the first capacitor cell 11 and the charging end of second capacitor cell 12
Afterwards, it just can be discharged by corresponding RC circuits, and process simplification conventional art needs accurate monitoring charging currents
Process.
First RC circuits 13 and the 2nd RC circuits 14 can be First-order Rc Circuit, can also be other High Order RC circuits.This
Art personnel are understood that：The content instructed and guided according to embodiments of the present invention, it all can be to the first RC circuits 13 and
Two RC circuits 14 make other alternatives, it will be appreciated that the alternative done should fall into protection scope of the present invention it
It is interior.
Comparison circuit 15 is compared the first charging voltage Vramp1 or the second charging voltage Vramp2 with reference voltage V ref,
Export clock energizing signal.First charging voltage Vramp1 or the second charging voltage Vramp2 are within corresponding 1/2 clock cycle
Time constant curve is followed persistently to rise.When the first charging voltage Vramp1 or the second charging voltage Vramp2 is less than benchmark
During voltage Vref, the clock energizing signal is the low level signal of marginal belt burr.As the first charging voltage Vramp1 or second
When charging voltage Vramp2 is more than reference voltage V ref, the clock energizing signal is the high level signal of marginal belt burr.
In certain embodiments, the first charging voltage Vramp1 is identical with the second charging voltage Vramp2, therefore, relatively more electric
Road 15 can select same reference voltage V ref and the first charging voltage Vramp1 or the second charging voltage Vramp2 to be compared,
With the clock signal of the consistent low and high level of output duty cycle.
In order to which the burrs on edges of the clock energizing signal of output is handled into clean, and the clock signal of outputting standard, when
Clock energizing signal is further processed by clock process circuit, the clock signal CK of final output standard.
In summary, clock signal CK clock frequency is only relevant with electric capacity, resistance, and therefore, the clock circuit can
Adapt to wide-voltage range.
In certain embodiments, in order to realize the output of accurately clock signal, can by the first capacitor cell 11 or
The high-precision type of capacitance selection in second capacitor cell 12.
In certain embodiments, as shown in Figure 1a, the first RC circuits 13 and the 2nd RC circuits 14 share same resistance K1, because
This, the electric current that the first 11 pair the first of capacitor cell RC circuits 13 are discharged flows through resistance K1, similarly, the second capacitor cell 12
Resistance K1 is flowed through to the electric current that the 2nd RC circuits 14 are discharged, therefore, by sharing resistance, it can reduce integrated circuit
Design area, it is cost-effective.
In certain embodiments, clock circuit 100 includes five first switches and five second switches, each first switch
All include input, output end and control end with second switch.
As shown in figure 3, the first capacitor cell 11 includes the first electric capacity C1, first first switch CKB1 input with it is outer
Portion's power supply VCC connections, first first switch CKB1 output end is connected with the first electric capacity C1 one end, and the first electric capacity C1's is another
One end is grounded, and first first switch CKB1 control end receives the first control signal CKB.
Second capacitor cell 12 includes the second electric capacity C2.First second switch CK1 input connects with external power source VCC
Connect, first second switch CK1 output end is connected with the second electric capacity C2 one end, the second electric capacity C2 other end ground connection, the
One second switch CK1 control end receives the second control signal CK.
First RC circuits 13 include first resistor R1 and the 3rd electric capacity C3.Second first switch CKB2 input and
Two electric capacity C2 one end connection, second first switch CKB2 output end is connected to the 3rd node 103, second first switch
CKB2 control end is used to receive first control signal CKB.
Second second switch CK2 input is connected with the first electric capacity C1 one end, and second second switch CK2's is defeated
Go out end and be connected to the 3rd node 103, second second switch CK2 control end receives second control signal CK.
First resistor R1 one end is connected to the 3rd node 103, and the first resistor R1 other end is connected to Section Point
102。
3rd second switch CK3 input is connected to Section Point 102, the 3rd second switch CK3 output end
Be connected to the 3rd electric capacity C3 one end, the 3rd electric capacity C3 other end, the 3rd second switch CK3 control end receive this second
Control signal CK.
3rd first switch CKB3 is in parallel with the 3rd electric capacity C3.
4th second switch CK4 input is connected with the 3rd second switch CK3 output end, and the 4th second is opened
The output end for closing CK4 is connected to first node 101, and the 4th second switch CK4 control end receives the second control signal CK.
2nd RC circuits 14 include the 4th electric capacity C4, and share first resistor R1 with the first RC circuits 13.4th
One switch CKB4 input is connected to Section Point 102, the 4th first switch CKB4 output end respectively with the 5th the
One switch CKB5 input is connected with the 4th electric capacity C4 one end, and the 5th first switch CKB5 output end is connected to first
Node 101, the 4th first switch CKB4 control end and the 5th first switch CKB5 control end are all used to receive first
Control signal CKB.
5th second switch CK5 is in parallel with the 4th electric capacity C4.
Comparison circuit 15 includes transport and placing device COMP, second resistance R2 and 3rd resistor R3, transport and placing device COMP homophase input
End is connected to first node 101, transport and placing device COMP inverting input one end respectively with second resistance R2 and 3rd resistor R3
One end connection, second resistance R2 other end ground connection, the another of 3rd resistor R3 be connected to external power source VCC.
Clocked processing circuits 100 include d type flip flop TD, the first phase inverter OP1 and the second phase inverter OP2, d type flip flop TD's
CK ends are connected with transport and placing device COMP output end, and d type flip flop TD D ends are connected to non-Q ends, d type flip flop TD Q ends and first anti-
Phase device OP1 input connection, the first phase inverter OP1 output end is connected to the second phase inverter OP2 input.First is anti-phase
The output end that device OP1 output end is used to export the first control signal CKB, the second phase inverter OP2 is used to export the second control letter
Number CK.
In order to elaborate clock circuit operation principle provided in an embodiment of the present invention, combination of embodiment of the present invention Fig. 3, figure
4a, Fig. 4 b, Fig. 5 a, Fig. 5 b and Fig. 6, are described below：
Within first 1/2 clock cycle, first first switch CKB1 to the 5th first switch CKB5 closure, first
Individual second switch CK1 to the 5th second switch CK5 disconnects.Then, external power source VCC charges to the first electric capacity C1, the
Three electric capacity C3 discharge, and the first electric capacity C1 top crown voltage is charged to external power source VCC, the 3rd electric capacity C3 top crown voltage is let out
Zero potential is put into, is that charging is ready next time.At the same time, the second electric capacity C2 storage electric charge passes through R1 pairs of first resistor
4th electric capacity C4 is charged (the 4th electric capacity C4 chargings), when the second charging voltage Vramp2 is more than the anti-phase of comparator COMP
During the reference voltage V ref of input end, clock upset.
Within second 1/2 clock cycle, first first switch CKB1 to the 5th first switch CKB5 disconnects, and first
Individual second switch CK1 to the 5th second switch CK5 closure.Then, external power source VCC charges to the second electric capacity C2, the
Four electric capacity C4 discharge, and the second electric capacity C2 top crown voltage is charged to external power source VCC, the 4th electric capacity C4 top crown voltage is let out
Zero potential is put into, is that charging is ready next time.At the same time, the first electric capacity C1 storage electric charge passes through R1 pairs of first resistor
3rd electric capacity C3 is charged (the 3rd electric capacity C3 chargings), when the first charging voltage Vramp1 is more than the anti-phase of comparator COMP
During the reference voltage V ref of input end, clock upset.
To sum up, the clock circuit constantly repeats to be alternately performed that " within first 1/2 clock cycle, the second electric capacity C2 is to
Four electric capacity C4 charge, the first electric capacity C1 chargings, the 3rd electric capacity C3 electric discharges " with " within second 1/2 clock cycle, the first electric capacity
C1 charges to the 3rd electric capacity C3, the second electric capacity C2 chargings, the 4th electric capacity C4 electric discharges ", include two 1/2 clocks so as to export and have
The periodic signal of the sawtooth waveforms in cycle.The periodic signal of the sawtooth waveforms passes through the processing of comparison circuit 15 and clocked processing circuits 16
Afterwards, continuous clock signal can just be exported.
As shown in figure 3, the frequency of the clock signal is：
Obviously, in second resistance R2 and 3rd resistor R3, on the premise of the first electric capacity C1 to the 4th electric capacity C4 is determined, this when
The clock frequency that clock circuit 100 is exported is related as electric capacity, also, in the unit interval, the electric charge that the clock circuit 100 is consumed
Size is：
Therefore, the clock circuit 100 can realize low-power consumption effect.
As the another aspect of the embodiment of the present invention, the embodiment of the present invention provides a kind of chip, and the chip is included such as Fig. 1 extremely
Clock circuit shown in Fig. 6.Therefore, the clock frequency of the clock circuit of the chip is only relevant with electric capacity, resistance, therefore, the core
The clock circuit of piece can adapt to wide-voltage range.
As the another aspect of the embodiment of the present invention, the embodiment of the present invention provides a kind of electronic equipment, the electronic equipment bag
Include clock circuit as shown in Figures 1 to 6.Therefore, the clock frequency of the clock circuit of the electronic equipment only has with electric capacity, resistance
Close, therefore, the clock circuit of the electronic equipment can adapt to wide-voltage range.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；At this
Under the thinking of invention, it can also be combined between the technical characteristic in above example or non-be the same as Example, step can be with
Realized with random order, and there are many other changes of the different aspect of the present invention as described above, for simplicity, they do not have
Have and provided in details；Although the present invention is described in detail with reference to the foregoing embodiments, the ordinary skill people of this area
Member should be understood：It can still modify to the technical scheme described in foregoing embodiments, or to which part skill
Art feature carries out equivalent substitution；And these modifications or replacement, the essence of appropriate technical solution is departed from each reality of the application
Apply the scope of a technical scheme.
Claims (13)
1. a kind of clock circuit, it is characterised in that including：
First capacitor cell, is charged within first 1/2 clock cycle, receiving external power source；
Second capacitor cell, is carried out within second 1/2 clock cycle of the clock cycle, receiving the external power source
Charging；
First RC circuits, within second 1/2 clock cycle of the clock cycle, first capacitor cell is to described first
RC circuits are discharged, so that the first RC circuits export the first charging voltage in first node；
2nd RC circuits, within first 1/2 clock cycle, second capacitor cell is carried out to the 2nd RC circuits
Electric discharge, so that the 2nd RC circuits export the second charging voltage in the first node；
Comparison circuit, the comparison circuit is used for first charging voltage or second charging voltage and reference voltage ratio
Compared with output clock energizing signal；
Clocked processing circuits, the clocked processing circuits are used to, according to the clock energizing signal, export clock signal.
2. clock circuit according to claim 1, it is characterised in that the first RC circuits are total to the 2nd RC circuits
Use same resistance.
3. clock circuit according to claim 1, it is characterised in that in first capacitor cell to the first RC electricity
When road is discharged, the 2nd RC circuits of switching to discharge condition.
4. clock circuit according to claim 1, it is characterised in that in second capacitor cell to the 2nd RC electricity
When road is discharged, the first RC circuits of switching to discharge condition.
5. clock circuit according to claim 1, it is characterised in that first charging voltage and the described second charging electricity
Pressure is identical.
6. the clock circuit according to any one of claim 1 to 5, it is characterised in that
The clock circuit includes five first switches and five second switches, and each first switch all includes defeated with second switch
Enter end, output end and control end；
First capacitor cell includes the first electric capacity, and the input of first first switch is used to connect with the external power source
Connect, the output end of first first switch is connected with one end of first electric capacity, the other end ground connection of first electric capacity, the
The control end of one first switch is used to receive the first control signal.
7. clock circuit according to claim 6, it is characterised in that
Second capacitor cell includes the second electric capacity；
The input of first second switch be used for be connected with the external power source, the output end of first second switch with it is described
One end connection of second electric capacity, the other end ground connection of second electric capacity, the control end of first second switch is used to receiving the
Two control signals.
8. clock circuit according to claim 7, it is characterised in that
The first RC circuits include first resistor and the 3rd electric capacity；
The input of second first switch is connected with one end of second electric capacity, the output end connection of second first switch
To the 3rd node, the control end of second first switch is used to receive first control signal；
The input of second second switch is connected with one end of first electric capacity, the output end connection of second second switch
To the 3rd node, the control end of second second switch is used to receive second control signal；
One end of the first resistor is connected to the 3rd node, and the other end of the first resistor is connected to Section Point；
The input of 3rd second switch is connected to the Section Point, and the output end of the 3rd second switch is connected to described
One end of 3rd electric capacity, the other end of the 3rd electric capacity, the control end of the 3rd second switch is used to receive second control
Signal processed；
3rd first switch is in parallel with the 3rd electric capacity；
The input of 4th second switch is connected with the output end of the 3rd second switch, the output end of the 4th second switch
The first node is connected to, the control end of the 4th second switch is used to receive second control signal.
9. clock circuit according to claim 8, it is characterised in that
The 2nd RC circuits include the 4th electric capacity, and share the first resistor with the first RC circuits；
The input of 4th first switch is connected to the Section Point, and the output end of the 4th first switch is respectively with the 5th
The input of individual first switch is connected with one end of the 4th electric capacity, and the output end of the 5th first switch is connected to described
The control end of one node, the control end of the 4th first switch and the 5th first switch is all used to receive the first control letter
Number；
5th second switch is in parallel with the 4th electric capacity.
10. clock circuit according to claim 9, it is characterised in that the comparison circuit includes transport and placing device, second resistance
And 3rd resistor, the in-phase input end of the transport and placing device is connected to the first node, the inverting input point of the transport and placing device
It is not connected with one end of the second resistance and one end of the 3rd resistor, the other end ground connection of the second resistance is described
The another of 3rd resistor is connected to the external power source.
11. clock circuit according to claim 10, it is characterised in that
The clocked processing circuits include d type flip flop, the first phase inverter and the second phase inverter, the CK ends of the d type flip flop and institute
State the output end connection of transport and placing device, the D ends of the d type flip flop are connected to non-Q ends, Q ends of the d type flip flop and described first anti-
The input connection of phase device, the output end of first phase inverter is connected to the input of second phase inverter；
The output end of first phase inverter is used to export first control signal, and the output end of second phase inverter is used for
Export second control signal.
12. a kind of chip, it is characterised in that including the clock circuit as described in any one of claim 1 to 11.
13. a kind of electronic equipment, it is characterised in that including the clock circuit as described in any one of claim 1 to 11.
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| CN107222188B CN107222188B (en) | 2020-06-19 |
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| CN101964647A (en) * | 2010-09-14 | 2011-02-02 | 日银Imp微电子有限公司 | Pulse width signal duty ratio detection circuit |
| CN102111130A (en) * | 2009-12-28 | 2011-06-29 | 无锡中星微电子有限公司 | Duty cycle correction circuit |
| CN103312298A (en) * | 2013-07-05 | 2013-09-18 | 东南大学 | Relaxation oscillator for increasing frequency-control current linearity |
| CN104052441A (en) * | 2014-06-10 | 2014-09-17 | 中国科学院高能物理研究所 | Pre-charge load-balancing switch capacitor circuit and switch capacitor comparator with same |
| CN104579254A (en) * | 2014-12-03 | 2015-04-29 | 北京兆易创新科技股份有限公司 | Relaxation oscillator |
| CN106501585A (en) * | 2016-12-09 | 2017-03-15 | 合肥中感微电子有限公司 | One kind overcharges power detection circuit and battery protection system |
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| CN102111130A (en) * | 2009-12-28 | 2011-06-29 | 无锡中星微电子有限公司 | Duty cycle correction circuit |
| CN101882924A (en) * | 2010-06-08 | 2010-11-10 | 北京思比科微电子技术股份有限公司 | Clock signal detection device |
| CN101964647A (en) * | 2010-09-14 | 2011-02-02 | 日银Imp微电子有限公司 | Pulse width signal duty ratio detection circuit |
| CN103312298A (en) * | 2013-07-05 | 2013-09-18 | 东南大学 | Relaxation oscillator for increasing frequency-control current linearity |
| CN104052441A (en) * | 2014-06-10 | 2014-09-17 | 中国科学院高能物理研究所 | Pre-charge load-balancing switch capacitor circuit and switch capacitor comparator with same |
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| CN106501585A (en) * | 2016-12-09 | 2017-03-15 | 合肥中感微电子有限公司 | One kind overcharges power detection circuit and battery protection system |
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| CN107222188B (en) | 2020-06-19 |
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