CN107220024B - Data processing method, device and system based on FPGA - Google Patents
Data processing method, device and system based on FPGA Download PDFInfo
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Abstract
The invention discloses a data processing method, a device and a system based on FPGA, which comprises the steps of receiving a plurality of inputs, and calculating a selection path result of each input in parallel by adopting a carry-ahead calculation method; and judging and analyzing each path selection result to obtain a calculation result. Therefore, the embodiment of the invention adopts the carry-ahead calculation method to simultaneously carry out parallel calculation on a plurality of inputs, calculates the path selection result corresponding to each input, and obtains the calculation result after judging and analyzing each path selection result so as to complete the calculation of the matching effective position. The invention greatly shortens the time delay in the calculation process and improves the data processing speed and the system performance in the use process.
Description
Technical Field
The embodiment of the invention relates to the technical field of data processing, in particular to a data processing method based on an FPGA. The embodiment of the invention also relates to a data processing device and a system based on the FPGA.
Background
Currently, LZ77 compression is a commonly used compression method, in order to improve the efficiency of data compression, Open Computing Language (Open Computing Language) of OpenCL of FPGA (Field programmable Gate Array) is used to implement LZ77 compression, and in the process of implementing LZ77 compression by OpenCL based on FPGA, the computation of matching effective positions is a key process, and the process directly affects the compression performance of the whole system. In the prior art, a serial calculation mode (as shown in fig. 1, fig. 1 is a serial calculation function model provided in the prior art) is adopted when performing the matching effective position calculation on a plurality of inputs, two or more inputs of each stage are calculated and then the calculation result is used for the operation of the next stage, and after the execution of the first stage is finished, the calculation result is input to the next stage and the calculation of the next stage is performed until the serial calculation is finished. Because the final result of matching the effective position can be obtained only after all stages of operation are completed, the clock frequency is reduced in the FPGA implementation process, the data processing speed is reduced, and the performance of the whole system is affected.
In summary, it can be seen how to provide a data processing method, device and system based on FPGA for solving the above technical problems, which is a problem to be solved at present.
Disclosure of Invention
The embodiment of the invention aims to provide a data processing method based on an FPGA (field programmable gate array), which greatly shortens the time delay in the calculation process in the use process and improves the data processing speed and the system performance.
In order to solve the above technical problem, an embodiment of the present invention provides a data processing method based on an FPGA, including:
receiving a plurality of inputs, and calculating a selection path result of each input in parallel by adopting a carry-ahead calculation method;
and judging and analyzing each path selection result to obtain a calculation result.
Optionally, the process of calculating each input selection path result by using the carry-look-ahead calculation method specifically includes:
performing Boolean function operation on each input and each input behind the input to obtain a plurality of corresponding operation results;
and obtaining a path selection result corresponding to each input according to each operation result.
Optionally, the process of determining and analyzing each result of selecting a path and obtaining a calculation result specifically includes:
obtaining a corresponding Boolean sequence according to each selection path result;
and taking the Boolean sequence as an output judgment condition, and obtaining a calculation result according to the Boolean sequence.
Optionally, the boolean function operation is a comparison operation;
the process of performing Boolean function operation on each input and each input positioned behind the input to obtain a plurality of corresponding operation results is as follows:
and comparing each input with each input behind the input to obtain a plurality of corresponding operation results.
In order to solve the above technical problem, an embodiment of the present invention provides a data processing apparatus based on an FPGA, including:
the calculation module is used for receiving a plurality of inputs and calculating a selection path result of each input in parallel by adopting a carry-look-ahead calculation method;
and the judgment analysis module is used for judging and analyzing each path selection result and obtaining a calculation result.
Optionally, the calculation module includes:
the Boolean function calculation unit is used for performing Boolean function operation on each input average and each input positioned behind the input average to obtain a plurality of corresponding operation results;
and the selection path calculation unit is used for obtaining a selection path result corresponding to each input according to each operation result.
Optionally, the judgment analysis module includes:
the Boolean sequence calculating unit is used for obtaining a corresponding Boolean sequence according to each selection path result;
and the analysis and judgment unit is used for taking the Boolean sequence as an output judgment condition and obtaining a calculation result according to the Boolean sequence.
Optionally, the boolean function calculation unit includes a comparison operation unit, configured to perform a comparison operation on each input with each input located behind the input, respectively, to obtain a plurality of corresponding operation results.
In order to solve the above technical problem, an embodiment of the present invention provides an FPGA-based data processing system, which includes the FPGA-based data processing apparatus described above.
The embodiment of the invention provides a data processing method, a device and a system based on an FPGA, comprising the following steps: receiving a plurality of inputs, and calculating a selection path result of each input in parallel by adopting a carry-ahead calculation method; and judging and analyzing each path selection result to obtain a calculation result.
Therefore, the embodiment of the invention adopts the carry-ahead calculation method to simultaneously carry out parallel calculation on a plurality of inputs, calculates the path selection result corresponding to each input, and obtains the calculation result after judging and analyzing each path selection result so as to complete the calculation of the matching effective position. The invention greatly shortens the time delay in the calculation process and improves the data processing speed and the system performance in the use process.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a serial computational function model provided in the prior art;
fig. 2 is a schematic flowchart of a data processing method based on an FPGA according to an embodiment of the present invention;
FIG. 3 is a functional model of parallel computation according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a data processing apparatus based on an FPGA according to an embodiment of the present invention.
Detailed Description
The embodiment of the invention provides a data processing method based on an FPGA (field programmable gate array), which greatly shortens the time delay in the calculation process in the use process and improves the data processing speed and the system performance.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 2, fig. 2 is a schematic flowchart of a data processing method based on an FPGA according to an embodiment of the present invention. The method comprises the following steps:
s11: receiving a plurality of inputs, and calculating a selection path result of each input in parallel by adopting a carry-ahead calculation method;
s12: and judging and analyzing each path selection result to obtain a calculation result.
Specifically, in the embodiment of the present invention, the received multiple inputs may be simultaneously subjected to parallel computation, the multiple inputs may be processed in parallel by using a carry-look-ahead computation method, a result of selecting a path for each input may be obtained, and a final computation result may be obtained according to the result of selecting a path for each input. In practical application, the multi-stage selector adopts an advance calculation method to calculate each input selection path result, namely, the advance calculation is carried out to complete each input selection path result, and then the final calculation result is output through the multi-stage selector. Referring to fig. 3, fig. 3 is a functional model of parallel computation according to an embodiment of the present invention, and in practical applications, a serial circuit structure in the prior art may be converted into a parallel computation circuit structure corresponding to the embodiment of the present invention, so as to implement parallel computation on multiple inputs, increase the computation speed, and improve the performance of the system to a certain extent.
The embodiment of the invention provides a data processing method, a device and a system based on an FPGA, comprising the following steps: receiving a plurality of inputs, and calculating a selection path result of each input in parallel by adopting a carry-ahead calculation method; and judging and analyzing each path selection result to obtain a calculation result.
Therefore, the embodiment of the invention adopts the carry-ahead calculation method to simultaneously carry out parallel calculation on a plurality of inputs, calculates the path selection result corresponding to each input, and obtains the calculation result after judging and analyzing each path selection result so as to complete the calculation of the matching effective position. The invention greatly shortens the time delay in the calculation process and improves the data processing speed and the system performance in the use process.
The embodiment of the invention discloses a data processing method based on an FPGA (field programmable gate array). compared with the previous embodiment, the technical scheme is further explained and optimized in the embodiment. Specifically, the method comprises the following steps:
in the previous embodiment S11, the process of calculating the selection path result for each input by using the carry look ahead calculation method may specifically include the following steps S110 and S111:
s110: performing Boolean function operation on each input and each input behind the input to obtain a plurality of corresponding operation results;
s111: and obtaining a path selection result corresponding to each input according to each operation result.
It should be noted that, in practical applications, when multiple inputs are calculated in parallel, one selector is adopted, and the function of each stage can be decomposed into two parts, where the first part is the selector and the second part is the boolean function operation that determines the switch state of the selector, and the boolean function operation can be represented by f (x, y). The n-level calculation has n +1 inputs in total, and in order to avoid the problem that when n is too large, a circuit for parallel calculation is too complex, a forward calculation method is adopted to perform parallel calculation on a plurality of inputs, a Boolean function operation is expanded, meanwhile, a circuit model can be optimized in a targeted mode, and a selection path result corresponding to each input can be calculated. For the serial calculation in the prior art, the boolean function equation corresponding to the function model in fig. 1 can be expressed as follows:
It can be understood that n +1 inputs are shared in the n-level calculation, and in the specific calculation process, the first input sum and each input located behind the first input sum are subjected to boolean function operation, and the corresponding operation results are obtained and stored. For example, the result of the Boolean function operation of the first input and the second input can be represented by f1,2The expression that the operation result obtained by the Boolean function operation of the first input and the third input can be used as f1,3It is shown that the operation result obtained by performing Boolean function operation on the first input of … and the (n + 1) th input can be represented by f1,n+1Represents; after the first input and the following inputs are calculated, respectively performing Boolean function operation on the second input and the following inputs (the third input is input to the (n + 1) th input) until the nth input and the (n + 1) th input perform Boolean function operation and obtain corresponding calculation results, wherein the calculation results can be fn,n+1And (4) showing. After all the inputs are subjected to Boolean function operation, the obtained operation results can be tabulated in a matrix formAnd showing and obtaining a state matrix of path transition, wherein the state matrix can obtain a result of selecting a path corresponding to each input. Specifically, referring to table 1, table 1 is a path transition state matrix table corresponding to n-level calculation, where fi,jThe operation result of the boolean function operation corresponding to the ith input and the jth input is shown, and f being 0 or 1 indicates that either of the two inputs at the stage is selected.
TABLE 1
| b2 | b3 | bn+1 | ||
| b1 | f1,2 | f1,3 | - | f1,n+1 |
| b2 | . | f2,3 | - | f2,n+1 |
| b3 | . | . | - | f3,n+1 |
| - | - | - | fi,j | - |
| bn | fn,n+1 |
Further, in the previous embodiment S12, the process of performing judgment analysis on each result of selecting a path and obtaining a calculation result may specifically include the following steps S120 and S121:
s120, obtaining a corresponding Boolean sequence according to each selection path result;
and S121, taking the Boolean sequence as an output judgment condition, and obtaining a calculation result according to the Boolean sequence.
Specifically, the boolean function sequence S ═ may be obtained for each input according to the selection path to which each input corresponds (S ═ S)1,s2,…sn) And determining the final output result of the multiplexer by using each Boolean function sequence as the input condition judged by the multiplexer.
The boolean sequence for n-level computations can be expressed as S ═ (S)1,s2,…sn) Then, we can get:
Can prove the relation
And relation formula
Are equivalent, and in practical applications (i.e. when implemented in hardware),
the specific form of (3) can be adjusted to the condition of iterative expansion moderately according to the length of n actually realized, and the complexity is low.
Optionally, the boolean function operation is a comparison operation;
the process of performing Boolean function operation on each input and each input positioned behind the input to obtain a plurality of corresponding operation results is as follows:
and comparing each input with each input behind the input to obtain a plurality of corresponding operation results.
It can be understood that the comparison operation may be simpler in calculation, and when other boolean function operations may also be used, which operation is specifically used may be determined according to actual situations.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a data processing apparatus based on an FPGA according to an embodiment of the present invention. On the basis of the above-described embodiment:
the device includes:
the calculation module 1 is used for receiving a plurality of inputs and calculating a selection path result of each input in parallel by adopting a carry-ahead calculation method;
and the judgment analysis module 2 is used for judging and analyzing each path selection result and obtaining a calculation result.
Specifically, the calculating module 1 may include a boolean function calculating unit and a selection path calculating unit, where:
the Boolean function calculation unit is used for performing Boolean function operation on each input average and each input positioned behind the input average to obtain a plurality of corresponding operation results;
and the selection path calculation unit is used for obtaining a selection path result corresponding to each input according to each operation result.
Further, the judgment analysis module 2 includes a boolean sequence calculation unit and an analysis judgment unit, wherein:
the Boolean sequence calculating unit is used for obtaining a corresponding Boolean sequence according to each selection path result;
and the analysis and judgment unit is used for taking the Boolean sequence as an output judgment condition and obtaining a calculation result according to the Boolean sequence.
More specifically, in this embodiment, the boolean function calculation unit includes a comparison operation unit, configured to perform a comparison operation on each input with each input located behind the input, so as to obtain a plurality of corresponding operation results.
Therefore, the embodiment of the invention adopts the carry-ahead calculation method to simultaneously carry out parallel calculation on a plurality of inputs, calculates the path selection result corresponding to each input, and obtains the calculation result after judging and analyzing each path selection result so as to complete the calculation of the matching effective position. The invention improves the data processing speed and the system performance in the using process.
In addition, for a specific description of the data processing method in the embodiment of the present invention, please refer to the above method embodiment, which is not described herein again.
On the basis of the above embodiments, an embodiment of the present invention provides an FPGA-based data processing system, which includes the FPGA-based data processing apparatus.
It should be noted that, in the embodiment of the present invention, a carry-look-ahead calculation method is adopted to perform parallel calculation on multiple inputs at the same time, calculate the result of selecting a path corresponding to each input, and obtain a calculation result after performing judgment and analysis on each result of selecting a path, so as to complete calculation of matching an effective position. The invention improves the data processing speed and the system performance in the using process.
In addition, for a specific description of the data processing method in the embodiment of the present invention, please refer to the above method embodiment, which is not described herein again.
It should also be noted that in this specification, terms such as "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (7)
1. A data processing method based on FPGA is characterized by comprising the following steps:
receiving a plurality of inputs, and calculating a selection path result of each input in parallel by adopting a carry-ahead calculation method;
judging and analyzing each path selection result to obtain a calculation result; wherein:
the process of calculating each input selection path result by adopting the carry look ahead calculation method specifically comprises the following steps:
performing Boolean function operation on each input and each input behind the input to obtain a plurality of corresponding operation results;
obtaining a path selection result corresponding to each input according to each operation result;
the calculation result is a calculation result of the matching effective position.
2. The FPGA-based data processing method of claim 1, wherein the process of judging and analyzing each result of selecting the path and obtaining the calculation result specifically comprises:
obtaining a corresponding Boolean sequence according to each selection path result;
and taking the Boolean sequence as an output judgment condition, and obtaining a calculation result according to the Boolean sequence.
3. The FPGA-based data processing method of claim 1 or 2, wherein said boolean function operation is a comparison operation;
the process of performing Boolean function operation on each input and each input positioned behind the input to obtain a plurality of corresponding operation results is as follows:
and comparing each input with each input behind the input to obtain a plurality of corresponding operation results.
4. An FPGA-based data processing apparatus, comprising:
the calculation module is used for receiving a plurality of inputs and calculating a selection path result of each input in parallel by adopting a carry-look-ahead calculation method;
the judgment analysis module is used for judging and analyzing each path selection result and obtaining a calculation result; wherein:
the calculation module comprises:
the Boolean function calculation unit is used for performing Boolean function operation on each input average and each input positioned behind the input average to obtain a plurality of corresponding operation results;
the selection path calculation unit is used for obtaining a selection path result corresponding to each input according to each operation result;
the calculation result is a calculation result of the matching effective position.
5. The FPGA-based data processing apparatus of claim 4, wherein the decision analysis module comprises:
the Boolean sequence calculating unit is used for obtaining a corresponding Boolean sequence according to each selection path result;
and the analysis and judgment unit is used for taking the Boolean sequence as an output judgment condition and obtaining a calculation result according to the Boolean sequence.
6. The FPGA-based data processing apparatus of claim 4, wherein the Boolean function calculating unit comprises a comparison operation unit for performing a comparison operation on each input with the respective input located therebehind to obtain a plurality of corresponding operation results.
7. An FPGA-based data processing system comprising an FPGA-based data processing apparatus as claimed in any one of claims 4 to 6.
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