CN107204789B - CAN chip and electronic equipment - Google Patents

CAN chip and electronic equipment Download PDF

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Publication number
CN107204789B
CN107204789B CN201710531864.XA CN201710531864A CN107204789B CN 107204789 B CN107204789 B CN 107204789B CN 201710531864 A CN201710531864 A CN 201710531864A CN 107204789 B CN107204789 B CN 107204789B
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receiving unit
unit
pin
circuit
chip
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CN107204789A (en
Inventor
谭建明
唐杰
玉维友
贺小林
李翠娟
刘桂鹏
李忠正
陈位旭
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Gree Electric Appliances Inc of Zhuhai
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Gree Electric Appliances Inc of Zhuhai
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • H04B1/44—Transmit/receive switching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L2012/40208—Bus networks characterized by the use of a particular bus standard
    • H04L2012/40215—Controller Area Network CAN

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

The invention discloses a CAN chip and an electronic device. Wherein, the CAN chip includes: the device comprises a sending unit, a reversing unit, a receiving unit and a logic judgment circuit; the transmitting unit is connected with a write pin of the CAN chip and used for converting the logic level into a differential level of the CAN bus; the reversing unit is connected with an output pin of the sending unit and used for receiving the control signal output by the logic judgment circuit and gating and accessing a polarity pin of the receiving unit according to the control signal; the receiving unit and the output end of the reversing unit are used for converting the differential level of the CAN bus into the logic level; the logic judgment circuit is connected with the output end of the receiving unit and used for generating the control signal according to the output signal of the receiving unit and sending the control signal to the reversing unit.

Description

CAN chip and electronic equipment
Technical Field
The present invention relates to the field of Control Area Network (CAN) non-polar communication, and in particular, to a CAN chip and an electronic device.
Background
Currently, in a CAN non-polar communication process, a commutation circuit is usually built outside a CAN chip for its commutation function, and polarity switching is controlled by a micro control unit (MCU for short). However, the hardware circuit and the software protocol of the implementation scheme are complex and prone to failure, so that the reliability is not high.
In view of the above problems, no effective solution has been proposed.
Disclosure of Invention
The embodiment of the invention provides a CAN chip and electronic equipment, which at least solve the technical problems that in the related technology, the implementation scheme of a reversing function in the CAN electrodeless communication process is complex, so that faults are easy to occur and the reliability is low.
According to an aspect of an embodiment of the present invention, there is provided a CAN chip including: the device comprises a sending unit, a reversing unit, a receiving unit and a logic judgment circuit; the transmitting unit is connected with a write pin of the CAN chip and used for converting the logic level into a differential level of the CAN bus; the reversing unit is connected with an output pin of the sending unit and used for receiving the control signal output by the logic judgment circuit and gating and accessing a polarity pin of the receiving unit according to the control signal; the receiving unit is connected with the output end of the reversing unit and used for converting the differential level of the CAN bus into the logic level; the logic judgment circuit is connected with the output end of the receiving unit and used for generating the control signal according to the output signal of the receiving unit and sending the control signal to the reversing unit.
Optionally, the receiving unit includes: a first receiving unit and a second receiving unit; the CAN chip further comprises: the gating circuit is connected with the output ends of the first receiving unit and the second receiving unit and comprises an AND gate circuit.
Optionally, the CAN chip further includes: a housing; the gating circuit, the sending unit, the reversing unit, the receiving unit and the logic judging circuit are all arranged in the shell.
Optionally, an input end of the sending unit is connected to a writing pin on the housing, and an output end of the sending unit is connected to the reversing unit, and is configured to receive a signal input through the writing pin; the output end of the reversing unit is respectively connected with the first receiving unit and the second receiving unit, and is used for matching the sending unit with one of the first receiving unit and the second receiving unit, wherein the polarities of the first receiving unit and the second receiving unit are different; the input ends of the first receiving unit and the second receiving unit are connected with the output end of the reversing unit, and the output ends of the first receiving unit and the second receiving unit are respectively connected with the gating circuit and the logic judging circuit; a first end of the logic judgment circuit is connected with a polarity enabling pin, a second end of the logic judgment circuit is connected with the first receiving unit and the second receiving unit, and a third end of the logic judgment circuit is connected with the reversing unit; the input end of the gating circuit is connected with the output pins of the first receiving unit and the second receiving unit.
Optionally, the output end of the sending unit includes: CAN _ H pin and CAN _ L pin.
Optionally, the commutation unit comprises: a first switching sub-circuit and a second switching sub-circuit; the first switching sub-circuit and the second switching sub-circuit are both connected with the CAN bus, and the CAN chip pin accessed by the first switching sub-circuit and the CAN chip pin accessed by the second switching sub-circuit have opposite polarities.
Optionally, an output end of the commutation unit is connected to a CAN _ H pin and a CAN _ L pin provided on the housing.
Optionally, the CAN chip further includes: and the power supply pin and the power ground pin are arranged on the shell.
Optionally, the CAN chip further includes: and the extension pin is arranged on the shell.
Optionally, the output terminal of the gating circuit is connected to a read pin disposed on the housing.
Optionally, input pins of the first receiving unit and the second receiving unit are connected with a CAN _ H pin and a CAN _ L pin provided on the housing.
Optionally, the logic determining circuit includes: a latch circuit.
Optionally, the gating circuit comprises: and gate circuit.
According to another aspect of the embodiments of the present invention, there is also provided an electronic device, including: the CAN chip is the CAN chip.
In the embodiment of the invention, the reversing function is realized in the CAN by arranging the circuit for realizing the polarity reversing function in the CAN chip without external MCU identification, so that the software and hardware resources CAN be saved, the reliability of the non-polarity communication of the CAN is improved, and the technical problems of easy failure and low reliability caused by more complex implementation schemes of the reversing function in the non-polarity communication process of the CAN in the related technology are solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
fig. 1 is a schematic structural diagram of a CAN chip according to an embodiment of the present application;
FIG. 2a is a schematic diagram of an alternative CAN chip according to an embodiment of the present application;
FIG. 2b is a schematic diagram of an alternative CAN chip according to an embodiment of the present application;
FIG. 3 is a truth table diagram for a latch according to an embodiment of the application.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In the related technology, the reversing function of CAN nonpolar communication needs to be provided with an external reversing circuit, the circuit is complex, the cost is high, the reliability is not high, and faults are easy to occur; the reversing function of CAN nonpolar communication needs external MCU identification control, the reaction speed is slow, MCU internal resources are wasted, and the cost is high. In view of the above problems, embodiments of the present application provide corresponding solutions, which are described in detail below.
Fig. 1 is a schematic structural diagram of a CAN chip according to an embodiment of the present application. As shown in fig. 1, the CAN chip includes: a transmitting unit 101, a reversing unit 103, a receiving unit 105 and a logic judging circuit 107; wherein the content of the first and second substances,
the transmitting unit 101 is connected with a write pin of the CAN chip and used for converting the logic level into a differential level of the CAN bus;
in an alternative embodiment, a CAN processing unit (e.g., an MCU inside the chip) may be disposed between the transmitting unit 101 and the write pin of the CAN chip. At this time, the logic level of the internal MCU is converted into a differential level of the CAN bus.
A commutation unit 103, connected to an output pin of the transmitting unit 101, for receiving the control signal output by the logic determining circuit 107, and gating a polarity pin of the receiving unit 105 according to the control signal;
a receiving unit 105, connected to an output end of the commutation unit 103, for converting the differential level of the CAN bus into a logic level, where the logic level refers to a logic level of a processing unit (e.g., MCU) inside a chip;
a logic judgment circuit 107 connected to the output terminal of the receiving unit 105, for generating the control signal according to the output signal of the receiving unit 105, and sending the control signal to the commutation unit 103.
Optionally, as shown in fig. 2a, the receiving unit 105 includes: a first receiving unit 1051 and a second receiving unit 1052; the above CAN chip may further include: the gate circuit 109 is connected to the output terminals of the first receiving unit 1051 and the second receiving unit 1052.
In an alternative embodiment, the first receiving unit 1051 and the other nodes connected to the CAN bus and the second receiving unit 1052 and the CAN bus have different polarities.
In the embodiment shown in fig. 2a and 2b, pin 1 of the first receiving unit 1051 is connected to the CAN _ H pin and pin 2 is connected to the CAN _ L pin. Pin 1 of the second receiving unit 1052 is connected to the CAN _ L pin of the case, and pin 2 is connected to the CAN _ H pin of the case.
The gating circuit 109 may be implemented by a logic gate circuit, for example, an and gate circuit, but is not limited thereto.
Optionally, as shown in fig. 2a, the CAN chip further includes: a housing 10; the gate circuit 109, the transmission unit 101, the commutation unit 103, the reception unit 105, and the logic determination circuit 107 are all provided inside the housing 10.
As shown in fig. 2a and 2b, the input terminals of the first receiving unit 1051 and the second receiving unit 1052 are connected to the output terminal of the commutation unit 103, and the output terminals of the first receiving unit 1051 and the second receiving unit 1052 are connected to the gating circuit 109 and the logic determining circuit 107, respectively;
the transmitting unit 101, an input end of which is connected to a writing pin (TXD) on the housing 10, and an output end of which is connected to the commutating unit 103, for receiving a signal input through the writing pin;
the output end of the reversing unit 103 is connected to the first receiving unit 1051 and the second receiving unit 1052, respectively, for matching the transmitting unit 101 with one of the first receiving unit 1051 and the second receiving unit 1052, wherein the polarities of the first receiving unit 1051 and the second receiving unit 1052 are different;
input terminals of the first receiving unit 1051 and the second receiving unit 1052 are connected to an output terminal of the inverting unit 103, and output terminals of the first receiving unit 1051 and the second receiving unit 1052 are connected to the gate circuit 109 and the logic determining circuit 107, respectively;
a first terminal of the logic determining circuit 107 is connected to a polarity enable pin (i.e., MS pin), a second terminal thereof is connected to the first receiving unit 1051 and the second receiving unit 1052, and a third terminal thereof is connected to the commutation unit 103;
in an alternative embodiment, the MS pin is a master-slave select pin. When MS is grounded, the default definition of chip power-on is fixed polarity, and the polarity is not changeable; when the MS is pulled up, the default definition polarity of the chip power-on is variable.
An input terminal of the gate circuit 109 is connected to output pins of the first receiving unit 1051 and the second receiving unit 1052.
Optionally, the output end of the sending unit 101 includes: CAN _ H pin (CAN _ H) and CAN _ L pin (CAN _ L).
Optionally, the commutation unit 103 comprises: a first switching sub-circuit 1031 and a second switching sub-circuit 1033; the first switching sub-circuit 1031 and the second switching sub-circuit 1033 are both connected to the CAN bus, and the CAN chip pins accessed by the first switching sub-circuit 1031 and the CAN chip pins accessed by the second switching sub-circuit 1033 have opposite polarities (i.e., one is connected to the CAN _ H level and the other is connected to the CAN _ L level). The first switching sub-circuit 1031 and the second switching sub-circuit 1033 may be implemented by a single-pole double-throw switch, but are not limited thereto. Optionally, the first switching sub-circuit 1031 and the second switching sub-circuit 1033 are both connected to a CAN bus (CAN _ H pin and CAN _ L pin), but the polarities are opposite; and a CAN _ L pin of the sending unit is connected with a CAN _ L pin on the shell. When the second switching sub-circuit 1033 is selected, the polarity is reversed.
Optionally, as shown in fig. 2b, a CAN _ H pin of the receiving unit 1 is connected to a CAN _ H pin on the housing, and a CAN _ L pin is connected to a CAN _ L pin on the housing. The connection of the receiving unit 2 to the pins provided on the housing is of opposite polarity to the connection of the receiving unit 1 to the pins on the housing. When a differential signal comes in from the outside, both receiving units receive, but the converted levels are the same when the differential level of the recessive bit is received and different when the differential level of the dominant bit is received.
Optionally, an output end of the commutation unit 103 is connected to a CAN _ L pin (CAN _ H) and a CAN _ L pin (CAN _ L) provided on the housing.
Optionally, as shown in fig. 2a, the CAN chip further includes: a power supply pin (VCC) and a power ground pin (VDD) are provided on the housing 10.
Optionally, as shown in fig. 2a, the CAN chip further includes: and an extension pin (NC) provided on the housing 10. The extension pin is used for extending the functions of the CAN chip.
Alternatively, as shown in fig. 2a, the output terminal of the gating circuit 109 is connected to a read pin (RXD) provided on the housing 10.
Alternatively, the input pins of the first receiving unit 1051 and the second receiving unit 1052 are connected to a CAN _ H pin (CAN _ H) and a CAN _ L pin (CAN _ L) provided in the housing 10.
Alternatively, as shown in fig. 2a and 2b, the logic determining circuit 107 may include, but is not limited to: an SR latch.
The structure of the CAN chip is described in detail below with reference to the embodiment shown in fig. 2 b. In an alternative embodiment of the present application, as shown in fig. 2b, the chip is mainly structured as follows: a sending unit 101, a commutation unit 103; two receiving units (1051,1052), an AND gate 109, an SR latch 107;
the CAN chip is defined as an 8PIN package, wherein:
VCC is a power supply pin and is defined as a No. 1 pin;
VSS is power ground and is defined as No. 4 pin;
TXD is a signal transmission pin of the butt joint MCU and is defined as a No. 2 pin;
RXD is a signal receiving pin of the butt joint MCU and is defined as a No. 3 pin;
CAN _ H is defined as a No. 7 pin, is CAN _ H in a default state and is variable when the CAN _ H is positioned in a slave module;
CAN _ L is defined as a No. 6 pin, is CAN _ L in a default state and is variable when the slave module is in use;
MS is a polarity enable pin, the grounding is a fixed polarity, and the connection VCC is a variable polarity, and is defined as a No. 5 pin;
and the NC pin is empty, and the function is reserved and is defined as a No. 8 pin.
The implementation principle of the reversing function is as follows:
reception of no polarity:
when a signal exists on the CAN bus, if a hidden bit is received, the "receiving unit 1" (i.e. the first receiving unit 1051) and the "receiving unit 2" (i.e. the second receiving unit 1052) both output "1" after being judged, and the pin RXD through the and gate circuit 109 is still "1";
when the display character bit is received, a sending 0 is determined to exist in the receiving unit 1 and the receiving unit 2, and the sending 0 is still 0 after the sending 0 passes through the AND gate circuit and the RXD pin;
through the scheme of adding the AND gate to the double receiving units, the received signals reach non-polarity.
Sending nonpolarity:
when the receiver receives the explicit bit, the output of the receiving unit 1 and the receiving unit 2 is 0, and the output of the receiving unit 1 is 1, namely, only two states of 01 or 10 exist. And the two receiver outputs are respectively connected to the 'S and R' pins of the SR latch, so that the two states of '01' or '10' determine that Q is set to be 1 or 0, and thus the two polarities of the commutation unit are connected. A specific truth table is shown in fig. 3.
When the CAN _ H of the external node is connected with the CAN _ H of the local node and the CAN _ L of the external node is connected with the CAN _ L of the local node, when the receiver receives the display character bit, the receiving unit 1 outputs 0, the receiving unit 2 outputs 1, and the Q of the SR latch outputs 0, the reversing unit executes reversing action and matches the polarities of the sending unit and the receiving unit 1.
When the CAN _ H of the external node is connected with the CAN _ L of the local node and the CAN _ L of the external node is connected with the CAN _ H of the local node, when the receiver receives the display character bit, the receiving unit 1 outputs 1, the receiving unit 2 outputs 0, the Q of the SR latch outputs 1, the reversing unit executes action, and the sending unit is matched with the receiving unit 2 in polarity;
by adopting the scheme provided by the embodiment, the CAN communication circuit is simplified, and the reliability of the circuit is improved; an external MCU (micro control unit) is not needed for identification and control, the utilization rate of internal resources is improved, and the protocol complexity is reduced; the number of devices is reduced, and the cost is reduced.
In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims (12)

1. A controller area network, CAN, chip, comprising: the device comprises a sending unit, a reversing unit, a receiving unit, a logic judgment circuit and a gating circuit; wherein the content of the first and second substances,
the transmitting unit is connected with a writing pin of the CAN chip and used for converting the logic level into a differential level of the CAN bus;
the reversing unit is connected with an output pin of the sending unit and used for receiving the control signal output by the logic judgment circuit and gating and accessing a polarity pin of the receiving unit according to the control signal;
the receiving unit is connected to the output end of the reversing unit, and is configured to convert the differential level of the CAN bus into the logic level, and the receiving unit includes: a first receiving unit and a second receiving unit;
the logic judgment circuit is connected with the output end of the receiving unit and used for generating the control signal according to the output signal of the receiving unit and sending the control signal to the reversing unit, wherein the logic judgment circuit is also connected with a polarity enabling pin, the polarity is not changeable when the polarity enabling pin is grounded, and the polarity is changeable when the polarity enabling pin is pulled up;
the gating circuit is connected with the output ends of the first receiving unit and the second receiving unit and comprises an AND gate circuit.
2. The CAN chip of claim 1, further comprising: a housing; the gating circuit, the sending unit, the reversing unit, the receiving unit and the logic judging circuit are all arranged in the shell.
3. The CAN chip of claim 2,
the input end of the sending unit is connected with a writing pin on the shell, and the output end of the sending unit is connected with the reversing unit and used for receiving a signal input through the writing pin;
the output end of the reversing unit is respectively connected with the first receiving unit and the second receiving unit, and is used for matching the sending unit with one of the first receiving unit and the second receiving unit, wherein the polarities of the first receiving unit and the second receiving unit are different;
the input ends of the first receiving unit and the second receiving unit are connected with the output end of the reversing unit, and the output ends of the first receiving unit and the second receiving unit are respectively connected with the gating circuit and the logic judging circuit;
a first end of the logic judgment circuit is connected with a polarity enabling pin, a second end of the logic judgment circuit is connected with the first receiving unit and the second receiving unit, and a third end of the logic judgment circuit is connected with the reversing unit;
the input end of the gating circuit is connected with the output pins of the first receiving unit and the second receiving unit.
4. The CAN chip of claim 3, wherein the output of the transmitting unit comprises: CAN _ H pin and CAN _ L pin.
5. The CAN chip of claim 4, wherein the commutation unit comprises: a first switching sub-circuit and a second switching sub-circuit; the first switching sub-circuit and the second switching sub-circuit are both connected with the CAN bus, and the CAN chip pin accessed by the first switching sub-circuit and the CAN chip pin accessed by the second switching sub-circuit have opposite polarities.
6. The CAN chip of claim 2, wherein an output of the commutation cell is connected to CAN H and CAN L pins provided on the housing.
7. The CAN chip of claim 2, further comprising: and the power supply pin and the power ground pin are arranged on the shell.
8. The CAN chip of claim 2, further comprising: and the extension pin is arranged on the shell.
9. The CAN chip of claim 2 wherein an output of said gating circuit is connected to a read pin disposed on said housing.
10. The CAN chip of claim 2, wherein input pins of the first receiving unit and the second receiving unit are connected to a CAN _ H pin and a CAN _ L pin provided on the housing.
11. The CAN chip of any one of claims 1 to 10, wherein the logic determination circuit comprises: a latch circuit.
12. An electronic device, comprising: a controller area network, CAN, chip, characterized in that said CAN chip is a CAN chip according to any of claims 1 to 11.
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