CN107195546A - A kind of groove forming method - Google Patents
A kind of groove forming method Download PDFInfo
- Publication number
- CN107195546A CN107195546A CN201710564684.1A CN201710564684A CN107195546A CN 107195546 A CN107195546 A CN 107195546A CN 201710564684 A CN201710564684 A CN 201710564684A CN 107195546 A CN107195546 A CN 107195546A
- Authority
- CN
- China
- Prior art keywords
- polysilicon
- trench
- oxide layer
- layer
- forming method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 59
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 178
- 229920005591 polysilicon Polymers 0.000 claims abstract description 177
- 238000005530 etching Methods 0.000 claims abstract description 54
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 42
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 42
- 239000010703 silicon Substances 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 36
- 230000008569 process Effects 0.000 claims description 20
- 230000003647 oxidation Effects 0.000 claims description 17
- 238000007254 oxidation reaction Methods 0.000 claims description 17
- 238000001259 photo etching Methods 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 4
- 230000008859 change Effects 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 10
- 230000009467 reduction Effects 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 239000013078 crystal Substances 0.000 description 9
- 239000000377 silicon dioxide Substances 0.000 description 5
- 230000002146 bilateral effect Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3088—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
Abstract
The invention provides a kind of groove forming method.The groove forming method includes：In silicon substrate formation polysilicon layer and in the polysilicon layer the first polysilicon trench of formation；The first oxide layer is formed on the polysilicon layer surface, first oxide layer covers the inner surface of first polysilicon trench；First oxide layer is performed etching and the second polysilicon trench is formed；The second oxide layer is formed on the polysilicon layer surface, second oxide layer covers the inner surface of second polysilicon trench；Second oxide layer is performed etching and the 3rd polysilicon trench is formed；The silicon substrate is performed etching by the use of the polysilicon layer as mask, and forms substrate trenches.The groove forming method reduction provided using the present invention makes requirement of the narrow groove to lithographic equipment, can efficiently reduce element manufacturing cost.
Description
【Technical field】
The present invention relates to semiconductor chip fabrication process technical field, specially power device manufacturing process flow field；
Especially, it is related to a kind of groove forming method.
【Background technology】
Drain-source the two poles of the earth of vertical bilateral diffusion field-effect tranisistor (VDMOS) make electric current in device respectively in the both sides of device
Internal vertical circulates, and adds current density, improves rated current, the conducting resistance of unit area is also smaller, is a kind of use
The power device of way widely.At present, the developing direction of vertical bilateral diffusion field-effect tranisistor is：
(1) forward conduction resistance is reduced to reduce static power consumption；
(2) switching speed is improved to reduce transient power loss.
Wherein, reduce static power consumption mainly to realize by reducing the total conducting resistance of device.The total conducting resistance of device
Mainly it is made up of three parts：(1) channel resistance；(2) drift zone resistance；(3) resistance substrate.The size of this three partial ohmics value by
The structure and manufacturing process of device are determined.
For low voltage power devices, drift zone resistance is smaller with respect to proportion in conducting resistance, so in electric conduction
Hinder channel resistance in part and play main decisive action.Therefore, reduction channel resistance can be substantially reduced the electric conduction of device
Resistance, reduces the quantity increase that primitive unit cell is dimensioned such that raceway groove in per device area, adds the width length ratio of raceway groove, make electric current
Path increases, so as to reduce channel resistance.At present, the main method for reducing primitive unit cell size is the width for reducing groove.Often at present
Groove manufacturing method, groove width is determined by the minimum line thickness of photoetching process.In order to reduce groove width, it is necessary to make
With more advanced lithographic equipment, device manufacturing cost can be substantially increased.
In view of this, it is necessary to which a kind of groove forming method is provided, with solve prior art presence above mentioned problem.
【The content of the invention】
One of purpose of the present invention is to provide a kind of ditch made suitable for narrow groove to solve the above problems
Groove forming method.
The groove forming method that the present invention is provided, including：In silicon substrate formation polysilicon layer and in the polysilicon layer shape
Into the first polysilicon trench；The first oxide layer, the first oxide layer covering described first are formed on the polysilicon layer surface
The inner surface of polysilicon trench；First oxide layer is performed etching and the second polysilicon trench is formed；In the polysilicon
Layer surface the second oxide layer of formation, second oxide layer covers the inner surface of second polysilicon trench；To described second
Oxide layer performs etching and forms the 3rd polysilicon trench；The silicon substrate is carved as mask using the polysilicon layer
Erosion, and form substrate trenches.
A kind of as the groove forming method provided in the present invention improves, in an advantageous embodiment, described in silicon
Substrate formation polysilicon layer simultaneously includes the step of the polysilicon layer the first polysilicon trench of formation：In the surface of silicon
Polysilicon layer is formed, and mask formation etching window is used as by the use of photoresist；Using the etching window in the polysilicon layer
Form the first polysilicon trench.
A kind of as the groove forming method provided in the present invention improves, in an advantageous embodiment, and described first
The groove width of polysilicon trench is consistent with the photoetching width of current photolithographic equipment.
A kind of as the groove forming method provided in the present invention improves, in an advantageous embodiment, described many
The step of crystal silicon layer surface the first oxide layer of formation, includes：, first will be described many after first polysilicon trench formation
The photoresist of crystal silicon layer surface is got rid of；First time oxidation processes are carried out on the polysilicon layer surface by thermal oxidation technology,
So as to form first oxide layer on the polysilicon layer surface.
A kind of as the groove forming method provided in the present invention improves, in an advantageous embodiment, and described first
Oxide layer is formed with oxide layer side wall, and the first polysilicon ditch in the trench vertical surfaces of first polysilicon trench
The oxide layer side wall of groove causes effective groove width of first polysilicon trench to reduce.
A kind of as the groove forming method provided in the present invention improves, in an advantageous embodiment, described to the
One oxide layer is performed etching and included the step of forming the second polysilicon trench：Aoxidized by dry etch process to described first
Layer is performed etching, so as to get rid of the oxidation of the trench bottom surfaces of the polysilicon layer surface and first polysilicon trench
Layer, wherein after first oxide layer etching, the vertical surface of first polysilicon trench has still had the oxidation
Layer side wall；After first oxide layer etching, continue to carry out the dry etch process to first polysilicon trench,
So as to form the second polysilicon trench；Wherein, the groove width of second polysilicon trench is less than the first polysilicon ditch
The groove width of groove.
A kind of as the groove forming method provided in the present invention improves, in an advantageous embodiment, described many
The step of crystal silicon layer surface the second oxide layer of formation, includes：After second polysilicon trench formation, pass through thermal oxide work
Skill carries out second of oxidation processes on the polysilicon layer surface, so as to form the second oxide layer on the polysilicon layer surface.
A kind of as the groove forming method provided in the present invention improves, in an advantageous embodiment, and described second
Oxide layer is formed further with oxide layer side wall, and second polycrystalline in the trench vertical surfaces of second polysilicon trench
The oxide layer side wall of silicon trench causes effective groove width of second polysilicon trench to reduce.
A kind of as the groove forming method provided in the present invention improves, in an advantageous embodiment, described to the
Dioxide layer is performed etching and included the step of forming three polysilicon trench：Aoxidized by dry etch process to described second
Layer is performed etching, so as to get rid of the oxidation of the trench bottom surfaces of the polysilicon layer surface and second polysilicon trench
Layer, wherein the vertical surface of second polysilicon trench has still had the oxide layer after second oxide layer etching
Side wall；After second oxide layer etching, continue to carry out the dry etch process to second polysilicon trench, from
And form the 3rd polysilicon trench；Wherein, the groove width of the 3rd polysilicon trench is less than second polysilicon trench
Groove width.
A kind of as the groove forming method provided in the present invention improves, in an advantageous embodiment, described to utilize
Polysilicon layer is performed etching as mask to the silicon substrate, and is included the step of form substrate trenches：In the 3rd polycrystalline
After silicon trench formation, by the use of the polysilicon layer with the 3rd polysilicon trench as mask, the silicon substrate is carried out
Dry etching, so as to etch substrate trenches in the silicon substrate；Wherein, the width of the substrate trenches is by more than the described 3rd
What the groove width of crystal silicon groove was determined.
Compared to prior art, the groove forming method multiple etching polysilicon of the invention provided and before each etching
Increase a polysilicon oxidation to reduce groove effective width, finally by the use of the polysilicon layer as mask with silicon lining
End eclipse carves groove, therefore photoetching width of the groove width much smaller than lithographic equipment of the substrate trenches.Therefore, using this hair
The groove forming method reduction of bright offer makes the requirement of narrow groove to lithographic equipment, can efficiently reduce element manufacturing into
This.
【Brief description of the drawings】
Technical scheme in order to illustrate the embodiments of the present invention more clearly, embodiment will be described below used in
Accompanying drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for ability
For the those of ordinary skill of domain, on the premise of not paying creative work, it can also be obtained according to these accompanying drawings other attached
Figure, wherein：
A kind of schematic flow sheet of embodiment of groove forming method that Fig. 1 provides for the present invention；
Fig. 2 is to make polysilicon layer in silicon substrate in the groove forming method shown in Fig. 1 and form the section of etching window
Schematic diagram；
Fig. 3 is the section signal using the etching window the first polysilicon trench of formation in the polysilicon layer shown in Fig. 2
Figure；
Fig. 4 is in polysilicon layer surface progress first time oxygen after the first polysilicon trench formation shown in Fig. 3
Change the diagrammatic cross-section for handling and being formed the first oxide layer；
Fig. 5 is that the first oxide layer shown in Fig. 4 is performed etching and the diagrammatic cross-section of the second polysilicon trench is formed；
Fig. 6 is in second of oxygen of polysilicon layer surface progress after the second polysilicon trench formation shown in Fig. 5
Change the diagrammatic cross-section for handling and being formed the second oxide layer；
Fig. 7 is that the second oxide layer shown in Fig. 6 is performed etching and the diagrammatic cross-section of the 3rd polysilicon trench is formed；
Fig. 8 is that the silicon substrate is carried out using the polysilicon layer with the 3rd polysilicon trench shown in Fig. 7 as mask
Etch and formed the diagrammatic cross-section of groove；
Fig. 9 is the contrast schematic diagram of the groove width shown in Fig. 8 and photoetching width.
【Embodiment】
The technical scheme in the embodiment of the present invention will be clearly and completely described below, it is clear that described implementation
Example is only a part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, this area is common
All other embodiment that technical staff is obtained under the premise of creative work is not made, belongs to the model that the present invention is protected
Enclose.
To solve the problem of being difficult to narrow groove of semiconductor trench preparation method presence of prior art, the present invention is carried
For a kind of groove forming method, it mainly passes through a photoetching, multiple etching polysilicon, polycrystalline of increase before etching every time
Silicon is aoxidized, and silica, thickness increase are formed after polysilicon oxidation, and then reduces trench mask width, is finally made with polysilicon
For mask etching formation groove, the final width of groove is much smaller than photoetching width, reduces the requirement to lithographic equipment, reduce
Device manufacturing cost.
Referring to Fig. 1, it is the groove forming method a kind of flow chart of embodiment of the invention provided.The groove is formed
Method can apply to the manufacture craft of power device, such as vertical bilateral diffusion field-effect tranisistor (VDMOS), for realizing work(
The narrow groove of rate device makes.Specifically, the groove forming method is mainly included the following steps that：
Step S1, mask formation etching window is used as in surface of silicon formation polysilicon layer, and by the use of photoresist.
Referring to Fig. 2, in step sl, a silicon substrate (Si substrates) being provided first, then, polycrystalline silicon growth work is utilized
Skill is in the silicon substrate one polysilicon layer of formation.After polysilicon layer formation, in polysilicon layer surface coating
Photoresist, and by the use of the photoresist as mask, etching window is produced, as shown in Figure 2.Wherein, the etching window
Opening size can be consistent with the photoetching width (i.e. the minimum line size of photoetching process) of current photolithographic equipment.
Step S2, using the etching window in the polysilicon layer the first polysilicon trench of formation.
Specifically, in step s 2, referring to Fig. 3, the etching window made using step S1, passes through dry etching work
Skill, can be in the polysilicon layer the first polysilicon trench of formation, wherein the groove width of first polysilicon trench is by institute
Etching window is stated to be determined.Also, in general, the groove width of first polysilicon trench is greater than expectation in the silicon
The target trench width of the substrate trenches of substrate formation.
Step S3, forms the first oxide layer, the first oxide layer covering described more than first on the polysilicon layer surface
The inner surface of crystal silicon groove；
Referring to Fig. 4, in step s3, after first polysilicon trench formation, first by the polysilicon layer
The photoresist on surface is got rid of, and then carries out first time oxidation processes on the polysilicon layer surface by thermal oxidation technology, from
And form the first oxide layer on the polysilicon layer surface.The material of first oxide layer can be specially silica (such as
First oxide layer can be silicon dioxide layer).Also, level of first oxide layer except covering the polysilicon layer
Beyond surface, the inner surface of first polysilicon trench, including trench vertical surfaces and trench bottom surfaces are also covered simultaneously, such as
Shown in Fig. 4.Groove vertical of first oxide layer in first polysilicon trench is can be seen that from Fig. 4 cross-section structure
Surface is formed with oxide layer side wall.
Step S4, performs etching to first oxide layer and forms the second polysilicon trench；
Referring to Fig. 5, in step s 4, first oxide layer is performed etching by dry etch process first, from
And the oxide layer of the trench bottom surfaces of the polysilicon layer surface and first polysilicon trench is got rid of, but now described
The vertical surface of one polysilicon trench has still had the oxide layer side wall.The oxide layer side wall can cause more than described first
The groove width of crystal silicon groove diminishes, therefore, in step s 4, after first oxide layer etching, continues to described the
One polysilicon trench carries out the dry etch process, so as to form the second polysilicon trench；Wherein, the second polysilicon ditch
Groove is using the oxide layer side wall of first polysilicon trench as side wall, therefore, and its groove width can be less than first polycrystalline
The groove width of silicon trench.
Step S5, forms the second oxide layer, the second oxide layer covering described more than second on the polysilicon layer surface
The inner surface of crystal silicon groove.
Referring to Fig. 6, after second polysilicon trench formation, by thermal oxidation technology in the polysilicon layer table
Face carries out second of oxidation processes, so as to form the second oxide layer on the polysilicon layer surface.The material of second oxide layer
Material equally can be specially silica (such as described second oxide layer can be silicon dioxide layer).Also, second oxidation
Layer also covers the inner surface of second polysilicon trench, bag simultaneously in addition to covering the horizontal surface of the polysilicon layer
Trench vertical surfaces and trench bottom surfaces are included, as shown in Figure 6；Second oxide layer is can be seen that from Fig. 6 cross-section structure to exist
The trench vertical surfaces of second polysilicon trench are formed further with oxide layer side wall.
Step S6, performs etching to second oxide layer and forms the 3rd polysilicon trench；
Referring to Fig. 7, in step s 6, second oxide layer is performed etching by dry etch process first, from
And the oxide layer of the trench bottom surfaces of the polysilicon layer surface and second polysilicon trench is got rid of, but now described
The vertical surface of two polysilicon trench has still had the oxide layer side wall.The oxide layer side wall can cause more than described second
The groove width of crystal silicon groove further reduces, therefore, in step s 6, after second oxide layer etching, Ke Yiji
It is continuous that the dry etch process is carried out to second polysilicon trench, so as to form the 3rd polysilicon trench.Wherein, described
Three polysilicon trench are using the oxide layer side wall of second polysilicon trench as side wall, therefore, and its groove width can be less than institute
The groove width of the second polysilicon trench is stated, i.e., it is relative to first polysilicon trench, and its groove width can at least reduce
The thickness of first oxide layer and second oxide layer, therefore the ditch groove width of first polysilicon trench can be significantly less than
Degree.
Step S7, is performed etching, and form substrate trenches by the use of the polysilicon layer as mask to the silicon substrate.
Referring to Fig. 8, after the 3rd polysilicon trench formation, using with many of the 3rd polysilicon trench
Crystal silicon layer carries out dry etching, so as to etch substrate trenches in the silicon substrate as mask to the silicon substrate.Wherein,
The width of the substrate trenches is determined by the groove width of the 3rd polysilicon trench；Therefore, as described above, described
The width of substrate trenches can be significantly less than the width of first polysilicon trench, that is, the photoetching for being less than the lithographic equipment is wide
Degree, as shown in Figure 9.The width of the substrate trenches is together decided on by the thickness of the photoetching width and oxide layer side wall.
Compared to prior art, the groove forming method that the present invention is provided is by multiple etching polysilicon and is etching every time
Increase a polysilicon oxidation before to reduce groove effective width, finally by the use of the polysilicon layer as mask with described
Silicon substrate etches groove, therefore photoetching width of the groove width much smaller than lithographic equipment of the substrate trenches.Therefore, use
The groove forming method reduction that the present invention is provided makes requirement of the narrow groove to lithographic equipment, can efficiently reduce element manufacturing
Cost.
Above-described is only embodiments of the present invention, it should be noted here that for one of ordinary skill in the art
For, without departing from the concept of the premise of the invention, improvement can also be made, but these belong to the protection model of the present invention
Enclose.
Claims (10)
1. a kind of groove forming method, it is characterised in that including：
In silicon substrate formation polysilicon layer and in the polysilicon layer the first polysilicon trench of formation；
The first oxide layer is formed on the polysilicon layer surface, first oxide layer covers the interior of first polysilicon trench
Surface；
First oxide layer is performed etching and the second polysilicon trench is formed；
The second oxide layer is formed on the polysilicon layer surface, second oxide layer covers the interior of second polysilicon trench
Surface；
Second oxide layer is performed etching and the 3rd polysilicon trench is formed；
The silicon substrate is performed etching by the use of the polysilicon layer as mask, and forms substrate trenches.
2. groove forming method according to claim 1, it is characterised in that it is described silicon substrate formation polysilicon layer and
The step of first polysilicon trench of polysilicon layer formation, includes：
Mask formation etching window is used as in surface of silicon formation polysilicon layer, and by the use of photoresist；
Using the etching window in the polysilicon layer the first polysilicon trench of formation.
3. groove forming method according to claim 2, it is characterised in that the groove width of first polysilicon trench
It is consistent with the photoetching width of current photolithographic equipment.
4. groove forming method according to claim 1, it is characterised in that described to form the first oxygen on polysilicon layer surface
The step of changing layer includes：
After first polysilicon trench formation, the photoresist on the polysilicon layer surface is got rid of first；
First time oxidation processes are carried out on the polysilicon layer surface by thermal oxidation technology, so that on the polysilicon layer surface
Form first oxide layer.
5. groove forming method according to claim 4, it is characterised in that first oxide layer is in first polycrystalline
The trench vertical surfaces of silicon trench are formed with oxide layer side wall, and the oxide layer side wall of first polysilicon trench causes institute
The effective groove width for stating the first polysilicon trench reduces.
6. groove forming method according to claim 1, it is characterised in that described to be performed etching to the first oxide layer and shape
The step of into the second polysilicon trench, includes：
First oxide layer is performed etching by dry etch process, so as to get rid of the polysilicon layer surface and institute
The oxide layer of the trench bottom surfaces of the first polysilicon trench is stated, wherein after first oxide layer etching, first polysilicon
The vertical surface of groove has still had the oxide layer side wall；
After first oxide layer etching, continue to carry out the dry etch process to first polysilicon trench, from
And form the second polysilicon trench；Wherein, the groove width of second polysilicon trench is less than first polysilicon trench
Groove width.
7. groove forming method according to claim 1, it is characterised in that described to form the second oxygen on polysilicon layer surface
The step of changing layer includes：
After second polysilicon trench formation, second of oxygen is carried out on the polysilicon layer surface by thermal oxidation technology
Change is handled, so as to form the second oxide layer on the polysilicon layer surface.
8. groove forming method according to claim 7, it is characterised in that second oxide layer is in second polycrystalline
The trench vertical surfaces of silicon trench are formed further with oxide layer side wall, and the oxide layer side wall of second polysilicon trench makes
The effective groove width for obtaining second polysilicon trench reduces.
9. groove forming method according to claim 1, it is characterised in that described to be performed etching to the second oxide layer and shape
The step of into three polysilicon trench, includes：
Second oxide layer is performed etching by dry etch process, so as to get rid of the polysilicon layer surface and institute
The oxide layer of the trench bottom surfaces of the second polysilicon trench is stated, wherein the second polysilicon ditch after second oxide layer etching
The vertical surface of groove has still had the oxide layer side wall；
After second oxide layer etching, continue to carry out the dry etch process to second polysilicon trench, from
And form the 3rd polysilicon trench；Wherein, the groove width of the 3rd polysilicon trench is less than second polysilicon trench
Groove width.
10. groove forming method according to any one of claim 1 to 9, it is characterised in that the utilization polysilicon layer
The step of being performed etching as mask to the silicon substrate, and form substrate trenches includes：
After the 3rd polysilicon trench formation, by the use of the polysilicon layer with the 3rd polysilicon trench as covering
Film, carries out dry etching, so as to etch substrate trenches in the silicon substrate to the silicon substrate；
Wherein, the width of the substrate trenches is determined by the groove width of the 3rd polysilicon trench.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710564684.1A CN107195546A (en) | 2017-07-12 | 2017-07-12 | A kind of groove forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710564684.1A CN107195546A (en) | 2017-07-12 | 2017-07-12 | A kind of groove forming method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107195546A true CN107195546A (en) | 2017-09-22 |
Family
ID=59883483
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710564684.1A Pending CN107195546A (en) | 2017-07-12 | 2017-07-12 | A kind of groove forming method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107195546A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1941411A (en) * | 2005-09-22 | 2007-04-04 | 三星电子株式会社 | Transistors including laterally extended active regions and methods of fabricating the same |
| CN104465323A (en) * | 2014-11-28 | 2015-03-25 | 上海华力微电子有限公司 | Method for reducing key dimension of active region |
| CN106098743A (en) * | 2015-04-29 | 2016-11-09 | 台湾积体电路制造股份有限公司 | The high aspect ratio etch that top does not broadens |
-
2017
- 2017-07-12 CN CN201710564684.1A patent/CN107195546A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1941411A (en) * | 2005-09-22 | 2007-04-04 | 三星电子株式会社 | Transistors including laterally extended active regions and methods of fabricating the same |
| CN104465323A (en) * | 2014-11-28 | 2015-03-25 | 上海华力微电子有限公司 | Method for reducing key dimension of active region |
| CN106098743A (en) * | 2015-04-29 | 2016-11-09 | 台湾积体电路制造股份有限公司 | The high aspect ratio etch that top does not broadens |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104733531B (en) | Use the double oxide Trench-gate power MOSFET of oxide filling groove | |
| CN107527948A (en) | Shield grid groove MOSFET and its manufacture method | |
| CN104795332B (en) | The forming method of fin formula field effect transistor | |
| CN102983171B (en) | The vertical structure without knot surrounding-gate MOSFET device and manufacture method thereof | |
| JPS5933880A (en) | Semiconductor device | |
| CN105448984A (en) | FinFET and preparation method thereof | |
| CN105448741A (en) | Shield grid groove type MOSFET process method | |
| CN205749689U (en) | A kind of test structure of fin formula field effect transistor parasitic capacitance | |
| CN206947355U (en) | A kind of electronic device | |
| CN108511521A (en) | A kind of production method of the igbt chip with the compound grid structure containing empty grid | |
| TW200418184A (en) | Semiconductor device and method for producing the same | |
| CN106024607B (en) | The manufacturing method of shield grid power MOSFET | |
| JPS5561037A (en) | Preparation of semiconductor device | |
| CN104638011B (en) | A kind of groove MOSFET device and preparation method thereof | |
| CN107195546A (en) | A kind of groove forming method | |
| US20140227878A1 (en) | Method for Manufacturing Small-Size Fin-Shaped Structure | |
| CN103730367B (en) | Semiconductor device manufacturing method | |
| CN105448981A (en) | VDMOS device, drain electrode structure thereof, and manufacturing method | |
| CN102479816B (en) | Metal-oxide semiconductor type field-effect transistor and manufacturing method thereof | |
| TWI689098B (en) | Multi-trench mosfet and fabricating method thereof | |
| CN108109909A (en) | A kind of forming method of groove | |
| CN208706657U (en) | A kind of buried gate structure | |
| CN108110056A (en) | Vertical bilateral diffusion field-effect tranisistor and preparation method thereof | |
| CN206819996U (en) | A kind of new electronic component | |
| CN108807517A (en) | Groove grid super node device and its manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170922 |
|
| RJ01 | Rejection of invention patent application after publication |