CN107181421A - It is a kind of to reduce the control method that digital control delay influences on LCL type combining inverter - Google Patents
It is a kind of to reduce the control method that digital control delay influences on LCL type combining inverter Download PDFInfo
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- CN107181421A CN107181421A CN201710430007.0A CN201710430007A CN107181421A CN 107181421 A CN107181421 A CN 107181421A CN 201710430007 A CN201710430007 A CN 201710430007A CN 107181421 A CN107181421 A CN 107181421A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
- H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
- H02M7/53873—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with digital control
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- Inverter Devices (AREA)
- Dc-Dc Converters (AREA)
Abstract
It is a kind of to reduce the control method that digital control delay influences on LCL type combining inverter, step 1 is the instant load-modulate modes of PWM, step 2 is that, in capacitance current feedback loop series connection single order high pass link (HPF), the output that it is exported with controller Gc (s) is superimposed.Step 1 eliminates digital control middle PWM loadings half and claps delay, step 2 compensate for capacitance current negative-feedback inner ring and partly clap delay in the zero-order holder of resonant frequency section, and the compatibility of LCL type combining inverter resonant frequency and control frequency is improved by step 1 and step 2.The present invention proposes that PWM loads+HPF compensation control programs immediately, on the one hand PWM loadings half are eliminated and clap delay, on the other hand delay of the active damping inner ring in resonant frequency section is compensate for, switching frequency and the compatibility and system stability margin of LCL filter resonant frequency is improved.
Description
Technical field
It is more particularly to a kind of to reduce digital control delay the present invention relates to LCL type control method of grid-connected inverter field
The control method influenceed on LCL type combining inverter.
Background technology
It is gradually deficient in traditional fossil energy, pollute under increasingly serious background, the new-energy grid-connected such as photovoltaic and wind energy is sent out
The application of electricity obtains tremendous development.Along with the continuous improvement of the new energy permeability such as photovoltaic and wind energy, combining inverter to
The stability and the quality of power supply of power network bring very big challenge.LCL type combining inverter is three rank lacuna systems, it is contemplated that LCL
The presence of resonance spikes, system open loop is unstable.For the existing various control scheme of suppression of resonance spikes, wherein based on electric capacity
The active damping control program of Current Negative Three-Point Capacitance suppresses resonance spikes only at resonant frequency, does not change system low frequency open-loop gain
Do not influence high-frequency harmonic to decay again, weaken resonance amplitude response only at resonance spikes, be a kind of wider scheme of application.
It can be equivalent at electric capacity two ends in capacitance current active damping negative-feedback resonance spikes Restrain measurement, its physical significance
Parallel resistance, so as to reach suppression resonance spikes effect.Because grid-connected inverting system is typically realized using digital control, it will usually
Introducing sampling zeroth order keeps half bat to clap delay with PWM loadings half.After being introduced in view of digital control delay, on the one hand reduce and be
The Phase margin of system open-loop transfer function, influences dynamic characteristic；In addition, the delay has had a strong impact on active damping LCL filter
Impedance operator, system resonance frequencies fall in different frequency ranges, and LCL impedance operators differ greatly.Thus, LCL filter resonance
The design of frequency and the selection of switching frequency are no longer independent, and both intercouple, once choose mismatch, system minimum phase attribute
It is difficult to ensure that, networking current stability is challenged.During in view of low switching frequency and electric network impedance, the situation is more very.
The content of the invention
In order to solve above-mentioned problem, the present invention provides a kind of digital control delay that reduces to LCL type parallel network reverse
The control method of device influence, can eliminate PWM loading delays, and combination sampling zeroth order keeps delay to hinder LCL active dampings
The influence of anti-characteristic, proposes the compensation tache of compensation active damping inner ring resonant frequency section delay, improve system control frequency with
The inter-compatibility of LCL filter resonant frequency, for up to this purpose, the present invention provides a kind of digital control delay that reduces to LCL
The control method of type combining inverter influence, this method is implemented according to following steps：
Step 1 is the instant load-modulate modes of PWM：Tc1=0.5T is met as boundary using computation delay of sampling, PWM is divided
Manner of comparison is interval, i.e., in dutycycle dk<Using high effectively manner of comparison when 0.5, in dk>Low effective ratio is used in the case of 0.5
Compared with mode, then controlling the whole period, dutycycle dk desirable scope is (0,1), solves PWM and loads dutycycle immediately
Dk limitation problems；
Step 2 compensate for capacitance current negative-feedback inner ring and partly clap delay in the zero-order holder of resonant frequency section：For electricity
The compensation of capacitance current negative-feedback active damping inner ring zero-order holder delay, proposition is compensated for single order high pass link, humorous
The delay that the approximate compensation of vibration frequency section is introduced by the equivalent inertial element of zero-order holder.
Further improvement of the present invention, step one is comprised the following steps that：
Step 1.1, sampled at DSP carrier triangular crest values into interruption, wherein the sampling stand-by period is tc2,
Software control algorithm calculates the time for tc1-tc2, and ur is triangular carrier amplitude, and um is the modulating wave that controller is exported, and in meter
Calculation is loaded immediately after finishing to be updated；
Step 1.2, enter at triangle crest value and interrupt, calculate the controlled quentity controlled variable um currently clapped, further software
Judge um correspondence current duty cycles dk size, work as dk<When 0.5, PWM manner of comparison is set to high effectively manner of comparison；Work as dk>
When 0.5, PWM manner of comparison is low effective manner of comparison by software modification, and now the counter inside DSP need to be right with (1-dk)
The digital quantity answered is compared, rather than dk, i.e., between kth+1 to k+2 is clapped, counter is no longer corresponding with um to be compared, but with
The corresponding digital quantities of 1-dk are compared at tc3, and then overturn PWM ripples, it is contemplated that PWM ripples have been set low before the bat of kth+1, institute
With comparison point tc3 arrival before be always maintained at the low level state, tc3 at reach comparison point, this be level upset at, but
Due to PWM manner of comparison have been modified to it is low effectively, so through not trigging signal tc3 at, continuing to keep low level, up to counter
Reach at tc4, level upset is high level.Hereafter, in period of the dutycycle more than 0.5 due to the recovery of high level, PWM is low
Effective ratio reaches stable state compared with state and recovers normal；
Step 1.3, when similarly can obtain dutycycle by switching to more than 0.5 less than 0.5, as shown in waveform, its high electricity
Level state can continue to keep, i.e., be high level before the bat of kth+3, while kth+3 has switched to high effectively manner of comparison after clapping,
Compared at tc5 and continue to high level state, until being able to level upset at tc6；
Step 1.4, it is contemplated that manner of comparison switching dutycycle occurs when dutycycle is by becoming greater than 0.5 less than 0.5
Missing, occurs the situation of dutycycle increase when becoming smaller than 0.5 more than 0.5 by dutycycle, enter in control software and interrupt journey
After sequence, it should first determine whether the size of a cycle dutycycle, and as condition to change PWM manner of comparison, if dutycycle
During by becoming greater than 0.5 less than 0.5, then PWM state is put into height by low after triangle crest value is entered；Dutycycle is by more than 0.5
When becoming smaller than 0.5, then PWM state is set low by height, compensate for system and lose or increase in the PWM that dutycycle is introduced at switching
Plus phenomenon.
Further improvement of the present invention, step 2 is comprised the following steps that：
Step 2.1：Propose that single order high pass link transmission function is：High pass link is connected on
Capacitance current sampling feedback loop, capacitance current sampled signal ics is ihc after high pass link, and is superimposed upon controller Gc (s)
Output end.
The present invention is a kind of to reduce the control method that digital control delay influences on LCL type combining inverter, and the present invention is proposed
PWM loads+HPF compensation control programs immediately, on the one hand eliminates PWM loadings half and claps delay, on the other hand compensate for active resistance
Buddhist nun's inner ring improves switching frequency and the compatibility and system of LCL filter resonant frequency is stable in the delay of resonant frequency section
Nargin.
Brief description of the drawings
The control method control structure schematic diagram that Fig. 1 provides for the present invention；
Fig. 2 loads manner of comparison schematic diagram immediately for the PWM that the present invention is provided；
The control block diagram for the raising LCL type combining inverter compensation delay that Fig. 3 provides for the present invention；
Fig. 4 is proposition single order high pass link Bode figures；
Fig. 5 is the experimental waveform under not being eliminated that is delayed；
Fig. 6 is the experimental waveform of control mode of the present invention.
Embodiment
The present invention is described in further detail with embodiment below in conjunction with the accompanying drawings：
The present invention provides the control method that a kind of reduction digital control delay influences on LCL type combining inverter, can disappear
It is delayed except PWM is loaded, and combines sampling zeroth order and keep influence of the delay to LCL active damping impedance operators, proposes that compensation has
The compensation tache of source damping inner ring resonant frequency section delay, raising system control frequency is mutual with LCL filter resonant frequency
Compatibility.
The structure chart of LCL type combining inverter provided by the present invention is as shown in Figure 1：Wherein LCL filter is by inverter
Side inductance L1, net side inductance L2 and filter capacitor C compositions.Phaselocked loop (PLL) module samples point of common coupling voltage Vpcc is passed through
Cross Second Order Generalized Integrator extraction line voltage fundamental wave and enter horizontal lock, output phase information θ and current amplitude I*Resultant current base
Quasi- iref.H2 is networking current sample coefficient, and Kg is voltage feed-forward control coefficient, and H1 is active damping coefficient, Gc(s) it is electric current
Adjuster transmission function, finally forms voltage VAB, and then obtain the given networking electric current ig of benchmark between bridge arm.Wherein A is one
Rank high pass compensation tache, B is DSP inner modulations ripple and carrier wave comparing element, specifically can be as shown in Figure 2.
Step (1.1)：Fig. 2 is the instant loading scheme principle schematics of improved PWM, at DSP carrier triangular crest values
Sampled into interrupting, wherein the sampling stand-by period is tc2, software control algorithm calculates the time for tc1-tc2, and ur is triangle
Carrier amplitude, um is the modulating wave that controller is exported, and loading updates immediately after calculating is finished.Fig. 2 gives PWM duty cycle
Dk by less than 0.5 to more than 0.5 again arrive less than 0.5 variation pattern, to illustrate modification the instant loading scheme of PWM manner of comparison
Principle.
Step (1.2)：Waveform A is directly changes the control program of PWM manner of comparison in software in Fig. 2, i.e., in triangle
Enter at crest value and interrupt, calculate the controlled quentity controlled variable um currently clapped, further software judges um correspondence current duty cycles dk
Size.Work as dk<When 0.5, PWM manner of comparison is set to high effectively manner of comparison；Work as dk>When 0.5, PWM manner of comparison passes through
Software modification is low effective manner of comparison.It is worth noting that, after low effective manner of comparison is revised as, being rung according to PWM momentums
Answer it is constant it is theoretical understand, now the counter inside DSP need to digital quantity corresponding with (1-dk) be compared, rather than dk exists
Kth+1 is between k+2 bats, and counter is no longer corresponding with um to be compared, but digital quantity corresponding with 1-dk at tc3 is compared,
And then overturn PWM ripples.In view of kth+1 bat before PWM ripples set low, so comparison point tc3 arrival before be always maintained at
The low level state.Comparison point is reached at tc3, this is at level upset, but because PWM manner of comparison has been modified to low have
Effect, so through not trigging signal tc3 at, continuing to keep low level, until counter reaches tc4 places, level is overturn as high level.
Hereafter, in period of the dutycycle more than 0.5 due to the recovery of high level, the low effective ratios of PWM reach stable state compared with state and recovered
Normally.
Step (1.3)：When similarly can obtain dutycycle by switching to more than 0.5 less than 0.5, such as waveform A institutes in Fig. 2
Show, its high level state can continue to keep, i.e., be high level before the bat of kth+3, while having been switched to after the bat of kth+3 high effectively
Manner of comparison, is compared at tc5 and continues to high level state, until being able to level upset at tc6.
Step (1.4)：Manner of comparison switching duty occurs during in view of dutycycle by becoming greater than 0.5 less than 0.5
Than missing, the situation of dutycycle increase occurs when becoming smaller than 0.5 more than 0.5 by dutycycle, as shown in situation A in Fig. 2.Cause
This, after control software enters interrupt routine, it should first determine whether the size of a cycle dutycycle, and as condition to repair
Change PWM manner of comparison, if dutycycle less than 0.5 by becoming greater than 0.5, enter triangle crest value after by PWM state by
It is low to put height；When dutycycle more than 0.5 by becoming smaller than 0.5, such as Fig. 3 compensates the control being delayed to improve LCL type combining inverter
Block diagram, then set low PWM state by height, be compensate for system and is lost or increase phenomenon in the PWM that dutycycle is introduced at switching, such as
In Fig. 2 shown in situation B waveforms.
Step (2.1)：Propose that single order high pass link (HPF) transmission function is：I.e. by high pass ring
Section is connected on capacitance current sampling feedback loop, and capacitance current sampled signal ics is ihc after high pass link, and is superimposed upon control
The output end of device Gc (s) processed.
Fig. 4 gives the Bode figures that zeroth order keeps time delay process and single order high pass compensation tache, and Fig. 5 is not eliminated for delay
Under experimental waveform；Fig. 6 is the experimental waveform of control mode of the present invention, and zeroth order keeps time delay process not influence system amplitude to increase
Benefit, but its phase angle characteristics is below 0 degree of line, and monotone decreasing, reduces system Phase margin and the impedance of influence active damping is special
Property.Its amplitude gain of single order high pass compensation tache attenuation characteristic is presented to low frequency, medium-high frequency section influence is smaller in below 0dB,
Because active damping stability occurs over just resonant frequency section, therefore the influence of amplitude gain can be neglected；Its phase angle 0 degree of line with
On, to the compensation to resonant frequency section delay, but phase angle compensation tapers off trend.
The above described is only a preferred embodiment of the present invention, being not the limit for making any other form to the present invention
System, and any modification made according to technical spirit of the invention or equivalent variations, still fall within model claimed of the invention
Enclose.
Claims (3)
1. a kind of reduce the control method that digital control delay influences on LCL type combining inverter, it is characterised in that：This method according to
Implement according to following steps：
Step 1 is the instant load-modulate modes of PWM：Tc1=0.5T is met as boundary using computation delay of sampling, PWM is divided and compares
Mode is interval, i.e., in dutycycle dk<Using high effectively manner of comparison when 0.5, in dk>Low effective ratio side is used in the case of 0.5
Formula, then controlling whole period, dutycycle dk desirable scope is (0,1), solve PWM load immediately dutycycle dk by
Limit problem；
Step 2 compensate for capacitance current negative-feedback inner ring and partly clap delay in the zero-order holder of resonant frequency section：For electric capacity electricity
The compensation of negative-feedback active damping inner ring zero-order holder delay is flowed, proposition is compensated for single order high pass link, in resonance frequency
The delay that the approximate compensation of rate section is introduced by the equivalent inertial element of zero-order holder.
2. the control method that a kind of reduction digital control delay according to claim 1 influences on LCL type combining inverter,
It is characterized in that：Step one is comprised the following steps that：
Step 1.1, sampled at DSP carrier triangular crest values into interruption, wherein the sampling stand-by period is tc2, software control
Algorithm processed calculates the time for tc1-tc2, urFor triangular carrier amplitude, umThe modulating wave exported for controller, and after calculating is finished
Load and update immediately；
Step 1.2, enter at triangle crest value and interrupt, calculate the controlled quentity controlled variable u currently clappedm, further software judges um
Correspondence current duty cycle dkSize, work as dk<When 0.5, PWM manner of comparison is set to high effectively manner of comparison；Work as dk>When 0.5,
PWM manner of comparison is low effective manner of comparison by software modification, and now the counter inside DSP need to be with (1-dk) corresponding number
Word amount is compared, rather than dk, i.e., kth+1 to k+2 clap between, counter no longer with umCorrespondence compares, but and tc3Locate 1-dk
Corresponding digital quantity is compared, and then overturns PWM ripples, it is contemplated that PWM ripples have been set low before the bat of kth+1, so comparing
Point tc3The low level state is always maintained at before arrival, in tc3Place reaches comparison point, and this is at level upset, but due to PWM ratios
Compared with mode have been modified to it is low effectively, so through tc3Locate not trigging signal, continue to keep low level, until counter reaches tc4Place,
Level upset is high level.Hereafter, in period of the dutycycle more than 0.5 due to the recovery of high level, the low effective ratios of PWM are compared with shape
State reaches stable state and recovers normal；
Step 1.3, when similarly can obtain dutycycle by switching to more than 0.5 less than 0.5, as shown in waveform, its high level shape
State can continue to keep, i.e., be high level before the bat of kth+3, while kth+3 has switched to high effectively manner of comparison after clapping, in tc5
Place is compared and continues to high level state, until tc6Place is able to level upset；
Step 1.4, it is contemplated that occur that manner of comparison switching dutycycle is lacked when dutycycle is by becoming greater than 0.5 less than 0.5,
The situation of dutycycle increase occurs when becoming smaller than 0.5 more than 0.5 by dutycycle, after control software enters interrupt routine,
The size of a cycle dutycycle should be first determined whether, and as condition to change PWM manner of comparison, if dutycycle by less than
0.5 when becoming greater than 0.5, then PWM state is put into height by low after triangle crest value is entered；Dutycycle more than 0.5 from being changed into small
When 0.5, then PWM state is set low by height, compensate for system and lost in the PWM that dutycycle is introduced at switching or increase existing
As.
3. the control method that a kind of reduction digital control delay according to claim 1 influences on LCL type combining inverter,
It is characterized in that：Step 2 is comprised the following steps that：
Step 2.1：Propose that single order high pass link transmission function is：High pass link is connected on electric capacity
Current sample feedback control loop, capacitance current sampled signal ics is ihc after high pass link, and is superimposed upon the defeated of controller Gc (s)
Go out end.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108173444A (en) * | 2017-12-16 | 2018-06-15 | 西安翌飞核能装备股份有限公司 | A kind of multiple-variable flow device active damping control method in parallel |
| CN108631629A (en) * | 2018-02-28 | 2018-10-09 | 南京航空航天大学 | Improve a kind of phase lead compensation method of LCL type gird-connected inverter robustness |
| CN112769347A (en) * | 2020-12-31 | 2021-05-07 | 中国科学院电工研究所 | Time delay compensation control method for converter |
| CN115425835A (en) * | 2022-09-16 | 2022-12-02 | 西南交通大学 | Traction rectifier power factor compensation method aiming at digital control delay |
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| CN105591400A (en) * | 2016-01-15 | 2016-05-18 | 湖南大学 | Rapid robustness single-current feedback control method of LCL type grid-connected inverter |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108173444A (en) * | 2017-12-16 | 2018-06-15 | 西安翌飞核能装备股份有限公司 | A kind of multiple-variable flow device active damping control method in parallel |
| CN108173444B (en) * | 2017-12-16 | 2019-10-29 | 西安翌飞核能装备股份有限公司 | A kind of multiple-variable flow device active damping control method in parallel |
| CN108631629A (en) * | 2018-02-28 | 2018-10-09 | 南京航空航天大学 | Improve a kind of phase lead compensation method of LCL type gird-connected inverter robustness |
| CN112769347A (en) * | 2020-12-31 | 2021-05-07 | 中国科学院电工研究所 | Time delay compensation control method for converter |
| CN112769347B (en) * | 2020-12-31 | 2022-04-26 | 中国科学院电工研究所 | Time delay compensation control method for converter |
| CN115425835A (en) * | 2022-09-16 | 2022-12-02 | 西南交通大学 | Traction rectifier power factor compensation method aiming at digital control delay |
| CN115425835B (en) * | 2022-09-16 | 2023-10-24 | 西南交通大学 | Traction rectifier power factor compensation method for digital control delay |
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