CN107179963B

CN107179963B - Backup method and device for nonvolatile static random access memory

Info

Publication number: CN107179963B
Application number: CN201610141206.5A
Authority: CN
Inventors: 刘旭东; 宋昆鹏; 陈云
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2016-03-11
Filing date: 2016-03-11
Publication date: 2021-02-23
Anticipated expiration: 2036-03-11
Also published as: CN107179963A

Abstract

The invention discloses a backup method and a backup device of a nonvolatile static random access memory (NVSRAM), wherein the NVSRAM comprises an SRAM and a nonvolatile memory (NVM), and the method comprises the following steps: determining a last used bit RUB value corresponding to a cache block in the SRAM; and backing up the data in the cache block of the SRAM to the NVM according to the sequence of the RUB values from small to large. According to the scheme, based on the RUB value corresponding to the cache block in the SRAM, when the system is powered off, the data in the SRAM is backed up to the NVM, so that related steps of dead block judgment in the prior art are omitted, a backup method of the NVSRAM is simplified, and hardware overhead related to backup in the NVSRAM is reduced.

Description

Backup method and device for nonvolatile static random access memory

Technical Field

The embodiment of the invention relates to the field of computers, in particular to a backup method and a backup device of a nonvolatile static random access memory.

Background

In recent years, with the development of large multi-core computing systems, the demand for high-density and high-performance on-chip cache has increased. A Nonvolatile Random Access Memory (SRAM) is a Memory structure combining an SRAM and a Nonvolatile Memory (NVM). And in the working mode, the SRAM is used for storing data, and the data can be written into the NVM unit when power is off. Non-volatile SRAM (NVSRAM) reduces power consumption while ensuring storage performance and data reliability, and is an ideal storage material for future mobile terminals, Personal Computers (PCs) and servers.

The backup process of the NVSRAM requires a large on-chip energy storage capacitor to supply power, which introduces a large chip area overhead and cost overhead. With the increase of the storage capacity, the NVSRAM-based parallel backup process generates a large peak current (Inrush current), which reduces the stability of the system; the backup time of the serial backup method based on the NVSRAM can be increased along with the increase of the backup data quantity, and the system performance is influenced. In practical application, the parallel backup process and the serial backup process based on the NVSRAM all back up the data stored in the NVSRAM, and the all backup process has larger data redundancy.

In the prior art, statistical Based Dead Block Prediction (SBDP) is a partial backup method Based on NVSRAM. The core idea of the method is that based on the difference of the distribution proportion of the death block and the survival block to different Recently Used Bits (RUBs), the optimal RUB threshold is selected according to the statistical distribution proportion result to judge the death block and the survival block. Wherein, RUB is a bit identifying a cache access order in a Least Recently Used (LRU) replacement algorithm, and a larger RUB value indicates that a last access time of a cache block is farther from a current time.

In the SBDP-based partial backup method for the NVSRAM, a nonvolatile processor needs to determine a decision result of a cache Block corresponding to an RUB according to a buffered Block sample Counter (Sampled Block Counter) and a Dead Block Counter (Dead Block Counter) corresponding to the RUB, where the decision result is used to indicate a ratio of Dead blocks in all corresponding cache blocks of an RUB value; the nonvolatile processor may determine whether the cache Block is a Dead Block according to the determination result and the state information bits (dirty bit and valid bit) corresponding to the cache Block, and store the prediction result of the cache Block in a Dead Block Table (Dead Block Table), so that the nonvolatile processor may perform partial backup on data stored in the SRAM according to the prediction result of the Dead Block stored in the Dead Block Table when the system is powered off. In the above-mentioned partial backup method of the NVSRAM based on the SBDP, the nonvolatile processor needs a large amount of hardware for determining whether the cache block is a dead block, which may cause a large hardware overhead.

Disclosure of Invention

The application provides a backup method and a backup device of a nonvolatile static random access memory, so as to simplify the backup method of an NVSRAM.

In a first aspect, the present application provides a backup method for a non-volatile static random access memory NVSRAM, the NVSRAM comprising an SRAM and a non-volatile memory NVM, the method comprising: determining a last used bit RUB value corresponding to a cache block in the SRAM; and backing up the data in the cache block of the SRAM to the NVM according to the sequence of the RUB values from small to large.

According to the scheme, based on the RUB value corresponding to the cache block in the SRAM, when the system is powered off, the data in the SRAM is backed up to the NVM, so that related steps of dead block judgment in the prior art are omitted, a backup method of the NVSRAM is simplified, and hardware overhead related to backup in the NVSRAM is reduced.

With reference to the first aspect, in a possible implementation form of the first aspect, before backing up data in cache blocks of the SRAM into the NVM in the order of smaller RUB values to larger RUB values, the method further includes: and backing up a dirty block in a cache block of the SRAM into the NVM.

According to the scheme, before the backup process of the data is carried out based on the RUB value, the data in the dirty block is backed up to the NVM, so that the reliability of data storage in the NVSRAM can be improved.

With reference to the first aspect and any one of the foregoing possible implementation manners, in a possible implementation form of the first aspect, the method further includes: monitoring the electric quantity of a standby power supply of the SRAM in the data backup process of the SRAM; and stopping the data backup process when the electric quantity of the standby power supply is less than or equal to a preset threshold value.

The scheme focuses on the electric quantity of the standby power supply in real time, and judges whether the rest cache blocks are backed up or not by combining the electric quantity of the standby power supply, so that the data backup failure possibly caused by the sudden termination of the data backup process is avoided.

With reference to the first aspect and any one of the foregoing possible implementation manners, in a possible implementation form of the first aspect, the SRAM includes multiple columns of cache lines, where each column of cache lines includes one or more cache blocks, and backing up data in the cache blocks of the SRAM to the NVM in an order from a small value to a large value includes: backing up the cache blocks with the RUB values i in the cache lines into the NVM column by column, determining whether all data in the SRAM are completely backed up, if not, repeatedly executing the step until all data in the SRAM are completely backed up or the electric quantity of a standby power supply of the SRAM is less than or equal to a preset threshold value, wherein i is an integer and the initial value of i is 0.

In a second aspect, the present application provides a backup apparatus for a non-volatile static random access memory NVSRAM, the NVSRAM comprising an SRAM and a non-volatile memory NVM, the apparatus comprising: a determining module, configured to determine a last used bit RUB value corresponding to a cache block in the SRAM; and the backup module is used for backing up the data in the cache block of the SRAM to the NVM according to the sequence from small to large of the RUB value determined by the determination module.

With reference to the second aspect, in a possible implementation form of the second aspect, the backup module is further configured to: and backing up a dirty block in a cache block of the SRAM into the NVM.

With reference to the second aspect and any one of the foregoing possible implementation manners, in a possible implementation form of the second aspect, the apparatus further includes: the monitoring module is used for monitoring the electric quantity of a standby power supply of the SRAM in the data backup process of the SRAM; and the control module is used for stopping the data backup process when the electric quantity of the standby power supply is less than or equal to a preset threshold value.

With reference to the second aspect and any one of the foregoing possible implementation manners, in a possible implementation form of the second aspect, the SRAM includes multiple columns of cache lines, where each column of cache lines includes one or more cache blocks, and the backup module is specifically configured to: backing up the cache blocks with the RUB values i in the cache lines into the NVM column by column, determining whether all data in the SRAM are completely backed up, if not, repeatedly executing the step until all data in the SRAM are completely backed up or the electric quantity of a standby power supply of the SRAM is less than or equal to a preset threshold value, wherein i is an integer and the initial value of i is 0.

In a third aspect, the present application provides a backup apparatus for NVSRAM, where the NVSRAM includes an SRAM and a nonvolatile memory NVM, the apparatus including: a memory, a processor, an input/output interface, a communication interface and a bus system, wherein the memory, the processor, the input/output interface and the communication interface are connected by the bus system, the memory is used for storing instructions, and the processor is used for executing the method of the first aspect.

In a fourth aspect, the present application provides a computer-readable storage medium for storing program code of a backup method of a non-volatile static random access memory NVSRAM, the program code for executing the method instructions of the first aspect.

In some implementations, a Dirty block may refer to a cache block with a Dirty bit (Dirty bit) of 1, and the data stored in the cache block is inconsistent with the data stored in main memory.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments of the present invention will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 shows statistics of death and survival blocks for different RUBs based on the SBDP algorithm.

Fig. 2 shows a schematic diagram of an application scenario of an embodiment of the present invention.

FIG. 3 shows a backup method of NVSRAM according to an embodiment of the present invention.

Fig. 4 shows a backup apparatus of NVSRAM according to an embodiment of the present invention.

Fig. 5 shows a backup apparatus of NVSRAM according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Fig. 1 shows statistics of death and survival blocks for different RUBs based on the SBDP algorithm. As can be seen from the statistical results of the four test samples shown in fig. 1, the larger the RUB value is, the larger the proportion of dead blocks in the cache block corresponding to the RUB value is, the smaller the RUB value is, and the larger the proportion of live blocks in the cache block corresponding to the RUB value is. In the 4 test samples shown in fig. 1, only in the third case, the ratio of dead blocks in the cache block corresponding to RUB ═ 0 is large, all the cache blocks corresponding to RUB ═ 0 are marked as dead blocks, and in the remaining three cases, the ratio of live blocks in the cache block corresponding to RUB ═ 0 is large, and all the cache blocks corresponding to RUB ═ 0 are marked as live blocks. Therefore, the backup is universal and universal when the cache corresponding to the RUB ═ 0 is started.

In view of the above statistical information, the method for backing up a nonvolatile static random access memory according to the embodiment of the present invention can omit the related steps related to determination of a dead block in the prior art, and directly back up data stored in an SRAM according to an RUB value corresponding to a cache block where the data is located.

The backup method of the non-volatile static random access memory according to the embodiment of the invention is described in detail below with reference to fig. 2 and 3.

Fig. 2 shows a schematic diagram of an application scenario of an embodiment of the present invention. The application scenario shown in fig. 2 may be an energy sensor device that may be applied in extreme environments for data collection or logging and maintenance related to geographical environments, airlines, etc. The Energy Sensor device shown in fig. 2 includes an Energy collection module (Energy Havestor), a nonvolatile processor (NVP), a peripheral Sensor (Sensor), a data storage unit, and a wireless Sensor (Transceiver).

If the energy collecting module generates a square wave, a Voltage Detection Circuit (VDC) can detect the power supply voltage in real time, when the voltage is lower than a preset threshold value, the VDC judges that the power supply of the energy sensor device is cut off at the moment, therefore, the VDC immediately sends a backup instruction to the nonvolatile processor, then the nonvolatile processor backs up data from the volatile unit to the nonvolatile unit, and the backup process is completed under the supply of a backup power supply (such as an on-chip capacitor).

FIG. 3 illustrates a backup method of NVSRAM of an embodiment of the present invention, which may be performed by a nonvolatile processor. The NVSRAM comprises an SRAM and an NVM, and the method shown in FIG. 3 comprises the following steps:

and 310, determining a corresponding RUB value of a latest used bit of a cache block in the SRAM.

And 320, backing up the data in the cache block of the SRAM to the NVM according to the sequence of the RUB values from small to large.

For example, the cache block corresponding to RUB ═ 0 may be backed up first, then the cache block corresponding to RUB ═ 1 may be backed up, and so on until all the cache blocks in the SRAM are backed up, and the backup operation may be ended.

Optionally, as an embodiment, before backing up data in cache blocks of the SRAM into the NVM in the order from small to large of RUB values, the method further includes: and backing up a dirty block in a cache block of the SRAM into the NVM.

Optionally, as an embodiment, the method further includes: monitoring the electric quantity of a standby power supply of the SRAM in the data backup process of the SRAM; and stopping the data backup process when the electric quantity of the standby power supply is less than or equal to a preset threshold value.

Specifically, when the first row of dirty blocks in the SRAM is backed up, the power amount in the standby power supply may be detected, and if the power amount is sufficient to back up the dirty blocks in the next row of cache rows, that is, higher than the power amount threshold, the dirty blocks in the next row of cache rows may be backed up until the power amount of the standby power supply is insufficient, or until all data in the cache blocks other than the cache block corresponding to the SRAM whose valid bit is 0 are backed up is completed, and the backup operation is ended.

It should be understood that, when the backup of the dirty blocks in the first row of cache columns is started, it may be assumed that the amount of power in the backup power supply is sufficient to backup the dirty blocks in the first row of cache columns, that is, when the backup of the dirty blocks in the first row of cache columns is started, the amount of power in the backup power supply may not be detected in energy, and the energy detection of the backup power supply may be performed every time one row of cache columns is backed up in a later backup process. The embodiment of the present invention does not specifically limit the electric quantity detection method of the standby power supply.

Optionally, as an embodiment, the SRAM includes multiple columns of Cache lines (Cache lines), where each column of Cache lines includes one or more Cache blocks, and the backing up data in the Cache blocks of the SRAM into the NVM according to a sequence from a small value to a large value includes: backing up the cache blocks with the RUB values i in the cache lines into the NVM column by column, determining whether all data in the SRAM are completely backed up, if not, repeatedly executing the step until all data in the SRAM are completely backed up or the electric quantity of a standby power supply of the SRAM is less than or equal to a preset threshold value, wherein i is an integer and the initial value of i is 0.

It should be understood that the above described SRAM comprises N columns of cache lines with respect to the degree of cache associativity. For example, in a four-way set associative cache, there are 4 columns of cache lines, i.e., N-4.

The NVSRAM backup method according to an embodiment of the present invention is described in detail above with reference to fig. 1 to 3. The backup apparatus of the NVSRAM according to an embodiment of the present invention is described in detail below with reference to fig. 4 and 5. It should be understood that the backup device of the NVSRAM shown in fig. 4 can implement the steps shown in fig. 3, and in order to avoid repetition, the detailed description is omitted here.

Fig. 4 is a backup device of NVSRAM according to an embodiment of the present invention, where the NVSRAM includes an SRAM and a nonvolatile memory NVM, and the device includes: a determination module 410 and a backup module 420.

A determining module 410, configured to determine a last used bit RUB value corresponding to a cache block in the SRAM;

a backup module 420, configured to backup data in the cache block of the SRAM to the NVM according to a descending order of the RUB values determined by the determining module.

Fig. 5 is a backup device of NVSRAM according to an embodiment of the present invention, where the NVSRAM includes an SRAM and a nonvolatile memory NVM, and the device in fig. 5 includes: memory 510, processor 520, input/output interface 530, communication interface 540, and bus system 550. The memory 510, the processor 520, the input/output interface 530 and the communication interface 540 are connected via a bus system 550, the memory 510 is used for storing instructions, and the processor 520 is used for executing the instructions stored in the memory 510, so as to control the input/output interface 530 to receive input data and information, output data such as operation results, and control the communication interface 550 to send signals.

A processor 520 configured to determine a last used bit RUB value corresponding to a cache block in the SRAM; and backing up the data in the cache block of the SRAM to the NVM according to the sequence of the RUB values from small to large.

It should be understood that, in the embodiment of the present invention, the processor 520 may adopt a general-purpose Central Processing Unit (CPU), a microprocessor, an Application Specific Integrated Circuit (ASIC), or one or more Integrated circuits, for executing related programs to implement the technical solutions provided by the embodiments of the present invention. The technical solutions provided in the embodiments of the present invention have been described in detail in the above embodiments, and are not described herein again.

It is also to be appreciated that the communication interface 540 enables communication between the apparatus 500 and other devices or communication networks using transceiver means such as, but not limited to, transceivers.

The memory 510 may include both read-only memory and random-access memory, and provides instructions and data to the processor 520. A portion of processor 520 may also include non-volatile random access memory. For example, processor 520 may also store information of the device type.

The bus system 550 may include a power bus, a control bus, a status signal bus, and the like, in addition to a data bus. For clarity of illustration, however, the various buses are designated in the figure as bus system 550.

In implementation, the steps of the above method may be performed by integrated logic circuits of hardware or instructions in the form of software in the processor 520. The steps of the NVSRAM backup method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules in the processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in the memory 530, and the processor 520 reads the information in the memory 530 and performs the steps of the above method in combination with the hardware thereof. To avoid repetition, it is not described in detail here.

It should be understood that in the present embodiment, "B corresponding to a" means that B is associated with a, from which B can be determined. It should also be understood that determining B from a does not mean determining B from a alone, but may be determined from a and/or other information.

It should be understood that the term "and/or" herein is merely one type of association relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

It should be understood that, in various embodiments of the present invention, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A backup method of a nonvolatile static random access memory (NVSRAM), wherein the NVSRAM comprises an SRAM and a nonvolatile memory (NVM), the method comprising:

determining a last used bit RUB value corresponding to a cache block in the SRAM;

and backing up the data in the cache block of the SRAM to the NVM according to the sequence of the RUB values from small to large.

2. The method of claim 1, wherein before said backing up data in cache blocks of the SRAM into the NVM in order of RUB values from small to large, the method further comprises:

and backing up a dirty block in a cache block of the SRAM into the NVM.

3. The method of claim 1 or 2, wherein the method further comprises:

monitoring the electric quantity of a standby power supply of the SRAM in the data backup process of the SRAM;

and stopping the data backup process when the electric quantity of the standby power supply is less than or equal to a preset threshold value.

4. The method of claim 1 or 2, wherein the SRAM comprises a plurality of columns of cache lines, wherein each column of cache lines comprises one or more cache blocks,

the backing up the data in the cache block of the SRAM to the NVM according to the sequence of the RUB values from small to large comprises the following steps:

backing up the cache blocks with the RUB values i in the cache lines into the NVM column by column, determining whether all data in the SRAM are completely backed up, if not, repeatedly executing the step until all data in the SRAM are completely backed up or the electric quantity of a standby power supply of the SRAM is less than or equal to a preset threshold value, wherein i is an integer and the initial value of i is 0.

5. A backup device of a non-volatile static random access memory (NVSRAM), wherein the NVSRAM comprises an SRAM and a non-volatile memory (NVM), the device comprising:

a determining module, configured to determine a last used bit RUB value corresponding to a cache block in the SRAM;

and the backup module is used for backing up the data in the cache block of the SRAM to the NVM according to the sequence from small to large of the RUB value determined by the determination module.

6. The apparatus of claim 5, wherein the backup module is further to: and backing up a dirty block in a cache block of the SRAM into the NVM.

7. The apparatus of claim 5 or 6, wherein the apparatus further comprises:

the monitoring module is used for monitoring the electric quantity of a standby power supply of the SRAM in the data backup process of the SRAM;

and the control module is used for stopping the data backup process when the electric quantity of the standby power supply is less than or equal to a preset threshold value.

8. The apparatus of claim 5 or 6, wherein the SRAM comprises a plurality of columns of cache lines, wherein each column of cache lines comprises one or more cache blocks,

the backup module is specifically configured to: