CN107171697B - Passive ultrahigh frequency radio frequency identification tag with automatic impedance matching function - Google Patents
Passive ultrahigh frequency radio frequency identification tag with automatic impedance matching function Download PDFInfo
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- H04B5/77—
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2208—Supports; Mounting means by structural association with other equipment or articles associated with components used in interrogation type services, i.e. in systems for information exchange between an interrogator/reader and a tag/transponder, e.g. in Radio Frequency Identification [RFID] systems
- H01Q1/2225—Supports; Mounting means by structural association with other equipment or articles associated with components used in interrogation type services, i.e. in systems for information exchange between an interrogator/reader and a tag/transponder, e.g. in Radio Frequency Identification [RFID] systems used in active tags, i.e. provided with its own power source or in passive tags, i.e. deriving power from RF signal
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- H04B5/48—
Abstract
The invention relates to a passive ultrahigh frequency radio frequency identification tag with an automatic impedance matching function, which comprises an automatic impedance matching network and a passive ultrahigh frequency radio frequency identification tag, wherein the automatic impedance matching network is used for adjusting the overall impedance of the passive ultrahigh frequency radio frequency identification tag by detecting the local voltage of the passive ultrahigh frequency radio frequency identification tag so as to match the overall impedance of the passive ultrahigh frequency radio frequency identification tag with the impedance of an antenna; and the passive ultrahigh frequency radio frequency identification tag is used for acquiring the maximum energy from the antenna based on impedance matching and completing the radio frequency identification of the energy. The impedance adjustment is carried out at the chip end of the passive ultrahigh frequency radio frequency identification tag, so that the impedance of the tag circuit can be dynamically adjusted in a larger frequency range and different circuit working states and working distances when the working states and the working distances are changed, the load impedance of the tag and the internal impedance of the antenna are matched with each other, the maximum power collection is realized, and the working distances of the tag in different working states are further improved.
Description
Technical Field
The invention relates to the field of passive ultrahigh frequency radio frequency identification tags, in particular to a passive ultrahigh frequency radio frequency identification tag with an automatic impedance matching function.
Background
Radio Frequency Identification (RFID) technology, which enables contactless information transfer by Radio Frequency signal coupling and identifies an object according to the transferred information, has been popular in the 90 s of the 20 th century.
According to different working frequency bands of the tags, the RFID tags can be classified into microwave frequency band (MW) tags, Ultra High Frequency (UHF) tags, High Frequency (HF) tags, Low Frequency (LF) tags, and the like. The label working between 860MHz and 960MHz frequency is called ultra high frequency label, is a hot spot of the current RFID industry development, and has the advantages of long communication distance, high communication speed, low cost and the like.
RFID tags can be classified into three types, passive, semi-active, and active tags, according to the manner of power supply. The semi-active tag and the active tag are provided with internal power supplies, and the antenna receiving end of the semi-active tag and the active tag has higher receiving sensitivity and can realize long-distance (10-20 meters) communication. The passive tag needs to collect the radio frequency energy sent by the reader and convert the radio frequency energy into direct current energy to supply power to an internal circuit, so that the communication distance of the passive tag is directly related to the energy conversion efficiency of the passive tag. Three kinds of tags have characteristics, but passive tags have great advantages in cost and volume, so the passive tags are mainly discussed in the application.
The passive ultrahigh frequency radio frequency identification tag has the working frequency of 860 MHz-960 MHz, and weak radio frequency signals obtained by an antenna are converted into a direct current power supply by a voltage doubling rectifying circuit in a radio frequency front end. Since the input end of the voltage-doubling rectifying circuit is usually connected with a capacitor in parallel or in series, the impedance of the voltage-doubling rectifying circuit is related to the frequency; when the output power of the voltage-multiplying rectifying circuit is changed, the voltage output by the voltage-multiplying rectifying circuit is changed, the working state of an MOSFET in the voltage-multiplying rectifying circuit is also changed, impedance change is caused, matching between the antenna and the chip is changed, only when the input impedance of the chip is well matched with the tag antenna, more radio frequency energy is input into the chip, and meanwhile, enough input voltage can be generated at the input port of the chip.
Currently, commercial UHF RFID tags adjust the impedance matching between the antenna and the chip by fine-tuning the shape of the antenna. However, in actual operation of the tag, the operating state of the tag changes, and the impedance at the tag end changes. The method of impedance matching by adjusting the shape of the antenna cannot achieve the best matching in the actual working state; however, no method for adjusting impedance at the chip end of the tag has been reported at present.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a passive ultrahigh frequency radio frequency identification tag with an automatic impedance matching function, which can adjust the impedance at the chip end of the tag.
The technical scheme for solving the technical problems is as follows: a passive ultrahigh frequency radio frequency identification tag with an automatic impedance matching function comprises an automatic impedance matching network and a passive ultrahigh frequency radio frequency identification tag,
the automatic impedance matching network is used for adjusting the overall impedance of the passive ultrahigh frequency radio frequency identification tag by detecting the local voltage of the passive ultrahigh frequency radio frequency identification tag so as to match the overall impedance of the passive ultrahigh frequency radio frequency identification tag with the impedance of an antenna;
the passive ultrahigh frequency radio frequency identification tag is used for acquiring the maximum energy from an antenna based on impedance matching and completing radio frequency identification of the energy.
The invention has the beneficial effects that: the invention carries out impedance adjustment at the chip end of the passive ultrahigh frequency radio frequency identification tag, can dynamically adjust the overall impedance of the passive ultrahigh frequency radio frequency identification tag when the frequency range is larger and different circuit working states and working distances are changed, so that the load impedance of the passive ultrahigh frequency radio frequency identification tag is matched with the internal impedance of the antenna, the maximum power collection is realized, and the working distances of the passive ultrahigh frequency radio frequency identification tag in different working states are further improved.
On the basis of the technical scheme, the invention can be further improved as follows.
Further, the automatic impedance matching network comprises a sampling comparison unit, a logic algorithm control unit and an adjustable impedance matching unit, wherein the adjustable impedance matching unit comprises an adjustable capacitor array;
the sampling comparison unit is used for continuously sampling the voltage output by the passive ultrahigh frequency radio frequency identification tag twice under the control of the logic control unit and comparing the voltages sampled twice continuously;
the logic algorithm control unit is used for adjusting the number of the adjustable capacitor arrays merged into the adjustable impedance matching unit according to the comparison result of the voltages sampled twice continuously;
the adjustable impedance matching unit is used for matching impedance between the antenna and the passive ultrahigh frequency radio frequency identification tag according to the number of the incorporated adjustable capacitor arrays.
Further, the automatic impedance matching network also comprises an auxiliary voltage-multiplying rectifying unit and a low starting voltage oscillator,
the auxiliary voltage-multiplying rectifying unit is used for converting an RF signal which is transmitted by an antenna and passes through the adjustable impedance matching unit into DC direct-current power supply voltage;
the low starting voltage oscillator is used for providing a clock signal for the logic algorithm control unit under the driving of the auxiliary voltage-multiplying rectifying unit.
Further, the automatic impedance matching network further comprises a delay unit, and the delay unit is used for controlling the work rhythm of the sampling comparison unit under the control of the logic algorithm control unit.
Further, the passive UHF RFID tag comprises a radio frequency analog front end, a digital baseband and an EEPROM,
the radio frequency analog front end is used for converting an RF signal which is transmitted by an antenna and passes through the adjustable impedance matching unit into DC (direct current) power supply voltage, processing the DC power supply voltage to supply power to the digital baseband and the EEPROM, receiving the RF signal transmitted by the antenna, demodulating the RF signal transmitted by the antenna to generate a baseband signal, and transmitting the baseband signal to the digital baseband;
the digital baseband is used for carrying out command analysis on the baseband signal to generate a corresponding instruction and a corresponding parameter;
the EEPROM is used for providing corresponding data read-write operation for the digital baseband according to the instruction and the parameter and returning corresponding read-write operation data to the digital baseband according to the instruction and the parameter;
the digital baseband is also used for transmitting the read-write operation data returned by the EEPROM and/or the internal data of the digital baseband to a radio frequency analog front end;
the radio frequency analog front end is also used for modulating the read-write operation data and/or the internal data of the digital baseband transmitted by the digital baseband and sending the modulated read-write operation data and/or the internal data of the digital baseband to an antenna.
Further, the radio frequency analog front end comprises a rectifying circuit, an energy storage capacitor Cp, a three-rail voltage stabilizing circuit, a modulation and demodulation circuit, a reference circuit, a reset circuit, a clock circuit and a voltage doubling circuit;
the input end of the rectifying circuit is connected to the output end of the adjustable impedance matching unit, and the output end of the rectifying circuit is connected with the input end of the sampling comparison unit;
one end of the energy storage capacitor Cp is connected to the output end of the rectifying circuit and forms a Vrect output end together with the output end of the rectifying circuit, and the other end of the energy storage capacitor Cp is grounded;
the input end of the three-rail voltage stabilizing circuit is connected to the output end of the rectifying circuit, the output end of the three-rail voltage stabilizing circuit comprises a VDD voltage stabilizing output end, a Vosc voltage stabilizing output end and a VEE voltage stabilizing output end, the VDD voltage stabilizing output end of the three-rail voltage stabilizing circuit is respectively connected with the digital baseband and the EEPROM, and the VEE voltage stabilizing output end of the three-rail voltage stabilizing circuit is connected with the EEPROM;
the modulation and demodulation circuit comprises a VDD starting end, an ANT end communicated with the antenna, a Mode end and a Demode end communicated with the digital baseband, wherein the VDD starting end of the modulation and demodulation circuit is connected to the VDD voltage stabilizing output end of the three-rail voltage stabilizing circuit, the ANT end of the modulation and demodulation circuit is connected to the antenna, and the Mode end and the Demode end of the modulation and demodulation circuit are respectively connected with the digital baseband;
the input end of the reference circuit is connected to the Vrect output end, the output end of the reference circuit comprises a Vref output end and a Bias output end, the Vref output end and the Bias output end of the reference circuit are respectively connected with the input end of the Reset circuit, the Vref output end and the Bias output end of the reference circuit are also respectively connected with the three-rail voltage stabilizing circuit, the Reset circuit further comprises a VDD starting end and a Reset output end, the VDD starting end of the Reset circuit is connected with the VDD voltage stabilizing output end of the three-rail voltage stabilizing circuit, and the Reset output end of the Reset circuit is connected with the digital baseband;
the input end of the clock circuit is respectively connected to the Vosc output end of the three-rail voltage stabilizing circuit and the Bias output end of the reference circuit, the output end of the clock circuit is a CLK output end, and the CLK output end of the clock circuit is respectively connected with the digital baseband and the EEPROM;
the input end of the voltage doubling circuit is respectively connected to the CLK output end of the clock circuit, the Vref output end of the reference circuit and the VDD output end of the three-rail voltage stabilizing circuit, the output end of the voltage doubling circuit is a VDD2 output end, and the VDD2 output end of the voltage doubling circuit is connected with the EEPROM.
Further, the EEPROM comprises a digital synchronous control logic circuit, a charge pump, a reading circuit, a voltage conversion switch and an EE _ cell array,
the digital synchronous control logic circuit comprises a VDD starting end, a Read input end, a Write input end, a HV _ en output end, an R/W output end and a CLKR output end, wherein the VDD starting end of the digital synchronous control logic circuit is connected to the VDD output end of the three-rail voltage stabilizing circuit, and the Read input end and the Write input end of the digital synchronous control logic circuit are connected with the digital baseband;
the input end of the charge pump is respectively connected with the HV _ en output end of the digital synchronous control logic circuit, the VEE output end of the three-rail voltage stabilizing circuit and the CLK output end of the clock circuit, and the output end of the charge pump is a Vpp output end;
the starting end of the reading circuit is respectively connected to the CLKR output end of the digital synchronous control logic circuit and the VDD output end of the three-rail voltage stabilizing circuit, and the reading circuit is also respectively communicated with the digital baseband and the voltage conversion switch;
the starting ends of the voltage transfer switches are respectively connected to the VDD output end of the three-rail voltage stabilizing circuit, the VDD2 output end of the voltage doubling circuit, the Vpp output end of the charge pump and the R/W output end of the digital synchronous control logic circuit, and the voltage transfer switches are respectively communicated with the EE _ cell array and the digital baseband;
the EE _ cell array communicates with the digital baseband through a decoding driving circuit.
Furthermore, the digital baseband is also used for interacting with a clock circuit in the radio frequency analog front end to finish the frequency calibration of the clock circuit.
Drawings
FIG. 1 is a block diagram of the overall structure of a passive UHF RFID tag with automatic impedance matching according to the present invention;
FIG. 2 is a circuit diagram of a specific structure of a passive UHF RFID tag with an automatic impedance matching function according to the present invention;
FIG. 3 is a specific circuit diagram of an adjustable impedance matching unit in a passive UHF RFID tag with an automatic impedance matching function according to the present invention;
fig. 4 is a specific circuit diagram of a sample-and-hold circuit in a passive uhf rfid tag having an automatic impedance matching function according to the present invention.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.
As shown in fig. 1, a passive uhf rfid tag with an automatic impedance matching function includes an automatic impedance matching network and a passive uhf rfid tag, where the automatic impedance matching network is configured to adjust the overall impedance of the passive uhf rfid tag by detecting a local voltage of the passive uhf rfid tag, so that the overall impedance of the passive uhf rfid tag matches the impedance of an antenna; the passive ultrahigh frequency radio frequency identification tag is used for acquiring the maximum energy from an antenna based on impedance matching and completing radio frequency identification of the energy. The passive ultrahigh frequency radio frequency identification tag with the automatic impedance matching function performs impedance adjustment at the chip end of the tag, can dynamically adjust the impedance of a tag circuit in a large frequency range and different circuit working states and when the working distance is changed, enables the load impedance of the tag and the internal impedance of an antenna to be matched with each other, realizes maximum power collection, and accordingly improves the working distance of the tag in different working states.
In this embodiment, a specific structural circuit of a passive uhf rfid tag with an automatic impedance matching function is shown in fig. 2, and includes the automatic impedance matching network and the passive uhf rfid tag, where the passive uhf rfid tag includes a radio frequency analog front end, a digital baseband, and an EEPROM.
The automatic impedance matching network comprises a sampling comparison unit, a logic algorithm control unit and an adjustable impedance matching unit, wherein the adjustable impedance matching unit comprises an adjustable capacitor array; the sampling comparison unit is used for continuously sampling the voltage output by the passive ultrahigh frequency radio frequency identification tag twice under the control of the logic control unit and comparing the voltages sampled twice continuously; the logic algorithm control unit is used for adjusting the number of the adjustable capacitor arrays merged into the adjustable impedance matching unit according to the comparison result of the voltages sampled twice continuously; the adjustable impedance matching unit is used for matching impedance between the antenna and the passive ultrahigh frequency radio frequency identification tag according to the number of the incorporated adjustable capacitor arrays. The automatic impedance matching network also comprises an auxiliary voltage-multiplying rectifying unit and a low starting voltage oscillator, wherein the auxiliary voltage-multiplying rectifying unit is used for converting an RF signal which is transmitted by an antenna and passes through the adjustable impedance matching unit into DC direct-current power supply voltage; the low starting voltage oscillator is used for providing a clock signal for the logic algorithm control unit under the driving of the auxiliary voltage-multiplying rectifying unit. The automatic impedance matching network also comprises a time delay unit, and the time delay unit is used for controlling the work rhythm of the sampling comparison unit under the control of the logic algorithm control unit. The sampling comparison unit comprises a sampling hold circuit and a comparator, and the delay unit comprises a first signal delay buffer and a second signal delay buffer. In this embodiment, a specific circuit structure of the adjustable impedance matching unit and the sample-and-hold circuit of the automatic impedance matching network is shown in fig. 3 and fig. 4, respectively.
In the passive ultrahigh frequency radio frequency identification tag, the radio frequency analog front end is used for converting an RF signal which is transmitted by an antenna and passes through the adjustable impedance matching unit into DC direct-current power supply voltage, processing the DC direct-current power supply voltage to supply power to the digital baseband and the EEPROM, receiving the RF signal transmitted by the antenna, demodulating the RF signal transmitted by the antenna to generate a baseband signal, and transmitting the baseband signal to the digital baseband; the digital baseband is used for carrying out command analysis on the baseband signal to generate a corresponding instruction and a corresponding parameter; the EEPROM is used for providing corresponding data read-write operation for the digital baseband according to the instruction and the parameter and returning corresponding read-write operation data to the digital baseband according to the instruction and the parameter; the digital baseband is also used for transmitting the read-write operation data returned by the EEPROM and/or the internal data of the digital baseband to a radio frequency analog front end; the radio frequency analog front end is also used for modulating the read-write operation data and/or the internal data of the digital baseband transmitted by the digital baseband and sending the modulated read-write operation data and/or the internal data of the digital baseband to an antenna.
Specifically, as shown in fig. 2, the radio frequency analog front end includes a rectifying circuit, an energy storage capacitor Cp, a three-rail voltage stabilizing circuit, a modulating and demodulating circuit, a reference circuit, a reset circuit, a clock circuit, and a voltage doubling circuit; the input end of the rectifying circuit is connected to the output end of the adjustable impedance matching unit, and the output end of the rectifying circuit is connected with the input end of the sampling comparison unit; one end of the energy storage capacitor Cp is connected to the output end of the rectifying circuit and forms a Vrect output end together with the output end of the rectifying circuit, and the other end of the energy storage capacitor Cp is grounded; the input end of the three-rail voltage stabilizing circuit is connected to the output end of the rectifying circuit, the output end of the three-rail voltage stabilizing circuit comprises a VDD voltage stabilizing output end, a Vosc voltage stabilizing output end and a VEE voltage stabilizing output end (the three-rail voltage stabilizing circuit consists of the VDD voltage stabilizing circuit, the Vosc voltage stabilizing circuit and the VEE voltage stabilizing circuit), the VDD voltage stabilizing output end of the three-rail voltage stabilizing circuit is respectively connected with the digital baseband and the EEPROM, and the VEE voltage stabilizing output end of the three-rail voltage stabilizing circuit is connected with the EEPROM; the modulation and demodulation circuit comprises a VDD starting end, an ANT end communicated with the antenna, a Mode end and a Demode end communicated with the digital baseband, wherein the VDD starting end of the modulation and demodulation circuit is connected to the VDD voltage stabilizing output end of the three-rail voltage stabilizing circuit, the ANT end of the modulation and demodulation circuit is connected to the antenna, and the Mode end and the Demode end of the modulation and demodulation circuit are respectively connected with the digital baseband; the input end of the reference circuit is connected to the Vrect output end, the output end of the reference circuit comprises a Vref output end and a Bias output end, the Vref output end and the Bias output end of the reference circuit are respectively connected with the input end of the Reset circuit, the Vref output end and the Bias output end of the reference circuit are also respectively connected with the three-rail voltage stabilizing circuit, the Reset circuit further comprises a VDD starting end and a Reset output end, the VDD starting end of the Reset circuit is connected with the VDD voltage stabilizing output end of the three-rail voltage stabilizing circuit, and the Reset output end of the Reset circuit is connected with the digital baseband; the input end of the clock circuit is respectively connected to the Vosc output end of the three-rail voltage stabilizing circuit and the Bias output end of the reference circuit, the output end of the clock circuit is a CLK output end, and the CLK output end of the clock circuit is respectively connected with the digital baseband and the EEPROM; the input end of the voltage doubling circuit is respectively connected to the CLK output end of the clock circuit, the Vref output end of the reference circuit and the VDD output end of the three-rail voltage stabilizing circuit, the output end of the voltage doubling circuit is a VDD2 output end, and the VDD2 output end of the voltage doubling circuit is connected with the EEPROM.
Specifically, as shown in fig. 2, the EEPROM includes a digital synchronous control logic circuit, a charge pump, a Read circuit, a voltage converting switch, and an EE _ cell array, the digital synchronous control logic circuit includes a VDD enable terminal, a Read input terminal, a Write input terminal, a HV _ en output terminal, an R/W output terminal, and a CLKR output terminal, the VDD enable terminal of the digital synchronous control logic circuit is connected to the VDD output terminal of the three-rail voltage stabilizing circuit, and the Read input terminal and the Write input terminal of the digital synchronous control logic circuit are connected to the digital baseband; the input end of the charge pump is respectively connected with the HV _ en output end of the digital synchronous control logic circuit, the VEE output end of the three-rail voltage stabilizing circuit and the CLK output end of the clock circuit, and the output end of the charge pump is a Vpp output end; the starting end of the reading circuit is respectively connected to the CLKR output end of the digital synchronous control logic circuit and the VDD output end of the three-rail voltage stabilizing circuit, and the reading circuit is also respectively communicated with the digital baseband and the voltage conversion switch; the starting ends of the voltage transfer switches are respectively connected to the VDD output end of the three-rail voltage stabilizing circuit, the VDD2 output end of the voltage doubling circuit, the Vpp output end of the charge pump and the R/W output end of the digital synchronous control logic circuit, and the voltage transfer switches are respectively communicated with the EE _ cell array and the digital baseband; the EE _ cell array communicates with the digital baseband through a decoding driving circuit.
Specifically, as shown in fig. 2, the digital baseband is a core processing module of the passive uhf rfid tag, is a carrier for a specific communication protocol and EEPROM control, and is composed of 8 units: the device comprises an initialization unit, a decoding unit, a state machine unit, a command analysis unit, an EEPROM control unit, a random number generation unit, a power consumption management unit and an output control unit, wherein the units respectively correspond to different processes or different functions in data processing of a digital baseband. The initialization unit completes initialization of the passive ultrahigh frequency radio frequency identification tag and loading of initialization information of the passive ultrahigh frequency radio frequency identification tag; the decoding unit decodes the demodulation signal transmitted from the radio frequency analog front end according to the specified data coding mode and outputs the demodulation signal to the command analysis unit, and the decoding unit is also responsible for interacting with a clock generation circuit in the radio frequency analog front end to finish the frequency calibration function of the clock circuit; the command analysis unit is used for analyzing the decoded demodulation signal to obtain a specific command and parameters thereof and transmitting the analysis result to the state machine unit, the output control unit and the EEPROM control unit; the state machine unit completes the skipping of the passive ultrahigh frequency radio frequency identification tag state and the overturning of the inventory mark according to the analyzed command and parameter; the output control unit reads and writes the memory bank through the EEPROM control unit according to the analyzed command and parameters and the information of the state machine, prepares data needing to be returned to the radio frequency analog front end, and outputs the data through FM0 or Miller coding; the EEPROM control unit is an interface channel between the digital baseband and the EEPROM and provides a control signal for reading and writing the EEPROM by the digital baseband, the EEPROM control unit receives signals from the initialization unit, the command analysis unit and the output control unit, the initialization unit loads initialization data from the EEPROM by using the EEPROM control unit, and command content analyzed by the command analysis unit can be used for generating address information required by read-write operation for the EEPROM control unit; the random number generating unit generates a 16bits random or pseudo random number (RN16) used in the interaction process of the passive UHF radio frequency identification tag and the reader. And the power consumption management unit completes the optimization of the global power consumption of the digital baseband according to the working period and the state jump of the passive ultrahigh frequency radio frequency identification tag.
The operation of the present invention will be explained with reference to the circuit configuration shown in fig. 2.
The overall working principle is as follows: in the present invention, the antenna and the automatic impedance matching network work together to receive the radio frequency signal (RF signal) to the maximum possible and provide it to the radio frequency analog front end; the radio frequency analog front end is responsible for converting received RF signals into starting voltage, data, clock, RESET signals and the like required by the work of the whole passive ultrahigh frequency radio frequency identification tag. The EPPROM and the digital baseband are used for realizing a specific communication protocol of the passive ultrahigh frequency radio frequency identification tag and processing data, feedback data is obtained after the data processing is finished, and the feedback data is returned to the radio frequency analog front end to be sent, and the main work of the EPPROM and the digital baseband comprises decoding and encoding of communication data, processing of data, storage of data and the like.
The working principle of each module is described as follows:
the automatic impedance matching network in the invention enables the antenna and the passive ultrahigh frequency radio frequency identification tag to achieve better matching by automatically adjusting the internal impedance, and reduces the loss of radio frequency signals from the antenna to the radio frequency analog front end. The RF signal transmitted from the antenna firstly enters the automatic impedance matching network, the adjustable impedance matching unit is specifically used for adjusting the voltage between the antenna and the auxiliary voltage-multiplying rectifying unit and between the antenna and a rectifying circuit in the radio frequency analog front end, so that the auxiliary voltage-multiplying rectifying unit and the rectifying circuit fully absorb and utilize the radio frequency energy sensed on the antenna, and an adjustable capacitor array in the adjustable impedance matching unit can be controlled by the logic algorithm control unit to be adjusted. The auxiliary voltage-multiplying rectifying unit can convert the obtained RF signal into DC (direct current) power supply voltage to supply power for other circuits in the automatic impedance matching network, the DC power supply voltage is not required, and the larger the energy of the input RF signal is, the larger the DC energy is provided. The low starting voltage oscillator can normally work to generate a clock signal required by the logic algorithm control unit when the power supply voltage is very low, and the power supply voltage of the low starting voltage oscillator is provided by the auxiliary voltage-multiplying rectifying unit. The logic algorithm control unit is used for dynamically controlling and adjusting the adjustable capacitor array in the adjustable impedance matching unit, executing a specific impedance matching algorithm according to a Comp signal fed back by the comparator, and controlling the adjustable impedance matching unit by the algorithm to achieve the purpose of optimizing the matching performance of the adjustable impedance matching unit. In addition, the logic algorithm control unit needs to control the action rhythm of the sample-and-hold circuit and the comparator to complete the judgment of whether the matching characteristic becomes good before and after the adjustable impedance matching network is adjusted once, and the judgment result is the Comp signal. The sampling and holding circuit is used for sampling DC (direct current) voltage generated by the analog radio frequency front-end rectifying circuit, respectively sampling and holding voltages output by the rectifying circuit before and after primary regulation, and supplying the sampled and held voltages to the comparator for judgment. Because the rectification circuits before and after primary adjustment have different matching and different input RF energy, the output DC voltage is different, the output voltage is higher when the matching is better after adjustment, and the output voltage is lower when the matching is worse, so the voltages before and after adjustment sampled by the sampling and holding circuit are different. The comparator compares the voltages before and after the first adjustment obtained from the sample-and-hold circuit, determines that the matching is good or bad, and generates a Comp signal. The first signal delay buffer and the second signal delay buffer in the automatic impedance matching network are used for assisting the logic algorithm control unit to complete the control of the working rhythm of the comparator and the sampling holding circuit. The first signal delay buffer and the second signal delay buffer have the overall function of enabling the sample-and-hold circuit to complete the work first and then enabling the comparator to work. The working process of the automatic impedance matching network is that an antenna receives RF energy and then enters an auxiliary voltage-multiplying rectifying unit and a radio frequency analog front end through an adjustable impedance matching unit, the auxiliary voltage-multiplying rectifying unit generates circuit working voltage, a low starting voltage oscillator starts to work to output clock signals, then a logic algorithm control unit controls a sample and hold circuit to sample the voltage output by a rectifying circuit in the radio frequency analog front end, the logic algorithm control unit controls the adjustable impedance matching unit to adjust impedance after sampling is finished, controls the sample and hold circuit to sample the voltage output by the rectifying circuit in the radio frequency analog front end again, then controls a comparator to compare the voltage before and after once adjustment of the sample and hold circuit, and the comparison result is used as a feedback signal to guide the logic algorithm control unit to adjust the impedance of the adjustable impedance matching unit to the best effect.
In the field of radio frequency identification, a reader is required to be used for communicating with a passive ultrahigh frequency radio frequency identification tag to acquire or modify data in the passive ultrahigh frequency radio frequency identification tag; the reader transmits carrier waves and modulated data to the passive ultrahigh frequency radio frequency identification tag by using the antenna, provides energy for the passive ultrahigh frequency radio frequency identification tag and transmits the data to the passive ultrahigh frequency radio frequency identification tag, and the reader receives and demodulates the data reflected by the passive ultrahigh frequency radio frequency identification tag through the antenna.
After an RF signal transmitted by the antenna enters a radio frequency analog front end through an automatic impedance matching network, the specific function realization part of the RFID system is related. The radio frequency analog front end part is the most basic part in the passive ultrahigh frequency radio frequency identification tag, and supports the normal operation of the EEROM and the digital baseband. In the radio frequency analog front end, a rectifying circuit is a total power supply voltage source of the whole passive ultrahigh frequency radio frequency identification tag, a three-rail voltage stabilizing circuit generates stable power supply voltage for the radio frequency analog front end, an EEROM and a digital baseband, and a reference circuit provides bias current and reference voltage with zero temperature coefficient for the interior of the radio frequency analog front end. The modulation and demodulation circuit is mainly used for demodulating a modulation signal from the reader to the passive ultrahigh frequency radio frequency identification tag, sending the demodulation signal to the digital baseband for command analysis, modulating data sent back by the digital baseband and then feeding back to the reader through an antenna, and reflecting the data to be sent back to the reader by the modulation and demodulation circuit in an impedance changing mode; the clock circuit is mainly used for providing stable clock signals for the EEPROM and the digital baseband and simultaneously serving as a driving clock of the charge pump. The reset circuit is used for generating a reset signal when the chip is powered on, providing the reset signal to the digital baseband and resetting the digital baseband to an initial state. The voltage doubler circuit is used to generate the required specific voltage for the EEPROM.
The EEPROM mainly provides data nonvolatile storage service for the RFID, wherein the data nonvolatile storage service comprises storage area content specified in an RFID protocol, the digital synchronous control logic circuit is a control circuit for EEPROM IP work, and the digital synchronous control logic circuit is mainly used for receiving an instruction sent by a digital baseband, sending a more specific operation instruction to each functional module after analyzing the instruction, and coordinating each functional module to complete read/write operation; the reading circuit is a core module realized by reading operation and can read out 16-bit data in parallel at one time; the decoding driving circuit is used for decoding an address and driving a selected storage unit needing to be operated after decoding; the voltage transfer switch enables the EE _ cell array working voltage to be switched between a reading operation working voltage and an erasing and programming operation working voltage, and provides correct working voltage for the EE _ cell array according to different reading and writing operations; the main function of the charge pump is to pump out the high voltage required for EE cell array rewriting.
In the passive uhf rfid tag having an automatic impedance matching function of the present invention,
the automatic impedance matching network comprises an auxiliary voltage-multiplying rectifying unit (namely an independent auxiliary charge pump) to realize energy conversion and independently supply power to the automatic impedance matching network; the radio frequency analog front end, the digital baseband and the EEPROM are powered by a rectifying circuit contained in the radio frequency analog front end; that is to say, the power supply of the automatic impedance matching network and the passive ultrahigh frequency radio frequency identification tag is not affected, and the auxiliary voltage doubling rectifying unit in the automatic impedance matching network works before the radio frequency analog front end starts to work, so that the requirement of the passive ultrahigh frequency radio frequency identification tag protocol is not affected.
The automatic impedance matching network detects the change of the output voltage of the rectifying circuit in the radio frequency analog front end, and then adjusts the whole impedance of the passive ultrahigh frequency radio frequency identification tag instead of the impedance of the radio frequency analog front end, so that the energy efficiency obtained by the whole passive ultrahigh frequency radio frequency identification tag is the highest.
The passive ultrahigh frequency radio frequency identification tag with the automatic impedance matching function has the following advantages:
1. the additionally added automatic impedance matching network has extremely low power consumption, so that the overall power consumption of the passive ultrahigh frequency radio frequency identification tag cannot be obviously improved;
2. the automatic impedance matching network comprises an auxiliary voltage-multiplying rectifying unit which is specially used for supplying power to the automatic impedance matching network; the passive ultrahigh frequency radio frequency identification tag is powered by a rectifying circuit at the radio frequency analog front end, and the passive ultrahigh frequency radio frequency identification tag and the radio frequency analog front end are connected to an antenna at the same time and are not mutually influenced;
3. the automatic impedance matching network is higher in power-on speed and is started before other parts start working, so that the effect of real-time dynamic adjustment can be achieved;
4. the invention can use the standard CMOS process, realize the full integration, reduce the production cost;
5. the automatic impedance matching network detects the output voltage of the radio frequency analog front-end rectifying circuit and adjusts the integral impedance of the passive ultrahigh frequency radio frequency identification tag, so that the integral optimal impedance can be obtained, and the integral impedance matching effect is optimal.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (5)
1. A passive ultrahigh frequency radio frequency identification tag with an automatic impedance matching function is characterized in that: comprises an automatic impedance matching network and a passive ultrahigh frequency radio frequency identification tag,
the automatic impedance matching network is used for adjusting the overall impedance of the passive ultrahigh frequency radio frequency identification tag by detecting the local voltage of the passive ultrahigh frequency radio frequency identification tag so as to match the overall impedance of the passive ultrahigh frequency radio frequency identification tag with the impedance of an antenna;
the passive ultrahigh frequency radio frequency identification tag is used for acquiring the maximum energy from an antenna based on impedance matching and completing radio frequency identification of the energy;
the automatic impedance matching network comprises a sampling comparison unit, a logic algorithm control unit and an adjustable impedance matching unit, wherein the adjustable impedance matching unit comprises an adjustable capacitor array;
the sampling comparison unit is used for continuously sampling the voltage output by the passive ultrahigh frequency radio frequency identification tag twice under the control of the logic algorithm control unit and comparing the voltages sampled twice continuously;
the logic algorithm control unit is used for adjusting the number of the adjustable capacitor arrays merged into the adjustable impedance matching unit according to the comparison result of the voltages sampled twice continuously;
the adjustable impedance matching unit is used for matching the impedance between the antenna and the passive ultrahigh frequency radio frequency identification tag according to the number of the incorporated adjustable capacitor arrays;
the automatic impedance matching network also comprises an auxiliary voltage-multiplying rectifying unit and a low starting voltage oscillator;
the auxiliary voltage-multiplying rectifying unit is used for converting an RF signal which is transmitted by an antenna and passes through the adjustable impedance matching unit into DC direct-current power supply voltage;
the low starting voltage oscillator is used for providing a clock signal for the logic algorithm control unit under the driving of the auxiliary voltage-multiplying rectifying unit;
the automatic impedance matching network also comprises a time delay unit, and the time delay unit is used for controlling the work rhythm of the sampling comparison unit under the control of the logic algorithm control unit.
2. The passive UHF RFID tag of claim 1, wherein the tag comprises: the passive ultrahigh frequency radio frequency identification tag comprises a radio frequency analog front end, a digital baseband and an EEPROM,
the radio frequency analog front end is used for converting an RF signal which is transmitted by an antenna and passes through the adjustable impedance matching unit into DC (direct current) power supply voltage, processing the DC power supply voltage to supply power to the digital baseband and the EEPROM, receiving the RF signal transmitted by the antenna, demodulating the RF signal transmitted by the antenna to generate a baseband signal, and transmitting the baseband signal to the digital baseband;
the digital baseband is used for carrying out command analysis on the baseband signal to generate a corresponding instruction and a corresponding parameter;
the EEPROM is used for providing corresponding data read-write operation for the digital baseband according to the instruction and the parameter and returning corresponding read-write operation data to the digital baseband according to the instruction and the parameter;
the digital baseband is also used for transmitting the read-write operation data returned by the EEPROM and/or the internal data of the digital baseband to a radio frequency analog front end;
the radio frequency analog front end is also used for modulating the read-write operation data and/or the internal data of the digital baseband transmitted by the digital baseband and sending the modulated read-write operation data and/or the internal data of the digital baseband to an antenna.
3. The passive UHF RFID tag with automatic impedance matching of claim 2, wherein: the radio frequency analog front end comprises a rectifying circuit, an energy storage capacitor Cp, a three-rail voltage stabilizing circuit, a modulation and demodulation circuit, a reference circuit, a reset circuit, a clock circuit and a voltage doubling circuit;
the input end of the rectifying circuit is connected to the output end of the adjustable impedance matching unit, and the output end of the rectifying circuit is connected with the input end of the sampling comparison unit;
one end of the energy storage capacitor Cp is connected to the output end of the rectifying circuit and forms a Vrect output end together with the output end of the rectifying circuit, and the other end of the energy storage capacitor Cp is grounded;
the input end of the three-rail voltage stabilizing circuit is connected to the output end of the rectifying circuit, the output end of the three-rail voltage stabilizing circuit comprises a VDD voltage stabilizing output end, a Vosc voltage stabilizing output end and a VEE voltage stabilizing output end, the VDD voltage stabilizing output end of the three-rail voltage stabilizing circuit is respectively connected with the digital baseband and the EEPROM, and the VEE voltage stabilizing output end of the three-rail voltage stabilizing circuit is connected with the EEPROM;
the modulation and demodulation circuit comprises a VDD starting end, an ANT end communicated with the antenna, a Mode end and a Demode end communicated with the digital baseband, wherein the VDD starting end of the modulation and demodulation circuit is connected to the VDD voltage stabilizing output end of the three-rail voltage stabilizing circuit, the ANT end of the modulation and demodulation circuit is connected to the antenna, and the Mode end and the Demode end of the modulation and demodulation circuit are respectively connected with the digital baseband;
the input end of the reference circuit is connected to the Vrect output end, the output end of the reference circuit comprises a Vref output end and a Bias output end, the Vref output end and the Bias output end of the reference circuit are respectively connected with the input end of the Reset circuit, the Vref output end and the Bias output end of the reference circuit are also respectively connected with the three-rail voltage stabilizing circuit, the Reset circuit further comprises a VDD starting end and a Reset output end, the VDD starting end of the Reset circuit is connected with the VDD voltage stabilizing output end of the three-rail voltage stabilizing circuit, and the Reset output end of the Reset circuit is connected with the digital baseband;
the input end of the clock circuit is respectively connected to the Vosc output end of the three-rail voltage stabilizing circuit and the Bias output end of the reference circuit, the output end of the clock circuit is a CLK output end, and the CLK output end of the clock circuit is respectively connected with the digital baseband and the EEPROM;
the input end of the voltage doubling circuit is respectively connected to the CLK output end of the clock circuit, the Vref output end of the reference circuit and the VDD output end of the three-rail voltage stabilizing circuit, the output end of the voltage doubling circuit is a VDD2 output end, and the VDD2 output end of the voltage doubling circuit is connected with the EEPROM.
4. The passive UHF RFID tag with automatic impedance matching of claim 3, wherein: the EEPROM comprises a digital synchronous control logic circuit, a charge pump, a reading circuit, a voltage conversion switch and an EE _ cell array,
the digital synchronous control logic circuit comprises a VDD starting end, a Read input end, a Write input end, a HV _ en output end, an R/W output end and a CLKR output end, wherein the VDD starting end of the digital synchronous control logic circuit is connected to the VDD output end of the three-rail voltage stabilizing circuit, and the Read input end and the Write input end of the digital synchronous control logic circuit are connected with the digital baseband;
the input end of the charge pump is respectively connected with the HV _ en output end of the digital synchronous control logic circuit, the VEE output end of the three-rail voltage stabilizing circuit and the CLK output end of the clock circuit, and the output end of the charge pump is a Vpp output end;
the starting end of the reading circuit is respectively connected to the CLKR output end of the digital synchronous control logic circuit and the VDD output end of the three-rail voltage stabilizing circuit, and the reading circuit is also respectively communicated with the digital baseband and the voltage conversion switch;
the starting ends of the voltage transfer switches are respectively connected to the VDD output end of the three-rail voltage stabilizing circuit, the VDD2 output end of the voltage doubling circuit, the Vpp output end of the charge pump and the R/W output end of the digital synchronous control logic circuit, and the voltage transfer switches are respectively communicated with the EE _ cell array and the digital baseband;
the EE _ cell array communicates with the digital baseband through a decoding driving circuit.
5. The passive UHF RFID tag with automatic impedance matching function of claim 3 or 4, wherein: the digital baseband is also used for interacting with a clock circuit in the radio frequency analog front end to finish the frequency calibration of the clock circuit.
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| CN109450560B (en) * | 2018-09-25 | 2021-08-10 | 广州求远电子科技有限公司 | Detection system and detection method of low-frequency communication device and terminal equipment |
| CN109614836B (en) * | 2019-01-08 | 2023-10-20 | 快脉信息科技(上海)有限公司 | Vehicle positioning radio frequency identification system and positioning method thereof |
| CN111598202B (en) * | 2019-02-21 | 2023-11-17 | 华大半导体有限公司 | Passive electronic tag chip and memory read charge pump starting method thereof |
| JP7201509B2 (en) * | 2019-03-29 | 2023-01-10 | ラピスセミコンダクタ株式会社 | Passive RFID tags and RFID systems |
| CN110137678B (en) * | 2019-04-18 | 2021-05-18 | 宁波大学 | Voltage-multiplying type radio frequency rectification antenna |
| CN110751000A (en) * | 2019-09-24 | 2020-02-04 | 国网湖南省电力有限公司 | Verification test method and device for ultrahigh frequency RFID (radio frequency identification) tag |
| CN112686357B (en) * | 2019-10-17 | 2023-05-23 | 莫冰 | Ultrahigh frequency RFID tag and anti-electromagnetic interference module thereof |
| CN111275153A (en) * | 2020-01-15 | 2020-06-12 | 中国电力科学研究院有限公司 | UHF RFID chip supporting digital communication interface and application method thereof |
| CN111275147B (en) * | 2020-01-20 | 2021-05-11 | 中南大学 | RFID (radio frequency identification) tag sensing system and method without calibration |
| CN113507277B (en) * | 2021-06-02 | 2023-06-06 | 西安电子科技大学 | Collaborative matching and self-tuning system of radio frequency energy acquisition front end |
| CN113420861B (en) * | 2021-06-02 | 2023-02-07 | 西安电子科技大学 | Radio frequency passive tag capable of activating self-tuning for multiple times in real time and method |
| CN113408685B (en) * | 2021-06-02 | 2023-02-03 | 西安电子科技大学 | Radio frequency energy acquisition system based on energy management and passive radio frequency tag |
| CN113283565B (en) * | 2021-06-02 | 2024-01-26 | 上海宜链物联网有限公司 | Automatic tuning system and method for antenna impedance of RFID tag chip |
| CN113792833A (en) * | 2021-09-10 | 2021-12-14 | 厦门印天电子科技有限公司 | Impedance self-adjusting ISO15693 label reading-writing device and adjusting method thereof |
| CN114091640B (en) * | 2021-11-09 | 2024-02-09 | 上海坤锐电子科技有限公司 | Electronic tag and electronic tag system |
| CN115965037B (en) * | 2023-03-16 | 2023-05-30 | 深圳市明泰智能技术有限公司 | RF tag read-write system adaptive to environment change and data processing method |
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| KR100662615B1 (en) * | 2006-01-13 | 2007-01-02 | 삼성전자주식회사 | Apparatus for transforming of a signal and apparatus for rfid tag having the same and method of driving the rfid tag |
| CN105826994B (en) * | 2016-03-19 | 2018-11-13 | 复旦大学 | A kind of RF energy acquisition system based on dynamic impedance matching technology |
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