CN107171297A - A kind of method and system that protective relaying maloperation is made of preventing based on FPGA - Google Patents
A kind of method and system that protective relaying maloperation is made of preventing based on FPGA Download PDFInfo
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- CN107171297A CN107171297A CN201710352502.4A CN201710352502A CN107171297A CN 107171297 A CN107171297 A CN 107171297A CN 201710352502 A CN201710352502 A CN 201710352502A CN 107171297 A CN107171297 A CN 107171297A
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- fpga
- protection
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- signal
- relay
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/26—Sectionalised protection of cable or line systems, e.g. for disconnecting a section on which a short-circuit, earth fault, or arc discharge has occured
- H02H7/261—Sectionalised protection of cable or line systems, e.g. for disconnecting a section on which a short-circuit, earth fault, or arc discharge has occured involving signal transmission between at least two stations
- H02H7/262—Sectionalised protection of cable or line systems, e.g. for disconnecting a section on which a short-circuit, earth fault, or arc discharge has occured involving signal transmission between at least two stations involving transmissions of switching or blocking orders
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- Emergency Protection Circuit Devices (AREA)
Abstract
The invention provides a kind of method and system that protective relaying maloperation is made of preventing based on FPGA, cpu cycle property sends protection startup/outlet data to FPGA, when FPGA detect protection startup/outlet data it is effective when control startup/exit relay action；As FPGA, to detect protection exit status signal invalid, and detects protection startup/discharge state signal after the time that timing is not set persistently again effectively, control startup/exit relay action；Or when invalid, timing and after the time persistently set, control startup/exit relay is failure to actuate.Improve the accuracy of protection startup/outlet data and the reliability of relay protection action; and protection startup, outlet signal are directly sent by FPGA; no longer through exporting plug-in unit, the multiple layers transmission of data is reduced, the quick-action, reliability and correctness of relay protection is improved；And logic is simple periodically to be judged to protection data, cumbersome signal content parsing is eliminated, FPGA internal resources are saved.
Description
Technical field
It is more particularly to a kind of that relay is prevented based on FPGA the invention belongs to the relay protection automatic field of power engineering
The method and system of protection misoperation.
Background technology
In order to adapt to economy, social development requirement, reply Global climate change and the significant challenge that faces of power network are permitted
Many countries have carried out the research and practice of intelligent grid.Build intelligent substation turns into the inevitable choice of electric power industry development,
Climate change is responded actively to China, economic society sustained and rapid development is ensured, promotes energy structure optimizing and efficiently utilize, protect
Hinder supply of electric power safety, cultivate emerging strategic industries, drive related industry development significant.
The realization of intelligent substation is reliable correct to switch and disconnecting link safety progress by Intelligent protection measuring controller
Protection act and operation, realize the normal operation of power transmission and transforming equipment, so as to ensure the strong reliability service of whole network system.
In intelligent Substation System, the protection act of switch tool and operation be by Intelligent protection measuring controller inside startup and go out
The mouth actuating of relay is realized.At present, the mode of the trigger protection measure and control device actuating of relay, mainly by CPU through outside
Bus sends protection data to outlet plug-in unit, by plug-in unit transmission protection in outlet starts, outlet signal drives corresponding relay to move
Make.Due to factors such as CPU exceptions so that the protection data that outlet plug-in unit is received have certain uncertainty, so as to cause
Protect error starting, export by mistake, have a strong impact on the safe operation of network system.In order to farthest ensure the safety of operation of power networks
It is reliable to protect the correct method of data stabilization, it is necessary to develop one kind and realize.
Publication No. " CN102420462B ", the China of entitled " a kind of process-level smart terminal equipment of smart substation "
Patent document, intelligent terminal disclosed in the patent includes CPU, control FPGA module, outlet FPGA, and the patent is sent out CPU
The content sent is by two layers of FPGA verification, if CPU is abnormal, and endless loop sends the operation life to some switch tool always
Order, then after being verified by multiple FPGA, be consistent with the command context that CPU is sent, still result in protective relaying maloperation.
The content of the invention
It is an object of the invention to provide it is a kind of based on FPGA preventing protective relaying maloperation make method, for solve because
CPU causes protection error in data the problem of make protective relaying maloperation extremely, at the same additionally provide it is a kind of based on FPGA prevent after
The system of electric protection misoperation.
To achieve the above object, the technical scheme is that：
A kind of method that protective relaying maloperation is made of preventing based on FPGA, including the step of control starting relay：
CPU constantly sends protection log-on data to FPGA with the cycle set, and the protection log-on data includes protection
Starting state signal and protection, which start, performs signal；
When FPGA detects protection starting state signal effectively, by FPGA forwarding protection log-on datas, control starts relay
Device is acted；Starting state invalidating signal is protected when FPGA is detected, and detects guarantor after the time that timing is not set persistently again
Protect starting state signal effectively, then by FPGA forwarding protection log-on datas, control starting relay action；Or when FPGA detections
To protection starting state invalidating signal, timing and after the time persistently set, control starting relay is failure to actuate.
Further, in addition to control exit relay the step of：
CPU constantly sends protection exit data to FPGA with the cycle set, and the protection exit data include protection
Discharge state signal and protection exit perform signal；
When FPGA detects protection exit status signal effectively, by FPGA forwarding protection outlet datas, control outlet relay
Device is acted；As FPGA, to detect protection exit status signal invalid, and detects guarantor after the time that timing is not set persistently again
Protect discharge state signal effectively, then by FPGA forwarding protection outlet datas, control exit relay action；Or when FPGA detections
Invalid to protection exit status signal, timing and after the time persistently set, control exit relay is failure to actuate.
Further, the first monostable flipflop is formed by the FPGA, to judge to protect starting state signal, and entered
Row timing.
Further, the second monostable flipflop is formed by the FPGA, to judge protection exit status signal, and entered
Row timing.
Present invention also offers it is a kind of based on FPGA preventing protective relaying maloperation make system, the system include CPU,
FPGA, starting-up later time, the CPU are connected with the FPGA, and the FPGA is used for and starting relay by starting-up later time respectively
Connection, the CPU constantly sends protection log-on data to FPGA with the cycle set, and the protection log-on data includes protection
Starting state signal and protection, which start, performs signal；When FPGA detects protection starting state signal effectively, forwarded and protected by FPGA
Protect log-on data, control starting relay action；Starting state invalidating signal is protected when FPGA is detected, and timing is not set persistently
Protection starting state signal is detected after the fixed time again effectively, then by FPGA forwarding protection log-on datas, control start after
Electrical equipment is acted；Or when FPGA detects protection starting state invalidating signal, timing and after the time persistently set, control starts
Relay is failure to actuate.
Further, in addition to outlet loop, the outlet loop is used to be connected with exit relay, and the CPU is to set
The fixed cycle constantly sends protection exit data to FPGA, and the protection exit data include protection exit status signal and guarantor
Shield outlet performs signal；
When FPGA detects protection exit status signal effectively, by FPGA forwarding protection outlet datas, control outlet relay
Device is acted；As FPGA, to detect protection exit status signal invalid, and detects guarantor after the time that timing is not set persistently again
Protect discharge state signal effectively, then by FPGA forwarding protection outlet datas, control exit relay action；Or when FPGA detections
Invalid to protection exit status signal, timing and after the time persistently set, control exit relay is failure to actuate.
Further, the first monostable flipflop is formed by the FPGA, to judge to protect starting state signal, and entered
Row timing.
Further, the second monostable flipflop is formed by the FPGA, to judge protection exit status signal, and entered
Row timing.
The beneficial effects of the invention are as follows：
Startup/outlet data is protected in being sent to FPGA for the cpu cycle property of the present invention, start when FPGA detects protection/
Startup/exit relay action is controlled when outlet data is effective；As FPGA, to detect protection exit status signal invalid, and timing
Protection startup/discharge state signal is detected after the time not set persistently again effectively, control startup/exit relay is moved
Make；Or when FPGA detects protection startup/discharge state invalidating signal, timing and after the time persistently set, control starts/
Exit relay is failure to actuate.The present invention improves the accuracy of protection startup/outlet data, and then improves relay protection action
Reliability, and directly by FPGA send protection start, outlet signal, no longer through export plug-in unit, reduce the multilayer of data
Transmission, improves the quick-action, reliability and correctness of relay protection；And protection data are periodically judged, logic letter
It is single, cumbersome signal content parsing is eliminated, FPGA internal resources are saved.
Brief description of the drawings
Fig. 1 is that the monostable circuit based on FPGA prevents the principle schematic of protection misoperation；
Fig. 2 is the flow chart that FPGA is handled protection data；
Fig. 3 is that FPGA utilizes flow chart of the monostable flipflop to the protection log-on data filtering of mistake.
Embodiment
The embodiment to the present invention is further described below in conjunction with the accompanying drawings：
A kind of embodiment of system for preventing protective relaying maloperation from making based on FPGA of the present invention：
A kind of system that protective relaying maloperation is made of preventing based on FPGA, including power supply, CPU, starting-up later time, export back
Road, outside FLASH and FPGA；CPU sends protection data to FPGA by external bus；Outside FLASH is used to deposit FPGA journeys
Sequence, and the guiding loading FPGA programs when upper electric；Power supply provides power supply, the configuration chip required for normal work for FPGA；CPU
The protection data-signal sent sends protection enabling signal and protection exit signal after FPGA is handled, respectively by starting
Loop, outlet loop drive corresponding starting relay and exit relay action, while FPGA is touched by monostable flipflop
Hair width 5ms pulse signal is filtered to wrong data, is prevented protection error starting, is exported by mistake.
The detailed process of the method for preventing protective relaying maloperation work based on the system is as follows：
1st, after CPU receives the information such as switch tool operation, failure, sent and protected to FPGA per 2ms by external bus
Log-on data and protection exit data.
2nd, after the loading of system electrification FPGA programs, FPGA detects the protection log-on data and protection exit of CPU transmissions in real time
Data.FPGA produces a CLK1K_en pulse signal per 100us, when FPGA detects the protection log-on data of CPU transmissions,
Handled, for FPGA, protection log-on data by start_updata, StartP_i, StartN_i, StartP_o and
StartN_o is constituted, if start_updata=1, sends corresponding protection starting state signal, then by FPGA forwarding protections
Log-on data, while the corresponding protection of FPGA outputs, which starts, performs signal StartP_o=StartP_i, StartN_o=
StartN_i, directly drives starting relay correct operation by starting-up later time, no longer through exporting plug-in unit, reduces many of data
Layer transmission, improves the quick-action, reliability and correctness of relay protection.
Meanwhile, FPGA generates the first monostable flipflop using CLK1K_en pulse signals, and width is 5ms, using monostable
State trigger is filtered to the abnormal signal that CPU is sent, when CPU is abnormal, due to the subcommand time and command context that send
All it is random, with very big uncertainty, by the start_updata signals in sense command, filter false data,
It is divided into situations below：
(1) protection log-on data may not be sent out, start_updata is now can't detect, or work as start_updata=
0, counter starts timing, often produces after a pulse signal timer cumulative 1, timing 5ms, exports log-on data StartP_o
=0, StartN_o=1, starting relay is correctly failure to actuate.
(2) if there is partial error data in correct data, detect start_updata=0, rolling counters forward once,
When being less than 5ms during counter counts, FPGA is not exported, and when detecting start_updata=1, counter is set to 0, simultaneously
Corresponding protection enabling signal StartP_o=StartP_i, StartN_o=StartN_i of FPGA outputs, passes through starting-up later time
Starting relay correct operation is driven, because the CPU cycles for sending protection data are 2ms, and is only more than when counter counts
During equal to 5ms, start_updata=0 is often detected, rolling counters forward is accumulated once, when being more than or equal to 5ms during counter counts,
FPGA just exports StartP_o=0, StartN_o=1, the filtering error data that the cycle is less than 5ms can thus be fallen, no
Normal exit is influenceed, is returned while exporting signal, enabling signal is maintained the state of invalid bit, starting relay is failure to actuate,
Prevent from exporting by mistake, improve the security reliability that starting relay is failure to actuate.
3rd, when FPGA detects the protection exit data of CPU transmissions, handled, for FPGA, protection exit data
Be made up of ck_updata, ck_i, ck_o, if ck_updata=1, send corresponding protection exit status signal, then by
FPGA forwarding protection outlet datas, while FPGA, which exports corresponding protection exit, performs signal ck_o=ck_i, directly by going out
Mouth loop driving exit relay correct operation, no longer through exporting plug-in unit, reduces the multiple layers transmission of data, improves relay guarantor
Quick-action, reliability and the correctness of shield.
Meanwhile, FPGA generates the second monostable flipflop using CLK1K_en pulse signals, and width is 5ms, using monostable
State trigger is filtered to the abnormal signal that CPU is sent, when CPU is abnormal, due to the subcommand time and command context that send
All it is random, with very big uncertainty, by the start_updata signals in sense command, filter false data,
It is divided into situations below：
(1) protection exit data may not be sent out, ck_updata is now can't detect, or work as ck_updata=0, are counted
Device starts timing, often produces after pulse signal timer cumulative 1, timing 5ms, exports outlet data ck_o=0, outlet after
Electrical equipment is correctly failure to actuate.
(2) if there are partial error data in correct data, ck_updata=0 is detected, rolling counters forward once, is counted
When the timing of number device is less than 5ms, FPGA is not exported, and when detecting ck_updata=1, counter is set to 0, while FPGA
The corresponding outlet enabling signal ck_o=ck_i of output, exit relay correct operation is driven by outlet loop, due to CPU hairs
The cycle for sending protection data is 2ms, and when being more than or equal to 5ms only when counter counts, often detects ck_updata=0, is counted
Rolling counters forward is accumulated once, and when being more than or equal to 5ms during counter counts, FPGA just exports ck_o=0, thus can the cycle is small
Fall in 5ms filtering error data, do not influence normal exit, returned while exporting signal, use message number and maintain invalid bit
State, starting relay is failure to actuate, and prevents from exporting by mistake, improves the security reliability that exit relay is failure to actuate.
In the present embodiment, CPU is sent and protects the cycle of data to be set to 2ms, the pulse width of monostable flipflop is set
5ms is set to, as other embodiment, can be arranged as required to as other numerical value, it can also be provided that a scope.
The cycle that CPU in this implementation sends protection data need to be less than the pulse width of monostable flipflop, such ability
Error signal is filtered away.
The present invention only judges that logic is simple to the CPU periodicity protection signals sent, is specifically sent out without parsing CPU
What is sent is any content, saves FPGA internal resources, improves the quick-action of relay protection.
The present invention realizes the modularized encapsulation exported to protection signal by FPGA, enhances portability, shortens again
The cycle of secondary exploitation.
Specific embodiment is presented above, but the present invention is not limited to embodiment described above.The present invention
Basic ideas be above-mentioned basic scheme, for those of ordinary skill in the art, according to the teachings of the present invention, design each
Plant the model deformed, formula, parameter and creative work need not be spent.In the principle and the situation of spirit for not departing from the present invention
Under to embodiment carry out change, modification, replacement and modification still fall within protection scope of the present invention.
Claims (8)
1. a kind of method that protective relaying maloperation is made of preventing based on FPGA, it is characterised in that including control starting relay
Step：
CPU constantly sends protection log-on data to FPGA with the cycle set, and the protection log-on data includes protection and started
Status signal and protection, which start, performs signal；
When FPGA detects protection starting state signal effectively, by FPGA forwarding protection log-on datas, control starting relay is moved
Make；Starting state invalidating signal is protected when FPGA is detected, and detects protection after the time that timing is not set persistently again and opens
Effectively, then by FPGA forwarding protection log-on datas, control starting relay is acted dynamic status signal；Or when FPGA detects guarantor
Starting state invalidating signal is protected, timing and after the time persistently set, control starting relay is failure to actuate.
2. the method that protective relaying maloperation is made of preventing based on FPGA according to claim 1, it is characterised in that also include
The step of controlling exit relay：
CPU constantly sends protection exit data to FPGA with the cycle set, and the protection exit data include protection exit
Status signal and protection exit perform signal；
When FPGA detects protection exit status signal effectively, by FPGA forwarding protection outlet datas, control exit relay is moved
Make；As FPGA, to detect protection exit status signal invalid, and detect and protect out again after the time that timing is not set persistently
Effectively, then by FPGA forwarding protection outlet datas, control exit relay is acted mouth status signal；Or when FPGA detects guarantor
Discharge state invalidating signal is protected, timing and after the time persistently set, control exit relay is failure to actuate.
3. the method that protective relaying maloperation is made of preventing based on FPGA according to claim 1, it is characterised in that by described
FPGA the first monostable flipflops of formation, to judge to protect starting state signal, and carry out timing.
4. the method that protective relaying maloperation is made of preventing based on FPGA according to claim 2, it is characterised in that by described
FPGA the second monostable flipflops of formation, to judge protection exit status signal, and carry out timing.
5. it is a kind of based on FPGA preventing protective relaying maloperation make system, it is characterised in that the system include CPU, FPGA,
Starting-up later time, the CPU is connected with the FPGA, and the FPGA is used to be connected with starting relay respectively by starting-up later time,
The CPU constantly sends protection log-on data to FPGA with the cycle set, and the protection log-on data includes protection and started
Status signal and protection, which start, performs signal；When FPGA detects protection starting state signal effectively, opened by FPGA forwarding protections
Dynamic data, control starting relay action；Starting state invalidating signal is protected when FPGA is detected, and what timing was not set persistently
Protection starting state signal is detected after time again effectively, then by FPGA forwarding protection log-on datas, controls starting relay
Action；Or when FPGA detects protection starting state invalidating signal, timing and after the time persistently set, control starts relay
Device is failure to actuate.
6. the system that protective relaying maloperation is made of preventing based on FPGA according to claim 5, it is characterised in that also include
Outlet loop, the outlet loop is used to be connected with exit relay, and the CPU is constantly sent with the cycle set to FPGA
Protection exit data, the protection exit data include protection exit status signal and protection exit performs signal；
When FPGA detects protection exit status signal effectively, by FPGA forwarding protection outlet datas, control exit relay is moved
Make；As FPGA, to detect protection exit status signal invalid, and detect and protect out again after the time that timing is not set persistently
Effectively, then by FPGA forwarding protection outlet datas, control exit relay is acted mouth status signal；Or when FPGA detects guarantor
Discharge state invalidating signal is protected, timing and after the time persistently set, control exit relay is failure to actuate.
7. the system that protective relaying maloperation is made of preventing based on FPGA according to claim 5, it is characterised in that by described
FPGA the first monostable flipflops of formation, to judge to protect starting state signal, and carry out timing.
8. the system that protective relaying maloperation is made of preventing based on FPGA according to claim 6, it is characterised in that by described
FPGA the second monostable flipflops of formation, to judge protection exit status signal, and carry out timing.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710352502.4A CN107171297B (en) | 2017-05-18 | 2017-05-18 | A kind of method and system for preventing protective relaying maloperation from making based on FPGA |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710352502.4A CN107171297B (en) | 2017-05-18 | 2017-05-18 | A kind of method and system for preventing protective relaying maloperation from making based on FPGA |
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| Publication Number | Publication Date |
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| CN107171297A true CN107171297A (en) | 2017-09-15 |
| CN107171297B CN107171297B (en) | 2019-02-05 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108155619A (en) * | 2017-12-31 | 2018-06-12 | 长园深瑞继保自动化有限公司 | Protective relaying device multi-core CPU embedded system handles method and platform |
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| EP2096751B1 (en) * | 2006-11-02 | 2014-03-12 | Mitsubishi Electric Corporation | Electric motor car control apparatus |
| CN103683502A (en) * | 2013-11-30 | 2014-03-26 | 许继电气股份有限公司 | Drive control method and drive control device for switch circuit of process level device of intelligent substation |
| CN105576688A (en) * | 2015-12-28 | 2016-05-11 | 国网辽宁省电力有限公司电力科学研究院 | Control protection method for flexible direct current power transmission system |
| CN106410973A (en) * | 2016-11-28 | 2017-02-15 | 国家电网公司 | Analysis method for maintenance state of protective relaying device of intelligent transformer station |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2096751B1 (en) * | 2006-11-02 | 2014-03-12 | Mitsubishi Electric Corporation | Electric motor car control apparatus |
| CN102420462A (en) * | 2011-12-01 | 2012-04-18 | 许继集团有限公司 | Process-level smart terminal equipment of smart substation |
| CN103683502A (en) * | 2013-11-30 | 2014-03-26 | 许继电气股份有限公司 | Drive control method and drive control device for switch circuit of process level device of intelligent substation |
| CN105576688A (en) * | 2015-12-28 | 2016-05-11 | 国网辽宁省电力有限公司电力科学研究院 | Control protection method for flexible direct current power transmission system |
| CN106410973A (en) * | 2016-11-28 | 2017-02-15 | 国家电网公司 | Analysis method for maintenance state of protective relaying device of intelligent transformer station |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108155619A (en) * | 2017-12-31 | 2018-06-12 | 长园深瑞继保自动化有限公司 | Protective relaying device multi-core CPU embedded system handles method and platform |
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| CN107171297B (en) | 2019-02-05 |
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