CN107170698B - Automatic adjusting method for etching amount of photoresist plug in through hole - Google Patents

Automatic adjusting method for etching amount of photoresist plug in through hole Download PDF

Info

Publication number
CN107170698B
CN107170698B CN201710368784.7A CN201710368784A CN107170698B CN 107170698 B CN107170698 B CN 107170698B CN 201710368784 A CN201710368784 A CN 201710368784A CN 107170698 B CN107170698 B CN 107170698B
Authority
CN
China
Prior art keywords
etching
photoresist
etching amount
oxide film
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710368784.7A
Other languages
Chinese (zh)
Other versions
CN107170698A (en
Inventor
江旻
昂开渠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huali Microelectronics Corp
Original Assignee
Shanghai Huali Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huali Microelectronics Corp filed Critical Shanghai Huali Microelectronics Corp
Priority to CN201710368784.7A priority Critical patent/CN107170698B/en
Publication of CN107170698A publication Critical patent/CN107170698A/en
Application granted granted Critical
Publication of CN107170698B publication Critical patent/CN107170698B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67242Apparatus for monitoring, sorting or marking
    • H01L21/67253Process monitoring, e.g. flow or thickness monitoring
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material

Abstract

The invention provides an automatic regulating method of the etching amount of a photoresist plug in a through hole, which is used for measuring the thickness of an oxide film of the through hole of the next batch on line; acquiring the detection time of the main etching end point of the previous batch of the same cavity, and calculating the weighted average value of the detection time; calculating to obtain target time for controlling the etching amount of the photoresist plug; and automatically adjusting the over-etching time of the next batch in the same cavity. The invention provides an automatic regulating method of the etching amount of a photoresist plug in a through hole, which considers the change of the self speed of a cavity and the thickness of an oxide film into a calculation formula, and utilizes an APC (advanced Process control) system to regulate the etching amount of the photoresist plug so as to achieve the effect of accurately controlling the appearance of the contact part of the through hole and a groove.

Description

Automatic adjusting method for etching amount of photoresist plug in through hole
Technical Field
The invention relates to the field of production control of semiconductor manufacturing factories, in particular to an automatic adjusting method for etching amount of a photoresist plug in a through hole.
Background
In the process of the through hole-preferred dual damascene trench etching process, photoresist is filled in the through hole to protect the appearance of the through hole in the trench etching process. Because the etching rate of the photoresist plug of the groove is usually less than that of the oxide film, fence-like residues are easily generated when the photoresist flows back to the oxide film, and the electrical characteristics and reliability of the through hole are influenced. Therefore, before the groove etching, a part of the photoresist plug in the through hole can be etched through the back etching of the photoresist, and the purpose of eliminating fence-shaped residues is achieved. Referring to fig. 1 to 6, a bottom barrier layer 200, a TEOS layer 300, a silicon nitride layer 400, a TEOS layer 500, a silicon oxynitride layer 600, and a photoresist 700 are sequentially disposed on a semiconductor substrate layer 100, fig. 2 is a structure after via etching, fig. 3 is a structure after photoresist filling, fig. 4 is a structure after photoresist etching, fig. 5 is a structure diagram of adding photoresist before trench etching, and fig. 6 is a structure after trench etching. In the prior art, photoresist back etching is performed in fixed time, cavity rate change and front layer film thickness change are not considered, and specific etching amount cannot be obtained through online measurement, so that the whole process integration is required to have an enough process window. Since both the electrical characteristics and the reliability of the via are related to this topography, fluctuations in the photoresist etch back may cause disturbances that are outside the process specification range under some particularly demanding process conditions.
Disclosure of Invention
The invention provides an automatic regulating method of the etching amount of a photoresist plug in a through hole, which considers the change of the self speed of a cavity and the thickness of an oxide film into a calculation formula, and utilizes an APC (advanced Process control) system to regulate the etching amount of the photoresist plug so as to achieve the effect of accurately controlling the appearance of the contact part of the through hole and a groove.
In order to achieve the above object, the present invention provides a method for automatically adjusting the etching amount of a photoresist plug in a via hole,
measuring the thickness of the oxide film of the through holes of the next batch on line;
acquiring the detection time of the main etching end point of the previous batch of the same cavity, and calculating the weighted average value of the detection time;
calculating to obtain target time for controlling the etching amount of the photoresist plug;
and automatically adjusting the over-etching time of the next batch in the same cavity.
Further, the target time for controlling the etching amount of the photoresist plug is calculated by adopting the following formula:
T=C*A*t,
where C is a constant, A is defined as the oxide film etching amount, i.e., the oxide film thickness, and t is defined as the weighted average of the main etching end point detection time.
Further, the constant C is calculated by using the following formula:
C=(1-S)*b/F,
wherein S is defined as the etching selection ratio of the oxide film and the photoresist, b is defined as the rate difference coefficient of main etching and through hole internal etching, which is a constant, and F is defined as the main etching amount.
Further, the etching selection ratio of the oxide film and the photoresist is calculated by adopting the following formula:
S=Vp/Va,
where Va is defined as the oxide film etch rate and Vp is defined as the photoresist etch rate.
The invention provides an automatic adjusting method for the etching amount of a photoresist plug in a through hole, which can calculate the etching rate by using an end point detection and conversion under the premise of very stable thickness of a photoresist coating by using an APC (advanced Process control) system under the condition of lacking an online detection means, calculate the time required by the required etching amount of the photoresist plug according to the thickness and the selection ratio of an oxide film, accurately control the etching amount and realize continuous adjustment.
Drawings
Fig. 1 to fig. 6 are flow charts of a prior art dual damascene trench etching process with via first.
FIG. 7 is a flowchart illustrating a method for automatically adjusting the etching amount of a photoresist plug in a via hole according to a preferred embodiment of the present invention.
FIG. 8 is a schematic diagram of the main etching amount according to the preferred embodiment of the present invention.
FIG. 9 is a schematic diagram of the over-etching amount according to the preferred embodiment of the invention.
FIG. 10 is a diagram illustrating the amount of oxide film etched according to the preferred embodiment of the present invention.
FIG. 11 is a diagram illustrating the amount of photoresist plug etching according to the preferred embodiment of the invention.
Detailed Description
The following description will be given with reference to the accompanying drawings, but the present invention is not limited to the following embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is noted that the drawings are in greatly simplified form and that non-precision ratios are used for convenience and clarity only to aid in the description of the embodiments of the invention.
Referring to fig. 7, fig. 7 is a flowchart illustrating a method for automatically adjusting the etching amount of the photoresist plug in the through hole according to a preferred embodiment of the invention. The invention provides a method for automatically adjusting the etching amount of a photoresist plug in a through hole,
step S100: measuring the thickness of the oxide film of the through holes of the next batch on line;
step S200: acquiring the detection time of the main etching end point of the previous batch of the same cavity, and calculating the weighted average value of the detection time;
step S300: calculating to obtain target time for controlling the etching amount of the photoresist plug;
step S400: and automatically adjusting the over-etching time of the next batch in the same cavity.
According to the preferred embodiment of the present invention, the target time for controlling the etching amount of the photoresist plug is calculated by using the following formula:
T=C*A*t,
wherein C is a constant, a is defined as the etching amount of the oxide film, i.e., the thickness of the oxide film, please refer to fig. 10, fig. 10 is a schematic diagram of the etching amount of the oxide film according to the preferred embodiment of the present invention, and t is defined as the weighted average of the main etching endpoint detection time.
Further, the constant C is calculated by using the following formula:
C=(1-S)*b/F,
wherein, S is defined as the etching selectivity of the oxide film and the photoresist, b is defined as the rate difference coefficient between the main etching and the etching inside the via hole, which is a constant, and F is defined as the main etching amount, as shown in fig. 8, fig. 8 is a schematic diagram of the main etching amount in the preferred embodiment of the present invention.
Referring to fig. 9, fig. 9 is a schematic diagram of the over-etching amount according to the preferred embodiment of the present invention, where the over-etching amount is R, the following results are obtained:
and R is (F/T b) T, wherein T is target time for controlling the etching amount of the photoresist plug, T is main etching end point detection time, and b is a rate difference coefficient of main etching and through hole internal etching.
The etching selection ratio of the oxide film and the photoresist is calculated by adopting the following formula:
S=Vp/Va,
where Va is defined as the oxide film etch rate and Vp is defined as the photoresist etch rate.
In the groove etching process, defining the etching amount of an oxide film, namely the thickness of the oxide film is A, and the etching rate is Va; the etching amount of the photoresist is P, and the etching rate is Vp; the etching selection ratio of the oxide film to the photoresist is S; ideally, the final height of the photoresist is flush with the bottom of the trench, so that: P/Vp is a/Va, S is Vp/Va, and P is a (S <1) is derived, as shown in fig. 11, and fig. 11 is a diagram illustrating the etching amount of the photoresist plug according to the preferred embodiment of the present invention.
Since P ═ a-R, combining the above formula can yield:
and T is A (1-S) T b/F, and the time can be finely adjusted on the basis of T to reach the required height of the photoresist plug. The etching time of the photoresist of the next batch in the same cavity is etched back, and the fine tuning range can be defined by user on the basis of ideal conditions.
In summary, the invention provides an automatic adjustment method for the etching amount of a photoresist plug in a through hole, which can calculate the etching rate by using end point detection on the premise that the thickness of the photoresist coating is very stable by using an APC (advanced Process control) system under the condition of lacking an online detection means, calculate the time required by the required etching amount of the photoresist plug according to the thickness and the selection ratio of the oxide film, accurately control the etching amount, and realize continuous adjustment.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention should be determined by the appended claims.

Claims (2)

1. A method for automatically adjusting the etching amount of a photoresist plug in a through hole is characterized by comprising the following steps:
measuring the thickness of the oxide film of the through holes of the next batch on line;
acquiring the detection time of the main etching end point of the previous batch of the same cavity, and calculating the weighted average value of the detection time;
obtaining target time for controlling the etching amount of the photoresist plug by calculation, wherein the target time for controlling the etching amount of the photoresist plug is calculated by adopting the following formula:
T=C*A*t,
wherein C is a constant, A is defined as the etching amount of the oxide film, namely the thickness of the oxide film, t is defined as the weighted average value of the main etching endpoint detection time, and the constant C is calculated by adopting the following formula:
C=(1-S)*b/F,
wherein S is defined as the etching selection ratio of the oxide film and the photoresist, b is defined as the rate difference coefficient of main etching and through hole internal etching, which is a constant, and F is defined as the main etching amount;
and automatically adjusting the over-etching time of the next batch in the same cavity.
2. The method of claim 1, wherein the etching selectivity of the oxide film to the photoresist is calculated using the following formula:
S=Vp/Va,
where Va is defined as the oxide film etch rate and Vp is defined as the photoresist etch rate.
CN201710368784.7A 2017-05-23 2017-05-23 Automatic adjusting method for etching amount of photoresist plug in through hole Active CN107170698B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710368784.7A CN107170698B (en) 2017-05-23 2017-05-23 Automatic adjusting method for etching amount of photoresist plug in through hole

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710368784.7A CN107170698B (en) 2017-05-23 2017-05-23 Automatic adjusting method for etching amount of photoresist plug in through hole

Publications (2)

Publication Number Publication Date
CN107170698A CN107170698A (en) 2017-09-15
CN107170698B true CN107170698B (en) 2020-01-24

Family

ID=59820464

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710368784.7A Active CN107170698B (en) 2017-05-23 2017-05-23 Automatic adjusting method for etching amount of photoresist plug in through hole

Country Status (1)

Country Link
CN (1) CN107170698B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5926690A (en) * 1997-05-28 1999-07-20 Advanced Micro Devices, Inc. Run-to-run control process for controlling critical dimensions
CN101937869A (en) * 2009-06-30 2011-01-05 上海华虹Nec电子有限公司 Damascus process integration method without dielectric film palisade residual risks
CN103400803A (en) * 2013-07-24 2013-11-20 上海宏力半导体制造有限公司 Formation method of flash memory storage unit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5926690A (en) * 1997-05-28 1999-07-20 Advanced Micro Devices, Inc. Run-to-run control process for controlling critical dimensions
CN101937869A (en) * 2009-06-30 2011-01-05 上海华虹Nec电子有限公司 Damascus process integration method without dielectric film palisade residual risks
CN103400803A (en) * 2013-07-24 2013-11-20 上海宏力半导体制造有限公司 Formation method of flash memory storage unit

Also Published As

Publication number Publication date
CN107170698A (en) 2017-09-15

Similar Documents

Publication Publication Date Title
US10998174B2 (en) Dry etching equipment and method for producing semiconductor device
May et al. Statistical experimental design in plasma etch modeling
CN100419962C (en) Controlling method for gate formation of semiconductor device
CN102468139B (en) Patterning methodology for uniformity control
US7596421B2 (en) Process control system, process control method, and method of manufacturing electronic apparatus
KR20030076672A (en) Method and apparatus for controlling etch selectivity
KR20050075317A (en) Method for eching insulation film
US9666472B2 (en) Method for establishing mapping relation in STI etch and controlling critical dimension of STI
US6893974B1 (en) System and method for fabricating openings in a semiconductor topography
CN107170698B (en) Automatic adjusting method for etching amount of photoresist plug in through hole
JP2008072032A (en) Manufacturing method of semiconductor device
CN100490089C (en) Method for etching inclined shoulder type side wall in large scale integrated circuit logic device
KR100836945B1 (en) A method for decreasing variation in gate electrode width
KR20040019270A (en) Semiconductor manufacturing apparatus and method for manufacturing semiconductor device
US6638777B2 (en) Apparatus for and method of etching
JP3887238B2 (en) Insulating film etching method
JP2011040601A (en) Method of manufacturing semiconductor device
US7064087B1 (en) Phosphorous-doped silicon dioxide process to customize contact etch profiles
CN105336585A (en) Etching method and formation method of interconnection structure
CN111968914B (en) Thick aluminum etching method
CN101901779A (en) Method for controlling processing process of STI (Shallow Trench Isolation) channel of wafer
US9418832B2 (en) Method of forming a dielectric film
JP2007005367A (en) Process control system, process control method and method of manufacturing electronic apparatus
JP2002016136A (en) Manufacturing method of semiconductor device
JP2006245036A (en) Forming method of element isolation layer, manufacturing method of electronic device, and cmp apparatus

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant