CN107168744B - System and method for the load of DSP chip file - Google Patents
System and method for the load of DSP chip file Download PDFInfo
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- CN107168744B CN107168744B CN201710364532.7A CN201710364532A CN107168744B CN 107168744 B CN107168744 B CN 107168744B CN 201710364532 A CN201710364532 A CN 201710364532A CN 107168744 B CN107168744 B CN 107168744B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
Abstract
The invention discloses a kind of systems for the load of DSP chip file, comprising: a main control module, a field programmable gate array FPGA chip and multiple digital signal processor DSP chips；The main control module is connected with the fpga chip using compact Peripheral Component Interconnect standard cpci bus；The main control module, for receiving control instruction and according to the title invocation target file of file destination in the control instruction and loading the file destination to the fpga chip；The fpga chip loads the file destination to the multiple dsp chip for guiding；Pass through hyperlink Hyper Link interface inter-link between the multiple dsp chip.The invention also discloses a kind of methods for the load of DSP chip file.
Description
Technical field
The present invention relates to field of communication technology, in particular to it is a kind of for Digital Signal Processing (full name in English:
Digital Signal Process, English abbreviation: DSP) chip file load system and method.
Background technique
Dsp chip has powerful data-handling capacity and the higher speed of service, in field of communication technology increasingly
To extensive use.When system designs, often using dsp chip as data processing unit.
Traditional dsp chip file loading scheme is mainly achieved in that utilizes emulator by burning file to DSP core in advance
In piece, then system electrification is loaded.Occurred using emulator later by burning file into external memory, by memory
It is designed to pluggable module, is linked together by contact pin and socket with circuit board, by replacement memory module again to system
It powers on to replace the file being loaded into dsp chip.
Existing dsp chip file loading scheme needs to carry out system power down process before file load, and the program is realized
Process is more complicated, and file loading speed is lower, and the cost is relatively high.
Summary of the invention
The embodiment of the invention provides a kind of system and methods for the load of DSP chip file to solve
Certainly the prior art needs to carry out system the lower and at high cost problem of power down process file loading speed before file load.In order to
There is a basic understanding to some aspects of the embodiment of disclosure, simple summary is shown below.The summarized section is not
Extensive overview, nor to determine key/critical component or describe the protection scope of these embodiments.Its sole purpose is
Some concepts are presented with simple form, in this, as the preamble of following detailed description.
According to a first aspect of the embodiments of the present invention, a kind of system for the load of dsp chip file, feature are provided
It is, comprising: a main control module, a field programmable gate array (full name in English: Field-Programmable
Gate Array, English abbreviation: FPGA) chip and multiple dsp chips；The main control module and the fpga chip are using tight
Gather type Peripheral Component Interconnect standard (full name in English: Compact Peripheral Component Interconnect, English
Referred to as: CPCI) bus connects；The main control module, for receiving control instruction and according to target text in the control instruction
The title invocation target file of part simultaneously loads the file destination to the fpga chip；Wherein, the main control module includes:
Based on Common Object Request Broker Architecture (full name in English: Common Object Request Broker
Architecture, English abbreviation: CORBA) specification software communication System Framework SCA middleware, cpci bus interface and behaviour
Make system；Software communication System Framework (the full name in English: Service Component based on CORBA specification
Architecture, English abbreviation: SCA) middleware includes waveform application component and apparatus assembly；The operating system includes outer
If component connection standard (full name in English: Peripheral Component Interconnect, English abbreviation: PCI) drives；
The waveform application component, for finding the apparatus assembly according to dsp chip ID in the control instruction and by the control
Instruction is sent to the apparatus assembly；The apparatus assembly, for calling the PCI driving to read file destination；The PCI drives
It is dynamic, for the file destination to be sent to the fpga chip；The fpga chip loads the file destination for guiding
To the multiple dsp chip；The waveform application component and the apparatus assembly pass through the interface communication that standardizes based on CORBA；
The apparatus assembly is additionally coupled to the cpci bus interface, and is connected by the cpci bus interface and the cpci bus
It connects；Pass through hyperlink Hyper Link interface inter-link between the multiple dsp chip.
Optionally, the control instruction includes file destination title, configuration parameter and dsp chip ID；The fpga chip
The file destination is loaded to corresponding dsp chip by dsp chip ID guidance；Control instruction include file destination title,
Configuration parameter and dsp chip ID can make system purposefully carry out file selection and load, accelerate system processing speed.
Optionally, further include a function selecting module, select and set configuration parameter generation control for carrying out function
Instruction；The function selecting module and the main control module based on Common Object Request Broker Architecture CORBA by being advised
The interface of model is communicated by local network LAN bus.The function selecting module and the main control module division of labor are clear, phase
The integrality of intercommunicated guarantee system work.
Optionally, the function choosing-item provided in the waveform application component and the function selecting module corresponds.Institute
It states apparatus assembly and dsp chip corresponds.The waveform application component can be loaded on the different apparatus assemblies.Institute
Pair of waveform application component, the function choosing-item provided in the function selecting module, the apparatus assembly and the dsp chip is provided
It should be related to interconnection, intercommunication and interoperability between guarantee system, reduce the complexity of exploitation, reduce development cost.
Optionally, the operating system of the main control module operation is VxWorks system, and the VxWorks system includes
The PCI driving.
Optionally, each external flash memory of the dsp chip (full name in English: Flash EEPROM, English abbreviation:
) and a Double Data Rate synchronous DRAM (full name in English: Dual Data Rate Synchronous Flash
Dynamic Random Access Memory, English abbreviation: DDR), dsp chip driving text is had cured in the FLASH
Part, for the fpga chip by universal input/output (full name in English: General Purpose Input Output,
English abbreviation: GPIO) interface provide control signal after load complete dsp chip initialization；The DDR, it is described for storing
File destination.
Optionally, the multiple dsp chip is two dsp chips.
Optionally, dsp chip ID is used to distinguish each dsp chip in the control instruction, comprising: device number, or,
Device number and manufacturer number.
According to a second aspect of the embodiments of the present invention, a kind of method for the load of dsp chip file is provided, comprising: main
Control module receives control instruction；The main control module parses the control instruction, obtains in the control instruction and includes
The title of file destination；The main control module selects waveform application component according to the title of the file destination；The waveform
Application component finds apparatus assembly according to the dsp chip ID for including in the control instruction and transmits the control instruction；It is described
Apparatus assembly receives the control instruction of the waveform application component transmitting；The apparatus assembly is according in the control instruction
The title of file destination calls the PCI driving to read the file destination；The file destination is sent to by the PCI driving
Fpga chip；The fpga chip loads the file destination to the corresponding dsp chip of the dsp chip ID.
Optionally, the control instruction is sent by function selecting module, and the control instruction includes file destination title, matches
Set parameter and dsp chip ID；The fpga chip loads the file destination to corresponding DSP by dsp chip ID guidance
Chip；Control instruction includes file destination title, configuration parameter and dsp chip ID, and system can be made purposefully to carry out file choosing
It selects and loads, accelerate system processing speed.
Optionally, dsp chip ID is used to distinguish each dsp chip in the control instruction, comprising: device number, or,
Device number and manufacturer number.
Optionally, the file destination is stored in the external DDR of the dsp chip.
Optionally, before function selecting module sends control instruction further include: powered on to the fpga chip；To described
Function selecting module, the main control module and the dsp chip power on.
Optionally, further includes: the fpga chip sends control signal；The dsp chip adds according to the control signal
Carry the dsp chip driving file being solidificated in the external FLASH of the dsp chip.
Technical solution provided in an embodiment of the present invention can include the following benefits:
System provided in this embodiment is based on SCA and carries out software structure design, and hardware configuration uses DSP+FPGA framework, real
Now to dsp chip file dynamically load, whole process does not need to restart load, improves the loading efficiency of file, improves system
Flexibility and compatibility, it is low to reduce system cost.
It should be understood that above general description and following detailed description be only it is exemplary and explanatory, not
It can the limitation present invention.
Detailed description of the invention
The drawings herein are incorporated into the specification and forms part of this specification, and shows and meets implementation of the invention
Example, and be used to explain the principle of the present invention together with specification.
Fig. 1 is a kind of system structure diagram for the load of dsp chip file shown according to an exemplary embodiment；
Fig. 2 is a kind of system structure diagram for the load of dsp chip file shown according to an exemplary embodiment；
Fig. 3 is a kind of block diagram of method for the load of dsp chip file shown according to an exemplary embodiment；
Fig. 4 is a kind of block diagram of method for the load of dsp chip file shown according to an exemplary embodiment.
Specific embodiment
The following description and drawings fully show specific embodiments of the present invention, to enable those skilled in the art to
Practice them.Embodiment only represents possible variation.Unless explicitly requested, otherwise individual components and functionality is optional, and
And the sequence of operation can change.The part of some embodiments and feature can be included in or replace other embodiments
Part and feature.The range of embodiment of the present invention includes the entire scope of claims and the institute of claims
There is obtainable equivalent.Herein, each embodiment can individually or generally be indicated that this is only with term " invention "
It is merely for convenience, and if in fact disclosing the invention more than one, it is not meant to automatically limit the range of the application
For any single invention or inventive concept.Herein, relational terms such as first and second and the like are used only for one
Entity, which is perhaps operated, to be distinguished and exists without requiring or implying between these entities or operation with another entity or operation
Any actual relationship or sequence.Moreover, the terms "include", "comprise" or its any other variant be intended to it is non-exclusive
Property include so that include a series of elements process, method or equipment not only include those elements, but also including
Each embodiment is described in a progressive manner other elements that are not explicitly listed herein, what each embodiment stressed
It is the difference from other embodiments, the same or similar parts in each embodiment may refer to each other.For embodiment
For disclosed structure, product etc., since it is corresponding with part disclosed in embodiment, so be described relatively simple, it is related
Place is referring to method part illustration.
As shown in Figure 1, the system provided in an embodiment of the present invention for the load of dsp chip file includes: a main control
Module 1200, a fpga chip 1300 and multiple dsp chips.
Main control module 1200 is connected with fpga chip 1300 using compact Peripheral Component Interconnect standard cpci bus.It is main
Control module 1200, for receiving control instruction and according to control instruction invocation target file and loading file destination to FPGA core
Piece 1300.
Wherein, main control module 1200 includes: software communication System Framework SCA middleware, CPCI based on CORBA specification
Bus interface and operating system, the SCA middleware based on CORBA specification includes waveform application component 1201 and apparatus assembly
1202, operating system includes Peripheral Component Interconnect standard PCI driving, waveform application component 1201, for according in control instruction
Dsp chip ID finds apparatus assembly 1202 and control instruction is sent to apparatus assembly 1202.Apparatus assembly 1202 is and DSP core
The software module of piece phase mapping.It is corresponding with each dsp chip to have an apparatus assembly 1202.Apparatus assembly 1202, for adjusting
It is driven with PCI and reads file destination, file destination is sent to fpga chip 1300,1201 He of waveform application component by PCI driving
For apparatus assembly 1202 by the interface communication standardized based on CORBA, apparatus assembly 1202 is additionally coupled to cpci bus interface, and leads to
Cpci bus interface is crossed to connect with cpci bus.
Hardware and software is defined in different levels in detail based on the system architecture of SCA, is the design of system
Provide detailed specification with exploitation, establish the structural framing independently of equipment, make system have component portability and
Reusability, and the compatibility between the product for ensuring to be developed according to SCA.SCA can guarantee reality between the various systems based on the specification
Now interconnection, intercommunication and interoperability, meanwhile, it also provides transplantable platform for different SCA waveform application components, and passes through
Interface sufficiently complicated using CORBA specification encapsulation, reduces the complexity of exploitation, reduces development cost.By SCA technology
The switching at runtime that can be realized file does not need device powers down or restarts and reload file.
Fpga chip 1300 passes through super for guidance load file destination to multiple dsp chips between multiple dsp chips
Link Hyper Link interface inter-link.
Hyper Link interface provides a kind of high speed, low latency between dsp chip, and the few communication connection of number of pins connects
Mouthful.Data transmission bauds has more advantage than previous single address data bus, is able to satisfy the data transportation requirements of high-speed.
Dsp chip has powerful data-handling capacity, can handle complicated data type, and software algorithm is easily modified, outside
If resourceful.System structure hardware of the embodiment of the present invention uses DSP+FPGA framework, and dsp chip passes through as processing center
Data/address bus completes the data exchange with fpga chip, realizes complex data communication and external control.Fpga chip is big using it
Scale hardware resource realizes Interface Expanding and control function, and initialization and the file of dsp chip are realized by fpga chip
Deployment.
System provided in this embodiment is based on SCA and carries out software structure design, and hardware configuration uses DSP+FPGA framework, real
Now to dsp chip file dynamically load, whole process does not need to restart load, improves the loading efficiency of file, improves system
Flexibility and compatibility, it is low to reduce system cost.
In some embodiments, referring to fig. 2, for dsp chip file load system include function selecting module 1100,
1200, fpga chips 1300 of main control module and multiple dsp chips.
Wherein, function selecting module 1100 select ands set configuration parameter generation control instruction, control for carrying out function
Instruction includes file destination title, configuration parameter and dsp chip ID.Wherein, the entitled text for being loaded into dsp chip of file destination
The title of part, to execute configuration parameter when corresponding function after dsp chip load file destination, dsp chip ID is configuration parameter
Load the dsp chip ID of file destination.
The different function choosing-items that function selecting module 1100 provides correspond to different file destinations.Main control module 1200
Local area network (full name in English: Local Area is passed through based on the interface of CORBA specification definition with function selecting module 1100
Network, English abbreviation: LAN) it is communicated.Function selecting module 1100 and the division of labor of main control module 1200 are clear, mutually interconnect
The integrality of logical guarantee system work
Main control module 1200 runs vxworks operating system, and the SCA middleware based on CORBA specification is deployed in master control
On molding block 1200, wherein the SCA middleware exists with .xml file and .out document form, by Spectra CX software
It generates.SCA middleware includes waveform application component 1201 and apparatus assembly 1202.Waveform application component 1201, refers to according to control
Dsp chip ID finds apparatus assembly 1202 and control instruction is sent to apparatus assembly 1202 in order, and apparatus assembly 1202 is used for
It calls the PCI driving of vxworks operating system to read file destination, file destination is write into ID pairs of dsp chip in control instruction
In the PCI address answered, and file destination is sent to fpga chip 1300.Each dsp chip has an exclusive ID, is used for
Each dsp chip is distinguished, the device number including dsp chip, further includes manufacturer number further.For each dsp chip
An apparatus assembly 1202 is taken out, waveform application component 1201 searches corresponding apparatus assembly 1202 by dsp chip ID, and
Send control instruction to apparatus assembly 1202.Waveform application component 1201 is and the function that provides in function selecting module 1100
The software module of option phase mapping, it is corresponding with each function choosing-item to have a waveform application component 1201.Apparatus assembly 1202
It is the software module with dsp chip phase mapping.It is corresponding with each dsp chip to have an apparatus assembly 1202.One waveform is answered
It can be loaded into component 1201 on different apparatus assemblies 1202.In waveform application component 1201, function selecting module 1100
Interconnection, intercommunication and interoperability between the function choosing-item of offer, apparatus assembly 1202 and the corresponding relationship guarantee system of dsp chip, drop
The complexity of low exploitation, reduces development cost.
Each external FLASH and DDR of dsp chip has cured dsp chip driving file, DSP core in FLASH
Load dsp chip driving file, is provided receiving fpga chip 1300 by universal input/output GPIO interface after piece powers on
The initialization of dsp chip is completed after control signal.File destination is stored in DDR.
DDR uses DDR3 in the present embodiment, and fpga chip uses sprtan-6, and dsp chip uses TMS320C6670 core
Piece.There are four the CorePac of integrated C66xDSP on TMS320C6670 chip, each core operates in 1.0 to 1.20GHz.
It is hardware-accelerated to provide high integration, low-power consumption and wieldy platform.
Fpga chip 1300 is connected by cpci bus and main control module 1200, and multiple dsp chips pass through Hyper
The connection of Link interface.
System electrification process are as follows: fpga chip 1300 is first powered up completion load, then function selecting module 1100 and master
Control module 1200 and dsp chip power on.Because the initialization of dsp chip and file load need the control of fpga chip 1300
System is realized, so first to power on to fpga chip 1300.
After system completion powers on, the dsp chip driving file that dsp chip load is solidificated in FLASH is receiving FPGA
The initialization of dsp chip is completed after the control signal that chip 1300 is provided by universal input/output GPIO interface.Then it executes
Dsp chip file loading procedure.
File dynamically load process are as follows: function to be loaded needed by the selection of function selecting module 1100 and is needed to configure
Parameter generates control instruction, by passing to main control module 1200 based on the interface that CORBA is standardized.Wherein, control instruction packet
Containing file destination title corresponding with the function of selection, the parameter needed to configure and need dsp chip ID to be loaded.File destination
For binary system (full name in English: binary, English abbreviation: bin) file, generated by emulator.Dsp chip ID is indicated target
File is loaded onto specified dsp chip.When main control module 1200 receives the control instruction of the sending of function selecting module 1100, wave
Shape application component 1201 can find corresponding apparatus assembly 1202 according to dsp chip ID in control instruction, and send an instruction to
Apparatus assembly 1202.When apparatus assembly 1202 receives the control instruction of the transmitting of waveform application component 1201, calling VxWorks behaviour
The PCI driving for making system reads file destination out of dsp chip external DDR, and file destination is write DSP core in control instruction
In the corresponding PCI address of piece ID, and file destination is sent to fpga chip 1300, finger is loaded by the guidance of fpga chip 1300
Fixed dsp chip directly substitutes original file and completes dsp chip file.When needing handoff functionality, in function selecting module
1100 carry out function switch, and successively execute abovementioned steps and complete to dsp chip file dynamically load, and whole process does not need weight
Open load.
System provided in this embodiment is based on SCA and carries out software structure design, and hardware configuration uses DSP+FPGA framework, real
Now to dsp chip file dynamically load, whole process does not need to restart load, improves the loading efficiency of file, improves system
Flexibility and compatibility, it is low to reduce system cost.
In some embodiments, system includes two dsp chips.
It is corresponding with aforementioned system embodiment, it is provided in an embodiment of the present invention to be loaded for dsp chip file referring to Fig. 3
Method include the following steps.
Step S301, main control module 1200 receive control instruction.
The received control instruction of main control module 1200 includes file destination title, and file destination is entitled to be loaded into DSP
The title of the file of chip.
Step S302, the main control module 1200 parse the control instruction, obtain in the control instruction and include
The title of file destination.
Step S303, the main control module 1200 select waveform application component according to the title of the file destination
1201。
The title of file destination is different, and corresponding waveform application component 1201 is different, and main control module 1200 is according to target
The title of file selects corresponding waveform application component 1201.
Step S304, the waveform application component 1201 find apparatus assembly according to dsp chip ID in the control instruction
1202 and the control instruction is sent to the apparatus assembly 1202.
Step S305, the apparatus assembly 1202 receive the control instruction.
Step S306, the apparatus assembly 1202 call PCI driving to read the file destination according to the control instruction,
And the file destination is sent to fpga chip 1300.
Step S307, the fpga chip 1300 load the file destination to the corresponding DSP core of the dsp chip ID
Piece.
Method provided in this embodiment may be implemented to dsp chip file dynamically load, and whole process, which does not need to restart, to be added
It carries, improves the loading efficiency of file, improve the flexibility and compatibility of system, it is low to reduce system cost.
In some embodiments, referring to fig. 4, the method for the load of dsp chip file includes the following steps.
Step S401, fpga chip 1300 power on.
Step S402, function selecting module 1100, main control module 1200 and dsp chip power on.
Fpga chip 1300 realizes the initialization and file deployment of dsp chip, first to FPGA before system is worked
Chip 1300 powers on, and powers on again to other modules after fpga chip 1300 powers on.
Step S403, the dsp chip driving text that the dsp chip load is solidificated in the external FLASH of the dsp chip
Part.
Dsp chip driving file, after system completion powers on, dsp chip meeting are had cured in the external FLASH of dsp chip
Automatic load dsp chip drives file.
Step S404, the dsp chip complete initialization according to the control signal that the fpga chip 1300 is sent.
Dsp chip first has to be initialized before load document, and fpga chip 1300 sends control signal and controls DSP core
Piece is initialized.
Step S405, function selecting module 1100 send control instruction.
Function selecting module 1100 can carry out function and select and set configuration parameter and generate control instruction.It is corresponding different
Function load file destination it is different, therefore the corresponding file destination title of each function.
Step S406, main control module 1200 receive control instruction.
The received control instruction of main control module 1200 includes file destination title, configuration parameter and dsp chip ID.Its
In, the title of the entitled file for being loaded into dsp chip of file destination, configuration parameter is to hold after dsp chip loads file destination
Configuration parameter when row corresponding function, dsp chip ID are the dsp chip ID for loading file destination.
Step S407, main control module 1200 parse the control instruction, obtain the target for including in the control instruction
The title of file.
Step S408, main control module 1200 select waveform application component 1201 according to the title of the file destination.
The different function choosing-items that function selecting module 1100 provides correspond to different file destinations, waveform application component
1201 be the software module with the function choosing-item phase mapping provided in function selecting module 1100, corresponding with each function choosing-item
There is a waveform application component 1201, main control module 1200 selects corresponding waveform application component according to the title of file destination
1201。
Step S409, the waveform application component 1201 find apparatus assembly according to dsp chip ID in the control instruction
1202 and the control instruction is sent to the apparatus assembly 1202.
Apparatus assembly 1202 is the software module with dsp chip phase mapping.It is corresponding with each dsp chip to have an equipment
Component 1202.Waveform application component 1201 selects corresponding apparatus assembly 1202 according to the title of file destination.
Step S410, the apparatus assembly 1202 receive the control instruction.
Step S411, the apparatus assembly 1202 call PCI driving to read the file destination according to the control instruction,
And the file destination is sent to fpga chip 1300.
Apparatus assembly 1202 calls PCI driving to read file destination, and the corresponding PCI of DSP is written in file destination by PCI driving
In address, and file destination is sent to fpga chip 1300.File destination is stored in the external DDR of dsp chip.PCI drives
It is dynamic to be comprised in the vxworks operating system run by main control module 1200.Step S412, the fpga chip 1300 load
The file destination is to the corresponding dsp chip of the dsp chip ID.
Control instruction includes dsp chip ID, and the dsp chip ID that fpga chip 1300 includes according to control instruction is literary by target
Part is loaded onto corresponding dsp chip.
After executing the load of an above-mentioned steps file destination of completion.System latency function selecting module 1100 sends control
System instruction, when function selecting module 1100 makes function switch, then follow the steps S406 and later the step of, complete DSP
The dynamically load of chip file.
Method provided in this embodiment may be implemented to dsp chip file dynamically load, and whole process, which does not need to restart, to be added
It carries, improves the loading efficiency of file, improve the flexibility and compatibility of system, it is low to reduce system cost.
It should be understood that the invention is not limited to the process and structure that are described above and are shown in the accompanying drawings,
And various modifications and changes may be made without departing from the scope thereof.The scope of the present invention is only limited by the attached claims
System.
Claims (10)
1. a kind of system for the load of DSP chip file characterized by comprising a master control molding
Block, a field programmable gate array FPGA chip and multiple digital signal processor DSP chips；
The main control module is connected with the fpga chip using compact Peripheral Component Interconnect standard cpci bus；
The main control module, for receiving control instruction and according to the title invocation target of file destination in the control instruction
File simultaneously loads the file destination to the fpga chip；
Wherein, the main control module includes: software communication System Framework SCA middleware, cpci bus based on CORBA specification
Interface and operating system；
The SCA middleware based on CORBA specification includes waveform application component and apparatus assembly；
The operating system includes Peripheral Component Interconnect standard PCI driving；
The waveform application component, for finding the apparatus assembly according to dsp chip mark ID in the control instruction and inciting somebody to action
The control instruction is sent to the apparatus assembly；
The apparatus assembly, for calling the PCI driving to read the file destination；
The PCI driving, for the file destination to be sent to the fpga chip；
The fpga chip loads the file destination to the multiple dsp chip for guiding；
The waveform application component and the apparatus assembly pass through the interface communication that standardizes based on CORBA；
The apparatus assembly is additionally coupled to the cpci bus interface, and passes through the cpci bus interface and the cpci bus
Connection；
Pass through hyperlink Hyper Link interface inter-link between the multiple dsp chip.
2. the system as claimed in claim 1, which is characterized in that each external flash memory FLASH of the dsp chip and one it is double
Times rate synchronous DRAM DDR has cured dsp chip driving file, in the FPGA in the FLASH
Chip provides the initialization of load completion dsp chip after control signal by universal input/output GPIO interface；The DDR is used
In the storage file destination.
3. the system as claimed in claim 1, which is characterized in that the multiple dsp chip is two dsp chips.
4. the system as claimed in claim 1, which is characterized in that dsp chip ID is used for each dsp chip in the control instruction
It distinguishes, comprising: device number, or, device number and manufacturer number.
5. a kind of method for the load of DSP chip file characterized by comprising
Main control module receives control instruction；
The main control module parses the control instruction, obtains the title for the file destination for including in the control instruction；
The main control module selects waveform application component according to the title of the file destination；
The waveform application component finds apparatus assembly according to the dsp chip ID for including in the control instruction and transmits the control
System instruction；
The apparatus assembly receives the control instruction of the waveform application component transmitting；
The apparatus assembly calls PCI driving to read the file destination according to the title of file destination in the control instruction；
The file destination is sent to fpga chip by the PCI driving；
The fpga chip loads the file destination to the corresponding dsp chip of the dsp chip ID.
6. method as claimed in claim 5, which is characterized in that dsp chip ID is used for each dsp chip in the control instruction
It distinguishes, comprising: device number, or, device number and manufacturer number.
7. method as claimed in claim 5, which is characterized in that the file destination is stored in the external DDR of the dsp chip
It is interior.
8. method as claimed in claim 5, which is characterized in that the file destination is sent to FPGA core by the PCI driving
Piece includes:
The file destination is written in the corresponding PCI address of the dsp chip ID for the PCI driving；
The PCI driving sends the file destination to the fpga chip.
9. method as claimed in claim 5, which is characterized in that before function selecting module sends control instruction further include:
The fpga chip is powered on；
To the function selecting module, the main control module and the dsp chip are powered on.
10. method as claimed in claim 9, which is characterized in that further include:
The dsp chip driving file that the dsp chip load is solidificated in the external FLASH of the dsp chip；
The dsp chip completes initialization according to the control signal that the fpga chip is sent.
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| CN201710364532.7A CN107168744B (en) | 2017-05-22 | 2017-05-22 | System and method for the load of DSP chip file |
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| CN201710364532.7A CN107168744B (en) | 2017-05-22 | 2017-05-22 | System and method for the load of DSP chip file |
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| CN108737529B (en) * | 2018-05-11 | 2021-11-19 | 湖南理工学院 | SCA waveform control method, apparatus, computer device and storage medium |
| CN110858254A (en) * | 2018-08-22 | 2020-03-03 | 北京芯愿景软件技术股份有限公司 | Safety chip |
| CN111666105B (en) * | 2019-03-08 | 2021-07-16 | 中国科学院长春光学精密机械与物理研究所 | Program storage and guide system and method based on DSP and FPGA |
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| CN103218338B (en) * | 2013-03-19 | 2015-10-07 | 中国科学院声学研究所 | The real-time many DSP debug system of a kind of signal processor system |
| CN103399771A (en) * | 2013-08-12 | 2013-11-20 | 中国航空无线电电子研究所 | Multi-DSP bootstrapping loading system based on serial high-speed interface bus and method thereof |
| CN103823698A (en) * | 2014-02-27 | 2014-05-28 | 四川九洲电器集团有限责任公司 | Method and device for programming and starting FPGA target program and DSP target program |
| CN106528203B (en) * | 2016-10-10 | 2019-10-18 | 上海无线电设备研究所 | A kind of automated procedures programming method of multi-DSP chip |
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