CN107168298A - Ladder diagram dynamic analysis method - Google Patents
Ladder diagram dynamic analysis method Download PDFInfo
- Publication number
- CN107168298A CN107168298A CN201710532356.3A CN201710532356A CN107168298A CN 107168298 A CN107168298 A CN 107168298A CN 201710532356 A CN201710532356 A CN 201710532356A CN 107168298 A CN107168298 A CN 107168298A
- Authority
- CN
- China
- Prior art keywords
- node
- ladder diagram
- instruction element
- instruction
- nodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B23/00—Testing or monitoring of control systems or parts thereof
- G05B23/02—Electric testing or monitoring
- G05B23/0205—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults
- G05B23/0218—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterised by the fault detection method dealing with either existing or incipient faults
- G05B23/0243—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterised by the fault detection method dealing with either existing or incipient faults model based detection method, e.g. first-principles knowledge model
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/24—Pc safety
- G05B2219/24065—Real time diagnostics
Abstract
The invention discloses a kind of ladder diagram dynamic analysis method, it is characterised in that：Ladder diagram storage organization based on two-dimensional chain table, the structure includes the step chained list and instruction element node linked list of the step of storage ladder diagram and instruction element respectively, and step chained list is that single-track link table, instruction element node linked list are doubly linked list, and its detailed step is as follows：From top to bottom, step is scanned from left to right, according to the logical relation that interelement computing is instructed in ladder diagram, if series relationship between two instruction elements, using AND node as their father nodes；If parallel relationship between two instructions, their father node is defined for OR nodes.Ladder diagram can be converted into two-dimensional chain table data structure storage by the present invention, trapezoid figure program is converted to instruct as leaf node, connection in series-parallel relation for father node logic binary tree intermediate form, with it is simple, efficient the characteristics of.
Description
Technical field
The invention belongs to technical field of industrial control, a kind of ladder diagram dynamic analysis method is concretely related to.
Background technology
With the formulation and implementation of industrial control field IEC61131-3 standards, SoftPLC technology is because of its versatility, cost performance
High, program portability is strong and programs the features such as facilitating and receives much attention, and research and development Soft- PLC system has very important significance.
The control logic of Soft- PLC system, which is realized, mainly two ways：(1) the Soft- PLC emulation based on instruction catalogue.Ladder diagram is first translated
Into instruction catalogue program, realize that procedure simulation is performed by the compiling to instruction catalogue.(2) trapezoid figure program parsing emulation.According to ladder
Shape figure logic is performed by scanning simulated program to ladder diagram.In order to coordinate the Soft- PLC editor's development system run on PC,
Design and develop Soft- PLC compiling system.In the prior art, it have studied the instruction catalogue Syntax Design process of Soft- PLC program, although
Soft- PLC emulation mode based on instruction catalogue is the method that most of Soft- PLC systems are used now, but this method needs are to instruction
Every instruction definition corresponding function of table, realization are complicated.Analysis mode scan round ladder diagram is directly carried out to ladder diagram, passed through
Contact judges its series and parallel relation between decision instruction and step, and algorithm performs are less efficient, to hardware requirements such as CPU and internal memories
It is higher.
The content of the invention
A kind of simple, efficient ladder diagram based on two-dimensional chain table is provided it is an object of the invention to overcome disadvantages mentioned above
Storage organization, the ladder diagram dynamic analysis method of scanning parsing ladder diagram topological sum logical relation.
A kind of ladder diagram dynamic analysis method of the present invention, wherein：Ladder diagram storage organization based on two-dimensional chain table, the knot
Structure includes the step chained list and instruction element node linked list of the step of storage ladder diagram and instruction element respectively, and its detailed step is such as
Under：
Step 1：From top to bottom, step is scanned from left to right, if it is 1 that instruction element is follow-up, is just scanned backward always, until
It was found that when the follow-up chained list of instruction element is more than 1, the follow-up chained list of recording instruction element, if scanned instruction element node is many
It is individual, often scan to two with regard to a newly-built AND node, be the father node of two instruction element node linked list nodes；Newly-built this
Individual AND node continues to participate in construction binary tree, is used as postorder AND node；
Step 2：Since multiple nodes of record, step 1 is performed, until finding that the follow-up of instruction element is 1, and after
After instruction element forerunner to be multiple, parallel branch terminates；
Step 3：From top to bottom, every newly-built OR node of two branch roads, is two parallel branches to instruction element chained list
Father node, newly-built OR nodes continue to participate in construction binary tree, are used as the child node of postorder OR nodes；
Step 4：OR nodes after whole parallel branch construction complete are used as the node operated before child node and parallel branch
Step 1 is continued executing with as child node；
Step 5：Terminate if all steps travel through completion, otherwise go to step 1.
Above-mentioned ladder diagram dynamic analysis method, wherein:Step chained list in the ladder diagram storage organization of the two-dimensional chain table
It is doubly linked list for single-track link table, instruction element node linked list.
The present invention is compared with prior art, with obvious beneficial effect, from above scheme, described two-dimentional chain
The ladder diagram storage organization of table, the structure includes the step of storage ladder diagram respectively and the step chained list of instruction element and instruction member
Part node linked list, wherein step chained list are that single-track link table, instruction element node linked list are doubly linked list, before each instruction element
Drive and follow-up relation can determine the series and parallel relation between instruction element.In specific steps, transported according between instruction in ladder diagram
The logical relation of calculation, if series relationship between two instructions, using AND node as their father nodes, first instruction of expression
As a result output is the input of second node, and the operation result of the forerunner of instruction can produce influence to follow-up operation；Two fingers
If parallel relationship between order, their father node is defined for OR nodes, and the output result of two instruction nodes carries out "or" fortune
The result of calculation is the input of node behind them, and the inclusive-OR operation of the result on the road of multiple parallel connections is the output on the road of parallel connection, from
And ladder diagram is compiled into logic Binomial Trees using binary tree principle, ladder diagram is converted to instruct as leaf node, go here and there simultaneously
Connection relation is the logic binary tree of father node.
In a word, ladder diagram can be converted into two-dimensional chain table data structure storage by the present invention, by trapezoid figure program be converted to
Instruct as leaf node, connection in series-parallel relation for the logic binary tree of father node intermediate form.
Below by way of embodiment, beneficial effects of the present invention are further illustrated.
Brief description of the drawings
Fig. 1 is ladder diagram data storage structural representation of the invention；
Fig. 2 is the trapezoid figure program example in embodiment；
Fig. 3 is converted to the process schematic of binary tree for the ladder diagram in embodiment；
Fig. 4 is the step condition schematic diagram in embodiment；
Fig. 5 parses schematic diagram for the piecemeal of logical relation in the binary tree in embodiment；
Fig. 6 is the logic operation outside control flow chart and clock timing diagram in embodiment；
Fig. 7 be embodiment in control logic ladder diagram example；
Fig. 8 is the logic binary tree intermediate form parsing in embodiment；
Four practice conditions of DIU modules that Fig. 9 monitors for the oscillograph in embodiment.
Embodiment
Below in conjunction with accompanying drawing and preferred embodiment, to specific according to a kind of ladder diagram dynamic analysis method proposed by the present invention
Embodiment, feature and its effect, are described in detail as after.
As shown in figure 1, a kind of ladder diagram dynamic analysis method of the present invention, wherein：Ladder diagram based on two-dimensional chain table is deposited
Storage structure, the structure includes the step chained list and instruction element node linked list of the step of storage ladder diagram and instruction element respectively,
Step chained list is that single-track link table, instruction element node linked list are doubly linked list, and its detailed step is as follows：
Step 1：From top to bottom, step is scanned from left to right, if it is 1 that instruction element is follow-up, is just scanned backward always, until
It was found that when the follow-up chained list of instruction element is more than 1, the follow-up chained list of recording instruction element, if scanned instruction element node is many
It is individual, often scan to two with regard to a newly-built AND node, be the father node of two instruction element node linked list nodes；Newly-built this
Individual AND node continues to participate in construction binary tree, is used as postorder AND node；
Step 2：Since multiple nodes of record, step 1 is performed, until finding that the follow-up of instruction element is 1, and after
After instruction element forerunner to be multiple, parallel branch terminates；
Step 3：From top to bottom, every newly-built OR node of two branch roads, is two parallel branches to instruction element chained list
Father node, newly-built OR nodes continue to participate in construction binary tree, are used as the child node of postorder OR nodes；
Step 4：OR nodes after whole parallel branch construction complete are used as the node operated before child node and parallel branch
Step 1 is continued executing with as child node；
Step 5：Terminate if all steps travel through completion, otherwise go to step 1.
1 ladder diagram node store structure design
Ladder diagram is made up of two kinds of elements of step and instruction element, and 1 ladder diagram is made up of multiple steps, and each step can
Include multiple different instruction elements.The trapezoidal illustrated example of certain control logic of Fig. 2, it includes two steps, first step
On to house between 3 elements, element be series relationship, the 2nd step includes 6 elements, have on sub- step one group it is parallel
Circuit.Forerunner and follow-up relation in view of each instruction element can determine the series and parallel relation between instruction element, therefore adopt
Ladder diagram is stored with two-dimensional chain table.
Step is represented with Rung in ladder diagram, and instruction element node is represented with node, and each node is included before one
Pointer chained list and heir pointer chained list are driven, they store forerunner's element and follow-up element respectively, in addition element into ladder diagram
When, the forerunner of element and follow-up relation are added in their chained list.With in addition between different steps in ladder diagram
One-dimensional chained list realize.The step chained list of the data structure of ladder diagram is single-track link table, and instruction element chained list is doubly linked list.
Fig. 1 is the two-dimensional chain table data structure schematic diagram of designed storage ladder diagram.For two-dimensional chain table, its each node types are
Identical.1 node data message of acquisition, which must be traveled through first, finds the affiliated step of node, then in the corresponding doubly linked list of step
Dotted line illustrates searching route in middle lookup node information, Fig. 1.The two-dimensional chain table rank of advanced units is searched for, then enters every trade search, its
The time complexity of lookup is O (mn).
The ladder diagram dynamic analysis of 2 logic-based binary trees
Ladder diagram is compiled according to order from top to bottom, from left to right, and each instruction element is one in ladder diagram
Node, each has the step of sequence, may be converted into the binary tree of an ordered arrangement, so whole ladder diagram just can be with
The binary tree forest of a piece of ordered arrangement is expressed as, by the postorder traversal to every binary tree, obtains one-to-one therewith
Character instruction collection.According to the logical relation of computing between instruction in ladder diagram, if series relationship between two instructions, saved with AND
Point is their father nodes, and the result output for representing first instruction is the input of second node, the operation knot of the forerunner of instruction
Fruit can produce influence to follow-up operation；If parallel relationship between two instructions, their father node is defined for OR nodes, two
The output result of individual instruction node carries out input of the result of inclusive-OR operation for node behind them, the result on the road of multiple parallel connections
Inclusive-OR operation be parallel connection road output.Based on this understanding, design traversal ladder diagram obtains the algorithm steps of logic binary tree
It is rapid as follows：
Step 1：From top to bottom, step is scanned from left to right, if it is 1 that element is follow-up, is just scanned backward always, until finding
When the follow-up chained list of instruction element is more than 1, the follow-up chained list of recording instruction element, if scanned node is multiple, is often scanned to two
An individual just newly-built AND node, is the father node of two nodes；This newly-built AND node continues to participate in construction binary tree, makees
For the child node of postorder AND node (if any).Than if any three nodes, solution is, the first two node newly-built one
Individual AND node, then an AND node is built, it is the father node of AND node and the 3rd node just now.
Step 2：Since multiple chained list nodes of record, step 1 is performed, until finding that the follow-up of element is 1, and after
After element forerunner to be multiple, parallel branch terminates.
Step 3：From top to bottom, every newly-built OR node of two branch roads, is the father node of two parallel branches, newly to chained list
The OR nodes built continue to participate in construction binary tree, are used as the child node of postorder OR nodes (if any).
Step 4：OR nodes after whole parallel branch construction complete are used as the node operated before child node and parallel branch
Step 1 is continued executing with as child node.
Step 5：Terminate if all steps travel through completion, otherwise go to step 1.
According to above-mentioned steps, Fig. 3 is that the 2nd step of Fig. 2 becomes the expression after binary tree.It is by first terraced first
One element XIC generates first leafy node, then encounters parallel relationship and obtains (b) and (c) two subtrees, embodies this
(d) is obtained after parallel relationship.(d) this overall and the 1st node XIC is series relationship, therefore is obtained after embodiment series relationship
(e).Last GEQ and (e) are series relationships, and then obtain the complete tree that (f) such one embodies a step.
When ladder diagram is run, trigger event is needed to give the input of rungInput parameter identifications step in above-mentioned algorithm,
RungOutput parameter identifications step is exported.Step condition schematic diagram is as shown in Figure 4.Controller is according to instruction step input condition
RungInput and associated variable execute instruction logic function, control logic computing produce a logical value output after terminating
(true or false), is used as the input of next instruction element.All dependent instructions in step are performed successively in this manner.
Each ladder in the tree-like intermediate code form that the execution of ladder diagram logic is translated into according to graphical analysis layer, ladder diagram
Level is that different steps in logic binary tree, whole step is stored in the way of forest, and the execution of trapezoid figure program need to be from
Every binary tree in top to bottm order parsing binary tree forest.Fig. 5 be ladder diagram parallel connection and serial connection relation step output with it is defeated
Go out schematic diagram.The corresponding AND structures of binary tree are series relationships in ladder diagram, now regard the input of upper strata step as left subtree
Step input, first run left subtree, then inputted the output of the step of left subtree as the step of right subtree, then run right
Subtree, and the output of the step of right subtree is exported as the step of AND structures；The OR structures of binary tree are corresponding be in ladder diagram simultaneously
Connection relation, upper strata step is now inputted and inputted as the step of left subtree and right subtree, first runs left subtree, running right son
Tree, then mutually or afterwards the step as OR structures is exported using the step output of left and right subtree.
Ladder diagram analysis unit is allocated as that for a part for whole Soft- PLC system, trapezoid figure program is compiled into logic binary tree
Afterwards, clock cycle (being usually 200ms) circular flow that logic operation module is set according to user.Before logic operation starts,
System first carries out the scanning of a non-executing logic to all ladder diagrams.And inside each ladder diagram, prescan algorithm according to
From top to bottom, order from left to right scans each instruction successively, according to data layer data is read in during scanning, updates the data the number of plies
According to flow carry out.Fig. 6 (1) is control flow outside logic operation, and system is related to control operation sequential RunClock, controls number
According to sequential WriteBackClock is write back, control data backup sequential tri- clocks of BackUpClock, the relation of its three is such as schemed
Shown in 6 (2).
3 algorithm logic correctness instance analysis
Fig. 7, which is one, which to be had in the ladder diagram of series and parallel structure, ladder diagram, 9 relay elements, is set to X1~
X9, step input is true, and each instruction element exports a logical value after performing, and it is as follows with logical relation expression formula：Y
=X1&&((X2&&X3)||(X4&&X5))&&X6&&(X7||X8)&&X9。
It is as shown in Figure 8 that Fig. 7 is converted to logic binary tree structure with algorithm above.It is proved below based on logical expression
Correctness：
(1) there is left subtree in inorder traversal logic binary tree, root node AND node, father node stacking successively is found most left
Side subtree leaf node is X1, it is firstly added X1。
(2)X1Father node is AND node, X1The output of node is used as X1The input of the right subtree of father node, right subtree is same
Inorder traversal is carried out, left subtree implementing result is (X2&&X3), right subtree implementing result is (X4&&X5), detection father node is OR
Node, is ((X according to the whole implementing result of OR structure elucidations2&&X3)||(X4&&X5))。
(3)X1It is AND node with OR nodes father node, X can be obtained according to AND structure elucidations1ˉX5Node implementing result is
X1&&((X2&&X3)||(X4&&X5))。
(4) similarly obtain having performed X6Node logical expression formula is X1&&((X2&&X3)||(X4&&X5))&&X6。
(5)X7With X8Node father node is OR nodes, and their implementing results are (X7||X8)。
(6) it is hereby achieved that X1-X8Node implementing result logic is X1*((X2*X3)+(X4*X5))*X6*(X7+X8)。
(7) root node is judged for AND node, is performed AND structure elucidations and is obtained the logical expression of whole step for X1&&
((X2&&X3)||(X4&&X5))&&X6&&(X7||X8)&&X9。
To sum up, the trapezoidal graph traversal algorithm logical expression operation result of logic-based binary tree and ladder diagram from top to bottom,
From left to right order execution ladder diagram logic operation result is identical, and example demonstrates correctness of algorithm.
4 checkings and performance evaluation
Author realizes the data structure designed above and analytical algorithm with C Plus Plus, is applied on QT platforms
Soft- PLC system.The major function of Soft- PLC system has object configuration function, hardware configuration function, and (module configuration, module write value/point
Mapping, port configuration etc.), control logic and tactful programmed function (establishment of ladder diagram, realize control to controlled device) and
Data analysis function etc..The embedded core controller for Soft- PLC system that what the auxiliary equipment used was researched and developed for seminar be mounted with,
1 oscillograph, 1 PC.Test is based primarily upon Black-box Testing method, and combines load testing method.
4.1 functional tests are tested
Design ladder diagram and control 6 DIU modules, 6 DIU modules distinguish carry on the different serial ports of core controller,
Each module uses 4 DO points, altogether 24 points.First module, first DO point is lighted, and returns to a value, and the value is used as the
The output condition of two points；After the second execution logic, return one value, the value as the 3rd point output condition；According to
This analogizes, after 24 points are all exported, while extinguishing 24 points, iterative cycles.
State conversion time is poor between four points of table 1DIU modules
Fig. 9 is four practice conditions of DIU modules that oscillograph is monitored, this shows that performed control logic is correct.
In the case where the system scan period is 100ms, state conversion time is as shown in table 1 between 10 DIU modules, four points, wherein
T1、T2、T3、T4Respectively DO1 to DO2, DO2 to DO3, DO3 to DO4, DO4 to DO1 state conversion time.It was found from data,
Each DIU module dotted state conversion times are in the range of 95-105ms, and the system scan period is 100ms, therefore it may be speculated that
System performs the time in 0-10ms, and this meets the requirement of the response time of energy-saving control system.4.2 robustness test experiments
Test environment is the traffic lights control logic built with DIU, and software uses (SuSE) Linux OS.Test system is set
The standby bi-colour light for including 12 24V, 6 DIU modules, PC 1.Operation result is shown：
1) the comprehensive instantiation carried out 45 days by a definite date is tested, step, bit manipulation instruction used in runtime, timing
Device/counter instruction, compare instruction, calculating/arithmetic instruction, transmission/logical order, program control instruction, circulation/termination and refer to
Make, the instruction of customized fuzzy can be parsed correctly, realize stable control targe.The interrupt response of actual test
Time is 23ms to the maximum, and minimum time is 20.5ms, and this time is that system field data of finishing is saved in file and out of service
Test to the time.
2) obvious above-mentioned interrupt response is than larger.Seminar's deep study and analysis time overhead is found, used in test system
To communications device data refresh on required for time be 20ms.Meanwhile, control logic is replicated to 10 times, 100 times respectively
With 1000 times to complicate control logic, test result is found, the time required for the interruption system of actual measurement is not because control
The increase of complexity processed, this explanation system service the executions time dependent on control logic number, system is in logic solution
The time united during analysis in completion system is foreseeable, i.e., actual response time is less than or equal to 3ms.
In a word, with the formulation and implementation of industrial control field IEC61131-3 standards, SoftPLC technology is developed rapidly, greatly
Amount is applied to industrial control field.The present invention is directed to the core component ladder diagram operation in system, the logic-based provided
The logic control implementing result of the ladder diagram intermediate form of binary tree complies fully with ladder diagram from top to bottom, from left to right sequentially holds
Row logic, this resolving simplifies the Soft- PLC simulation process based on instruction catalogue, while avoiding directly scanning ladder diagram emulation
The defect of process scan round complicated process structure, has a good application prospect.
The above described is only a preferred embodiment of the present invention, not making any formal limitation to the present invention, appoint
What is without departing from technical solution of the present invention content, and what the technical spirit according to the present invention was made to above example any simply repaiies
Change, equivalent variations and modification, in the range of still falling within technical solution of the present invention.
Claims (2)
1. a kind of ladder diagram dynamic analysis method, it is characterised in that：Ladder diagram storage organization based on two-dimensional chain table, the structure bag
The step chained list and instruction element node linked list of the step of storage ladder diagram and instruction element respectively are included, its detailed step is as follows：
Step 1：From top to bottom, step is scanned from left to right, if it is 1 that instruction element is follow-up, is just scanned backward always, until finding
When the follow-up chained list of instruction element is more than 1, the follow-up chained list of recording instruction element, if scanned instruction element node is multiple, often
Scan to two with regard to a newly-built AND node, be the father node of two instruction element node linked list nodes；This newly-built AND
Node continues to participate in construction binary tree, is used as postorder AND node；
Step 2：Since multiple nodes of record, step 1 is performed, until finding that the follow-up of instruction element is 1, and follow-up finger
It is multiple to make the forerunner of element, and parallel branch terminates；
Step 3：From top to bottom, every newly-built OR node of two branch roads is father's section of two parallel branches to instruction element chained list
Point, newly-built OR nodes continue to participate in construction binary tree, are used as the child node of postorder OR nodes；
Step 4：OR nodes after whole parallel branch construction complete are used as the node conduct operated before child node and parallel branch
Child node continues executing with step 1；
Step 5：Terminate if all steps travel through completion, otherwise go to step 1.
2. ladder diagram dynamic analysis method as claimed in claim 1, it is characterised in that:The ladder diagram of the two-dimensional chain table is deposited
Step chained list is that single-track link table, instruction element node linked list are doubly linked list in storage structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710532356.3A CN107168298A (en) | 2017-07-03 | 2017-07-03 | Ladder diagram dynamic analysis method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710532356.3A CN107168298A (en) | 2017-07-03 | 2017-07-03 | Ladder diagram dynamic analysis method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107168298A true CN107168298A (en) | 2017-09-15 |
Family
ID=59827879
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710532356.3A Pending CN107168298A (en) | 2017-07-03 | 2017-07-03 | Ladder diagram dynamic analysis method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107168298A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019128150A1 (en) * | 2017-12-25 | 2019-07-04 | 北京创昱科技有限公司 | Control flow processing method and apparatus, and electronic device and storage medium |
| CN112327744A (en) * | 2020-11-20 | 2021-02-05 | 深圳市海浦蒙特科技有限公司 | Method for interconverting ladder diagram and instruction list for programmable logic controller |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1588256A (en) * | 2004-09-23 | 2005-03-02 | 艾默生网络能源有限公司 | Method and system for changing ladder diagram program into instruction listing program |
| CN101364098A (en) * | 2008-09-12 | 2009-02-11 | 南京航空航天大学 | Method and system for conversing trapezoidal pattern to be instruction catalogue program, and interpretation execution method and system |
| CN101369234A (en) * | 2008-06-24 | 2009-02-18 | 杭州电子科技大学 | Method for compiling ladder diagram language into instruction list language according to IEC61131-3 standard |
| CN104331314A (en) * | 2014-10-31 | 2015-02-04 | 郑州众智科技股份有限公司 | Method for converting PLC (Programmable Logic Controller) ladder diagram into instruction list based on generator set controller |
-
2017
- 2017-07-03 CN CN201710532356.3A patent/CN107168298A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1588256A (en) * | 2004-09-23 | 2005-03-02 | 艾默生网络能源有限公司 | Method and system for changing ladder diagram program into instruction listing program |
| CN101369234A (en) * | 2008-06-24 | 2009-02-18 | 杭州电子科技大学 | Method for compiling ladder diagram language into instruction list language according to IEC61131-3 standard |
| CN101364098A (en) * | 2008-09-12 | 2009-02-11 | 南京航空航天大学 | Method and system for conversing trapezoidal pattern to be instruction catalogue program, and interpretation execution method and system |
| CN104331314A (en) * | 2014-10-31 | 2015-02-04 | 郑州众智科技股份有限公司 | Method for converting PLC (Programmable Logic Controller) ladder diagram into instruction list based on generator set controller |
Non-Patent Citations (1)
| Title |
|---|
| 杨观赐等: "面向智能控制的软PLC中梯形图的动态解析方法", 《贵州大学学报》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019128150A1 (en) * | 2017-12-25 | 2019-07-04 | 北京创昱科技有限公司 | Control flow processing method and apparatus, and electronic device and storage medium |
| CN112327744A (en) * | 2020-11-20 | 2021-02-05 | 深圳市海浦蒙特科技有限公司 | Method for interconverting ladder diagram and instruction list for programmable logic controller |
| CN112327744B (en) * | 2020-11-20 | 2021-10-22 | 深圳市海浦蒙特科技有限公司 | Method for interconverting ladder diagram and instruction list for programmable logic controller |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104965788B (en) | A kind of code static detection method | |
| CN107193745B (en) | Automated construction method of the PLC program to NuSMV input model | |
| CN104503917A (en) | Method and system for analyzing change impact domain based on data flow function invoking path | |
| CN102508780A (en) | Crossed dynamic software testing method and device | |
| EP3387525B1 (en) | Learning from input patterns in programing-by-example | |
| CN113672515A (en) | WASM intelligent contract vulnerability detection method based on symbolic execution | |
| Buinevich et al. | Method for partial recovering source code of telecommunication devices for vulnerability search | |
| CN107168298A (en) | Ladder diagram dynamic analysis method | |
| CN108037913A (en) | A kind of conversion method of xUML4MC models to MSVL LISP program LISPs, computer program | |
| CN103646194B (en) | A kind of credible sort method of the synchrodata string routine based on Formal Verification | |
| CN103455672B (en) | A kind of FPGA emulation testing use-case automatization homing method | |
| CN110457070A (en) | Verification method and device and Related product | |
| CN106021109A (en) | Automatic frame model for program structure analysis | |
| CN104461890A (en) | Qt program memory using static test method for air traffic control training system | |
| Li et al. | Recursive modeling of stateflow as input/output-extended automaton | |
| CN102760085B (en) | Communication track expanding method and device, communication track drive simulation method and system | |
| Chen et al. | Implementation of a symbolic circuit simulator for topological network analysis | |
| Banerjee | Advances in model-based testing of GUI-based software | |
| Romanov et al. | Representing programs with dependency and function call graphs for learning hierarchical embeddings | |
| CN1294495C (en) | Simulator structure method | |
| CN104657542B (en) | A kind of Petri net model detection method based on MSVL | |
| Chen et al. | Baton: symphony of random testing and concolic testing through machine learning and taint analysis | |
| CN103914380B (en) | Boundary value test method in structured testing and system thereof | |
| Dong et al. | Build your own model checker in one month | |
| Su et al. | STCG: state-aware test case generation for simulink models |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20170915 |
|
| WD01 | Invention patent application deemed withdrawn after publication |