CN107133081B - instruction dispatching method and interpreter - Google Patents
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- CN107133081B CN107133081B CN201610109699.4A CN201610109699A CN107133081B CN 107133081 B CN107133081 B CN 107133081B CN 201610109699 A CN201610109699 A CN 201610109699A CN 107133081 B CN107133081 B CN 107133081B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
- G06F9/45516—Runtime code conversion or optimisation
Abstract
the invention provides an instruction dispatching method and an interpreter. The method comprises the following steps: after receiving a first virtual machine instruction, acquiring column offset of the first virtual machine instruction on an instruction dispatch table according to the output type of a second virtual machine instruction; acquiring a row offset of the first virtual machine instruction on an instruction dispatch table according to an operation code of the first virtual machine instruction, and storing the row offset in a row index register; encoding a base address register for storing a first address of an instruction dispatch table, a row index register and a column offset into a memory access instruction; and when the memory access instruction is executed, acquiring the address of an instruction template required by the execution of the first virtual machine instruction at the address determined by the first address, the row offset and the column offset, and jumping to the address of the instruction template to finish instruction dispatching. Therefore, the acquisition of the head address of the line is avoided in the instruction dispatching process, the loading speed of the address of the instruction template is increased, and the instruction dispatching efficiency is improved.
Description
Technical Field
the present invention relates to hardware architecture, and more particularly, to an instruction dispatching method and interpreter.
Background
A Virtual Machine (VM) is a Virtual Machine that is virtualized by software or a method supported by a small amount of hardware, and a set of instruction sets, called a Virtual Machine instruction set, is usually provided in the Virtual Machine. A virtual machine typically interprets execution of a given sequence of virtual machine instructions on a local physical machine by an interpreter. The efficiency with which the interpreter interprets and simulates execution of virtual machine instructions often determines the startup performance and response speed of the virtual machine system. Therefore, deep analysis and optimization of the interpreter are of great significance for optimizing the design of the virtual machine and improving the performance of the system.
The basic flow of the existing interpreter for interpreting and executing the virtual machine instruction mainly includes: instruction fetching, instruction dispatching, operand fetching, and execution. The instruction fetching of the interpreter is used for receiving virtual machine instructions, each virtual machine instruction received by the interpreter corresponds to one instruction template, and each instruction template corresponds to one or more local machine instructions. When the interpreter interprets a virtual machine instruction, it needs to jump to the address of the instruction template corresponding to the virtual machine instruction, and then execute the corresponding local machine instruction in the address of the instruction template. When the interpreter finishes the interpretation and execution of the local machine instruction in the address of one instruction template, the interpreter needs to jump to the address of the instruction template corresponding to the next virtual machine instruction to continue to execute the interpretation of the virtual machine instruction. The process by which the interpreter jumps from the address of one instruction template to the address of another instruction template is referred to as the instruction dispatch process of the interpreter. In order to implement instruction dispatch, the address of an instruction template corresponding to each virtual machine instruction needs to be determined, and an instruction dispatch table is generally established according to the corresponding relationship between the instruction template and the virtual machine instruction in the existing method. And storing the addresses of all the instruction templates in the instruction dispatch table according to the output types and the difference of the operation codes of the virtual machine instructions corresponding to the instruction templates.
In the prior art, in each instruction dispatching process, an interpreter first obtains a head address of a line corresponding to a current virtual machine instruction in the instruction dispatching according to an output type of a last virtual machine instruction of the current virtual machine instruction, then obtains a column offset of the current virtual machine instruction in an instruction dispatching table according to an operation code of the current virtual machine instruction, and finally obtains an address of an instruction template corresponding to the current virtual machine instruction in the instruction dispatching table according to the head address of the line and the column offset, and the interpreter jumps to the address of the instruction template, thereby completing one instruction dispatching. In the working process of the existing interpreter, a row head address needs to be acquired every instruction assignment, and in order to acquire the row head address, a common 64-bit Microprocessor with interlocked pipeline stages (MIPS for short) reduced instruction set computer is taken as an example, 6-machine instruction needs to be executed to calculate the row head address in real time, and 11-machine instruction needs to be executed in one instruction assignment. Therefore, the acquisition overhead of the head address of the line in the existing instruction dispatching method is very high, so that the address loading speed of the instruction template is low, the instruction dispatching efficiency is reduced, and the execution efficiency of the interpreter and the virtual machine is low.
disclosure of Invention
The embodiment of the invention provides an instruction dispatching method and an interpreter, which are used for solving the problem of low instruction dispatching efficiency caused by low address loading speed of an instruction template in the existing instruction dispatching process.
an embodiment of the present invention provides an instruction dispatching method, including:
After a first virtual machine instruction is received, acquiring column offset of the first virtual machine instruction on the instruction dispatch table according to the output type of a second virtual machine instruction, wherein the second virtual machine instruction is a previous virtual machine instruction of the first virtual machine instruction; acquiring a row offset of the first virtual machine instruction on the instruction dispatch table according to an operation code of the first virtual machine instruction, and storing the row offset in a row index register;
Encoding a base register storing a first address of the instruction dispatch table, the row index register, and the column offset into a memory access instruction;
And when the memory access instruction is executed, acquiring the address of an instruction template required by the execution of the first virtual machine instruction at the address determined by the first address, the row offset and the column offset, and jumping to the address of the instruction template to finish instruction dispatching.
Another aspect of an embodiment of the present invention provides an interpreter, including:
A column offset obtaining module, configured to, after receiving a first virtual machine instruction, obtain a column offset of the first virtual machine instruction on the instruction dispatch table according to an output type of a second virtual machine instruction, where the second virtual machine instruction is a previous virtual machine instruction of the first virtual machine instruction;
A row offset obtaining module, configured to obtain a row offset of the first virtual machine instruction on the instruction dispatch table according to an opcode of the first virtual machine instruction, and store the row offset in a row index register;
the encoding module is used for encoding a base address register for storing a first address of the instruction dispatch table, the row index register and the column offset into a memory access instruction;
And the execution module is used for acquiring the address of an instruction template required by the execution of the first virtual machine instruction at the address determined by the first address, the row offset and the column offset when the memory access instruction is executed, and jumping to the address of the instruction template to finish instruction allocation.
The instruction dispatching method and the interpreter provided by the embodiment of the invention adopt the instruction dispatching table stored in the row according to the operation code of the virtual machine instruction and the output type of the virtual machine instruction in the column, store the initial address of the instruction dispatching table in the high-speed access storage component, simultaneously expand the access storage instruction supporting the 'base address + index + offset' addressing mode in the existing MIPS instruction set, and encode the base address register, the row index register and the column offset of the initial address of the storage instruction dispatching table corresponding to the virtual machine instruction to be interpreted and executed in the access storage instruction, so that the acquisition of the initial address of the row is avoided in the instruction dispatching process, the loading speed of the address of an instruction template is improved, the machine instruction to be executed is reduced, the instruction dispatching efficiency is improved, and the execution efficiency of the interpreter and the virtual machine is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive labor.
FIG. 1 is a diagram of a conventional instruction dispatch table;
FIG. 2 is a flowchart illustrating a first embodiment of an instruction dispatch method according to the present invention;
FIG. 3 is a block diagram of an instruction dispatch table according to a first embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a first embodiment of an interpreter according to the present invention.
Detailed Description
in order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The interpreter establishes an instruction dispatch table during initialization, and the instruction dispatch table is used for storing addresses of instruction templates corresponding to all virtual machine instructions. In an instruction dispatch table adopted in the existing instruction dispatch method, addresses of instruction templates are stored in different columns of the instruction dispatch table according to different operation codes of virtual machine instructions corresponding to the instruction templates, and the addresses of the instruction templates are stored in different rows of the instruction dispatch table according to different output types of the virtual machine instructions corresponding to the instruction templates. FIG. 1 is a diagram of a conventional instruction dispatch table. As shown in fig. 1, the rows of the instruction dispatch table are divided into 9 rows representing different types according to the output types of the virtual machine instructions, and the output types include: btos (byte type), cts (character type), stos (short integer type), itos (integer type), ltos (long integer type), ftos (single precision floating point type), dtos (double precision floating point type), tos (reference type data), vtos (no output type). The columns of the instruction dispatch table are divided into 256 columns according to the operation code of the virtual machine instruction according to the size of the computer instruction system. The instruction operation code includes: add, subtract, shift left, shift right, read, write, etc.
in order to reduce the number of machine instructions in the instruction dispatching process, and considering that the overhead of acquiring the head address of a line is the largest in the existing instruction dispatching process, an embodiment of the present invention provides a new instruction dispatching method, in which when an interpreter is initialized, the head address of the virtual machine instruction in the instruction dispatching table shown in fig. 1 is stored in a register, and 9 registers are required to store the head addresses corresponding to different output types. Therefore, in each instruction dispatching process, machine instructions do not need to be consumed to calculate and obtain the head of line address in real time, only when the head of line address needs to be used, the head of line address of the output type is read in the corresponding register according to the output type of the virtual machine instructions, and by taking a common 64-bit MIPS (million Instructions per second) simplified instruction set computer as an example, 6 machine instructions can be saved, and the efficiency of the instruction dispatching process is greatly improved. The improvement can obviously improve the efficiency of the instruction dispatching process, but the method occupies more resources due to the fact that 9 registers are occupied, and the number of the high-speed memory access registers in the computer system is usually small, so that the wide application of the method is influenced.
to avoid the above problem, an embodiment of the present invention provides an instruction dispatch method, in which only the first address of an instruction dispatch table is stored in a register, which is called a base register, and at this time, the location of the address of an instruction template in the instruction dispatch table is described by "first address + row offset + column offset". However, the conventional processor of the reduced instruction set such as MIPS only supports the addressing mode of "base address + offset", so at least two machine instructions are required to access the position in the instruction dispatch table described by the mode of "first address + row offset + column offset". In the conventional instruction dispatching method, after the row first address and the column offset are obtained, the row first address and the column offset are added to obtain a position in an instruction dispatching table, and then an address of an instruction template stored in the position is loaded by a memory access instruction, so that at least two machine instructions are required to access the position in the instruction dispatching table.
in the embodiment of the invention, in order to further improve the access speed of the instruction dispatch table, on the basis of the MIPS instruction set architecture of the existing processor, the access instruction is expanded, and the access instruction supporting the addressing mode of 'base address + index + offset' is newly introduced, wherein the 'base address' is the first address of the instruction dispatch table, and the 'index' and the 'offset' can be used for representing the row offset and the column offset of the virtual machine instruction in the instruction dispatch table. Therefore, the loading operation of the address of the instruction template can be finished only by one memory access instruction without executing an addition instruction, and the access speed of the memory address of 'base address + row offset + column offset' during instruction dispatching is directly improved.
However, in the MIPS reduced instruction set architecture employed by existing processors, the instruction encoding length is typically fixed to 32 bits. The memory access instruction supports only 16-bit offsets at maximum for encoding "row offset" and "column offset". In order to improve the access speed, the embodiment expands the access instruction, and the expanded access instruction needs to additionally use 5 bits for encoding the line index register for storing the line offset, so that no matter how the expanded access instruction is designed, the supported offset cannot exceed 11 bits (namely 16 bits-5 bits) at most. The column offset of the virtual machine instruction, when encoded into the memory access instruction, needs to be within an 11-bit encoding offset.
If the existing instruction dispatch table is still used, for example, when the value range of the operation code is 0 to 255 and the value range of the output type of the virtual machine instruction is 0 to 8, the range of the line offset of the virtual machine instruction is [0, 8 × 256 × address length × ]]the column offset ranges from 0, 255 Address Length]The address length is a preset value and represents the address length of the current processor, the unit of the address length is bytes, and the value of the address length is usually 4 or 8. When Address Length is 8, the range of row offsets is [0, 2 ]14]The range of column offsets is [0, 2 ]11-8]Therefore, the row offset with a larger range is stored in the index register, but the column offset with a relatively smaller offset still requires that the offset used for coding the column offset in the memory access instruction is not less than 12 bits and is larger than the 11-bit coding offset which can be provided by the extended memory access instruction. Therefore, the method for reducing machine instructions and improving instruction dispatch efficiency cannot be realized by adopting the conventional instruction dispatch table.
Therefore, in the instruction dispatching method provided by the embodiment of the invention, the rows and the columns of the original instruction dispatching table are also transposed. After the conversion, the address of the instruction template is stored in different rows of the instruction dispatch table according to the difference of the operation codes of the corresponding virtual machine instructions, and the address of the instruction template is pairedThe output types of the corresponding virtual machine instructions are stored in different columns of the instruction dispatch table. At this time, the column offset of the virtual machine instruction in the instruction dispatch table depends on the output type of the virtual machine instruction, the output types are 9, compared with 256 operation codes, the bit number of the column offset is greatly reduced, and when the Address Length is 8, the range of the column offset is [0, 26]at this time, only 7 bits of coding offset at most are needed to code the column offset.
therefore, it can be known from the above analysis that, in the instruction dispatching method provided in the embodiment of the present invention, the first address of the instruction dispatching table is stored in the base address register, and when an access instruction supporting a "base address + index + offset" addressing mode is newly introduced into the existing MIPS instruction set, the rows and columns of the existing instruction dispatching table are transposed, so that the first address of a row is prevented from being obtained in each instruction dispatching process, the access speed to the address in the instruction dispatching table is increased, and the instruction dispatching efficiency is further improved. The following describes the instruction dispatching method provided by the embodiment of the present invention in detail by using specific embodiments.
FIG. 2 is a flowchart illustrating a first embodiment of an instruction dispatching method according to the present invention. FIG. 3 is a block diagram of an instruction dispatch table according to a first embodiment of the present invention. The method embodiment provided by the invention can be executed by an instruction dispatching device, the device can be realized by software and/or hardware, and the device can be embedded into an interpreter in a terminal for realization. The terminal may be a processor-containing device such as a computer, a cell phone, etc. As shown in fig. 2, the instruction dispatching method in the embodiment of the present invention includes:
step 201, after receiving a first virtual machine instruction, acquiring a column offset of the first virtual machine instruction on an instruction dispatch table according to an output type of a second virtual machine instruction, wherein the second virtual machine instruction is a previous virtual machine instruction of the first virtual machine instruction; acquiring a row offset of the first virtual machine instruction on an instruction dispatch table according to an operation code of the first virtual machine instruction, and storing the row offset in a row index register;
Step 202, encoding a base address register, a row index register and a column offset for storing a first address of an instruction dispatch table into a memory access instruction;
And 203, when the memory access instruction is executed, acquiring the address of an instruction template required by the execution of the first virtual machine instruction at the address determined by the first address, the row offset and the column offset, and jumping to the address of the instruction template to finish instruction allocation.
As shown in fig. 3, the addresses of the instruction templates corresponding to the virtual machine instructions are stored in different rows of the instruction dispatch table according to different operation codes of the corresponding virtual machine instructions, and the addresses of the instruction templates are stored in different columns of the instruction dispatch table according to different output types of the corresponding virtual machine instructions.
The column offset and the row offset are not sequentially obtained in step 201, and the column offset may be obtained first, the row offset may be obtained first, or the processes of obtaining the column offset and the row offset may be performed in parallel. In step 201, according to the output type of the second virtual machine instruction, the column offset of the first virtual machine instruction on the instruction dispatch table is obtained, and the output type of the virtual machine instruction and the column offset are in a one-to-one correspondence relationship. The second virtual machine instruction is a last virtual machine instruction of the first virtual machine instruction, and the first virtual machine instruction is a virtual machine instruction to be executed. Since the output data of the previous virtual machine instruction is the input or operation object of the next virtual machine instruction, the column offset of the current virtual machine instruction is obtained according to the output type of the previous virtual machine instruction. Because the virtual machine instructions and the instruction templates have a one-to-one correspondence relationship, the positions of the virtual machine instructions in the instruction dispatch table are the storage positions of the addresses of the instruction templates in the instruction dispatch table, and the row offsets and the column offsets of the virtual machine instructions in the instruction dispatch table are the row offsets and the column offsets of the addresses of the instruction templates in the storage positions of the instruction dispatch table.
For example, in the process of acquiring the column offset, first, the serial number of the column occupied by the output type of the second virtual machine instruction in the instruction dispatch table is acquired; then, the column offset of the first virtual machine instruction on the instruction dispatch table is obtained according to the product of the sequence number and a preset value representing the address length of the processor. Specifically, the calculation formula of the column offset may be: column offset is a serial number × a preset value.
Meanwhile, according to the operation code of the first virtual machine instruction, the row offset of the first virtual machine instruction on the instruction dispatch table is obtained, and the row offset is stored in the row index register because the number of bits representing the row offset is large.
Illustratively, in the process of acquiring the line offset, an operation code of a first virtual machine instruction is acquired first; then, the row offset of the first virtual machine instruction on the instruction dispatch table is obtained according to the product of the total column number of the instruction dispatch table, the operation code and a preset numerical value representing the address length of the processor. Specifically, the calculation formula of the line offset may be: the row offset is the total column count × opcode × predetermined number.
Specifically, in step 202, a base register storing a first address of the instruction dispatch table, a row index register, and a column offset are encoded in the access instruction supporting an addressing mode of "base + index + offset", where the base register storing the first address of the instruction dispatch table corresponds to "base", the row index register storing the row offset corresponds to "index", and the column offset corresponds to "offset". Then, in step 203, when the access instruction is executed, the access instruction may directly access an address determined by "base address + row offset + column offset" encoded in the instruction, and obtain an address of an instruction template stored at the address and required for performing interpretation and execution on the first virtual machine instruction, and the interpreter jumps to the address of the instruction template to complete the instruction dispatching process.
The first address of the instruction dispatch table is stored in the base address register when the interpreter is initialized, and optionally, the first address may also be stored in other high-speed access memory components, such as a Content Addressable Memory (CAM) table.
The instruction dispatching method provided by the embodiment of the invention adopts the instruction dispatching table stored in the row according to the operation code of the virtual machine instruction and the output type of the virtual machine instruction in the column, stores the initial address of the instruction dispatching table in the high-speed access storage component, expands the access storage instruction supporting the 'base address + index + offset' addressing mode in the existing MIPS instruction set, and codes the base address register, the row index register and the column offset of the initial address of the storage instruction dispatching table corresponding to the virtual machine instruction to be explained and executed in the access storage instruction, so that the acquisition of the initial address of the row is avoided in the instruction dispatching process, the loading speed of the address of an instruction template is improved, the machine instruction to be executed is reduced, the instruction dispatching efficiency is improved, and the execution efficiency of an interpreter and a virtual machine is improved.
In order to improve the instruction dispatching efficiency, the instruction dispatching table can be further optimized on the basis of the above embodiments.
Specifically, as shown in fig. 3, the output types of the virtual machine instructions include: integer type, long integer type, single precision floating point type, double precision floating point type, reference type, and no output type. Illustratively, since the instruction template addresses of the btos output types and the instruction template addresses of the itos output types are the same as the instruction template addresses of the itos output types, when the instruction dispatch table structure in fig. 1 is transposed to the instruction dispatch table structure shown in fig. 3, entries related to the btos output types, the ctos output types and the stos output types are deleted, so as to reduce consumption of resources such as a memory.
Optionally, because the row offset in the prior art is obtained by using a total column number × an opcode × a preset value, multiplication in the row offset calculation process is complex, consumption is high, in order to simplify calculation of the row offset, at least one column of filling table entries may be added to the instruction dispatch table, contents stored in the filling table entries are empty, and the column number of the instruction dispatch table is raised to the power of 2 by increasing the column number of the filling table entries. Illustratively, as shown in FIG. 3, when the number of columns in the instruction dispatch table is 6, two columns of padding entries are added to expand the total number of columns in the instruction dispatch table to 8 columns, where 8 is the power of 4 of 2. I.e., adding two columns of fill entries at the end of the instruction dispatch table as shown in fig. 3.
On the basis of expanding the total column number of the instruction dispatch table to be 2 exponential power, when acquiring the row offset of the first virtual machine instruction on the instruction dispatch table, firstly acquiring the offset bit number according to the column number of the instruction dispatch table and a preset numerical value representing the address length of a processor; and moving the operation code of the first virtual machine instruction to the left by the offset digit to obtain the row offset of the first virtual machine instruction on the instruction dispatch table. Specifically, the product of the column number of the instruction dispatch table and the preset numerical value of the address length of the processor is obtained, and then the product is subjected to logarithm operation with the base 2 to obtain the offset digit number; then, the operation code of the first virtual machine instruction is shifted to the left by the offset bit number, and the row offset of the first virtual machine instruction on the instruction dispatch table is obtained. By expanding the total column number of the instruction dispatch table, the multiplication operation is changed into the displacement operation, thereby greatly improving the instruction dispatch efficiency.
it will be apparent to those skilled in the art that FIG. 3 is merely illustrative of one column arrangement and is not intended to limit the instruction dispatch table of the present invention. While FIG. 3 is an exemplary illustration of the filling table entry filling method after performing reduction and redundancy elimination on the entries of the instruction dispatch table, it is clear to those skilled in the art that the filling table entries may be directly added after the rows and columns of the instruction dispatch table shown in FIG. 1 are reversed, that is, 7 columns of filling table entries are added, so that the number of columns of the instruction dispatch table reaches 16 columns, that is, 4 times power of 2.
For example, if an address of an instruction template stored at a preset position labeled 15 rows and 15 columns in the instruction dispatch table shown in fig. 3 needs to be read, the preset position is described by "base address + row offset + column offset", the base address is a first address of the instruction dispatch table, and is also an address of a position labeled 0 rows and 0 columns in the instruction dispatch table, the row offset of the preset position indicates a distance between a row where the preset position is located and the first address, and the instruction dispatch table is stored in a manner that all rows are connected into one row in the order of row numbers from small to large during actual storage, so that the row offset of the preset position relative to the first address is 15 × the total column number × the preset value of the instruction dispatch table. The default value is usually 8, and when no padding column is added, the row offset is 15 × 6 × 8, and at this time, a binary multiplier needs to be called to obtain the row offset. After adding the padding columns, the row offset is 15 × 8 × 8, and at this time, when obtaining the row offset, it is considered that 8 × 8 performs a function of shifting 15 to the left by 6 bits in the binary multiplication, and the shift operation is fast and occupies less resources in the implementation process, so after adding the padding columns, it is only necessary to shift the operation code (i.e., 15) of the first vm instruction corresponding to the row where the preset position is located, i.e., the preset position, to the left by the offset number.
Further, on the basis of any of the above embodiments, the output types with higher access probability in the instruction dispatch process can be arranged at the adjacent positions of the instruction dispatch table, so as to enhance the locality of access and improve the access efficiency. Addresses of instruction templates corresponding to virtual machine instructions of the no-output type, the integer type, the reference type, and the single-precision floating-point type are stored in 4 consecutive columns of the instruction dispatch table. Illustratively, instruction dispatch tables are accessed with focused queries for the types vtos, itos, ato, and ftos output, so when designing an instruction dispatch table, the four types of entries vtos, itos, ato, and ftos are arranged in four adjacent columns as shown in FIG. 3.
The following describes the instruction dispatching method provided by the present invention in detail with respect to specific machine instruction codes as an example, which can reduce machine instructions.
In the existing MIPS instruction set computer, the prior art instruction dispatch process needs to execute the following 11 machine instructions in common:
Wherein, machine instructions 1-6 indicate that the head address of the line of the instruction dispatch table where the virtual machine instruction to be executed is located is loaded to the register t 3; the machine instruction 7 is used for calculating the column offset of the virtual machine instruction to be executed and storing the column offset in the register t2, and the machine instruction 8 is used for adding the head address of the row and the column offset to obtain the storage address Entry of the address of the instruction template corresponding to the virtual machine instruction to be executed in the instruction dispatch table; machine instruction 9 represents the access instruction to obtain the value stored in Entry in the instruction dispatch table, and stores the value, i.e. the address of the instruction template, into register t 3; machine instruction 10 indicates that the interpreter jumps to the address of the instruction template stored in register t3, completing the instruction dispatch.
The instruction dispatching process adopting the instruction dispatching method provided by the embodiment of the invention is as follows, and 4 strip machine instructions need to be executed:
The machine instruction 2 is a memory access instruction supporting a "base address + index + offset" addressing mode, gpr is a base address register storing a head address of an instruction dispatch table, the t2 register is a row index register storing a row offset, and col _ offset is a column offset. The access instruction gsldx may directly access Entry determined by "base address + row offset + column offset" encoded in the instruction and load the value stored in Entry, i.e., the address of the instruction template, into register t 3.
By way of the above exemplary comparison of specific machine instruction codes, it can be found that the instruction dispatching method provided by the embodiment of the present invention saves 6 machine instructions (machine instructions 1 to 6 in the prior art) by storing the first address of the instruction dispatching table in the high-speed access memory unit gpr; by extending the access instruction gsldx supporting the addressing mode of "base address + index + offset" in the existing MIPS instruction set, the load of Entry is reduced to 1 (machine instruction 2 in the present invention) by two machine (machine instructions 8 and 9 in the prior art) instructions. Because the number of instruction dispatches during the operation of the interpreter is usually as high as hundreds of billions, the execution of billions of magnitude machine instructions can be reduced by the embodiment of the invention, and the efficiency of the interpreter is greatly improved. The embodiment of the invention improves the instruction dispatching efficiency by reducing the machine instructions to be executed, thereby improving the execution efficiency of the interpreter and the virtual machine.
In another aspect, the present invention provides an interpreter for executing the instruction dispatching method described above. FIG. 4 is a schematic structural diagram of a first embodiment of an interpreter according to the present invention. As shown in fig. 4, includes:
a column offset obtaining module 401, configured to, after receiving a first virtual machine instruction, obtain a column offset of the first virtual machine instruction on an instruction dispatch table according to an output type of a second virtual machine instruction, where the second virtual machine instruction is a previous virtual machine instruction of the first virtual machine instruction;
A row offset obtaining module 402, configured to obtain a row offset of the first virtual machine instruction on the instruction dispatch table according to an opcode of the first virtual machine instruction, and store the row offset in the row index register;
an encoding module 403, configured to encode a base register storing a first address of the instruction dispatch table, a row index register, and a column offset into the access instruction;
And the execution module 404 is configured to, during execution of the memory access instruction, obtain an address of an instruction template required by execution of the first virtual machine instruction at an address determined by the first address, the row offset, and the column offset, and jump to the address of the instruction template to complete instruction dispatch.
Wherein, the column offset obtaining module 401 and the row offset obtaining module 402 have no strict execution order.
Furthermore, the instruction dispatch table stores addresses of all instruction templates corresponding to the virtual machine instructions, the addresses of the instruction templates are stored in different rows of the instruction dispatch table according to different operation codes of the corresponding virtual machine instructions, and the addresses of the instruction templates are stored in different columns of the instruction dispatch table according to different output types of the corresponding virtual machine instructions.
furthermore, at least one column of filling table entries are added in the instruction dispatch table, and the contents stored in the filling table entries are null; by increasing the number of columns of the fill table entries, the number of columns of the instruction dispatch table is raised to the power of 2.
further, the row offset obtaining module 402 is specifically configured to obtain the number of offset bits according to the number of columns of the instruction dispatch table and a preset value indicating the address length of the processor; and moving the operation code of the first virtual machine instruction to the left by the offset bit number to obtain the row offset of the first virtual machine instruction on the instruction dispatch table, and storing the row offset in the row index register.
further, the column offset obtaining module 401 is specifically configured to obtain a sequence number of a column occupied by the output type of the second virtual machine instruction in the instruction dispatch table; the column offset of the first virtual machine instruction on the instruction dispatch table is obtained according to the sequence number and a preset value representing the address length of the processor.
Further, addresses of instruction templates corresponding to virtual machine instructions of the no output type, the integer type, the reference type, and the single precision floating point type are stored in 4 consecutive columns of the instruction dispatch table.
further, the output type of the virtual machine instruction is one of the following: integer type, long integer type, single precision floating point type, double precision floating point type, reference type, and no output type.
The interpreter provided by the embodiment of the invention adopts the instruction dispatch table stored in the row according to the operation code of the virtual machine instruction and the output type of the virtual machine instruction in the column, stores the initial address of the instruction dispatch table in the high-speed access storage component, and simultaneously expands the access instruction supporting the 'base address + index + offset' addressing mode in the existing MIPS instruction set, and codes the base address register, the row index register and the column offset of the initial address of the storage instruction dispatch table corresponding to the virtual machine instruction to be interpreted and executed in the access instruction, so that the acquisition of the initial address of the row is avoided in the instruction dispatch process, the loading speed of the address of the instruction template is improved, the machine instruction to be executed is reduced, the instruction dispatch efficiency is improved, and the execution efficiency of the interpreter and the virtual machine is improved.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (13)
1. An instruction dispatching method, comprising:
After a first virtual machine instruction is received, acquiring column offset of the first virtual machine instruction on an instruction dispatch table according to the output type of a second virtual machine instruction, wherein the second virtual machine instruction is the last virtual machine instruction of the first virtual machine instruction; acquiring a row offset of the first virtual machine instruction on the instruction dispatch table according to an operation code of the first virtual machine instruction, and storing the row offset in a row index register;
Encoding a base register storing a first address of the instruction dispatch table, the row index register, and the column offset into a memory access instruction;
And when the memory access instruction is executed, acquiring the address of an instruction template required by the execution of the first virtual machine instruction at the address determined by the first address, the row offset and the column offset, and jumping to the address of the instruction template to finish instruction dispatching.
2. The method of claim 1, wherein the instruction dispatch table stores addresses of all instruction templates corresponding to the virtual machine instructions, the addresses of the instruction templates being stored in different rows of the instruction dispatch table according to different operation codes of the corresponding virtual machine instructions, and the addresses of the instruction templates being stored in different columns of the instruction dispatch table according to different output types of the corresponding virtual machine instructions.
3. the method of claim 2, wherein at least one column of padding entries is added to the instruction dispatch table, and the content stored in the padding entries is empty; by increasing the number of columns of the fill table entry, the number of columns of the instruction dispatch table is a power of 2.
4. The method of claim 3, wherein obtaining the row offset of the first virtual machine instruction on the instruction dispatch table according to the opcode of the first virtual machine instruction comprises:
acquiring the number of offset bits according to the column number of the instruction dispatch table and a preset numerical value representing the address length of the processor;
And moving the operation code of the first virtual machine instruction to the left by the offset bit number to obtain the row offset of the first virtual machine instruction on the instruction dispatch table.
5. The method of any of claims 2 to 4, wherein said obtaining a column offset of the first virtual machine instruction on the instruction dispatch table based on an output type of the second virtual machine instruction comprises:
acquiring the serial number of a column occupied by the output type of the second virtual machine instruction in the instruction dispatch table;
And obtaining the column offset of the first virtual machine instruction on the instruction dispatch table according to the sequence number and a preset numerical value representing the address length of the processor.
6. the method of any of claims 2 to 4, wherein addresses of instruction templates corresponding to virtual machine instructions of the no output type, the integer type, the reference type, and the single precision floating point type are stored in 4 consecutive columns of the instruction dispatch table.
7. The method of any of claims 2 to 4, wherein the output type of the virtual machine instruction is one of: integer type, long integer type, single precision floating point type, double precision floating point type, reference type, and no output type.
8. An interpreter, comprising:
The column offset acquisition module is used for acquiring column offset of a first virtual machine instruction on an instruction dispatch table according to the output type of a second virtual machine instruction after receiving the first virtual machine instruction, wherein the second virtual machine instruction is a virtual machine instruction which is the last virtual machine instruction of the first virtual machine instruction;
A row offset obtaining module, configured to obtain a row offset of the first virtual machine instruction on the instruction dispatch table according to an opcode of the first virtual machine instruction, and store the row offset in a row index register;
The encoding module is used for encoding a base address register for storing a first address of the instruction dispatch table, the row index register and the column offset into a memory access instruction;
And the execution module is used for acquiring the address of an instruction template required by the execution of the first virtual machine instruction at the address determined by the first address, the row offset and the column offset when the memory access instruction is executed, and jumping to the address of the instruction template to finish instruction allocation.
9. The interpreter of claim 8, wherein addresses of all instruction templates corresponding to virtual machine instructions are stored in the instruction dispatch table, wherein the addresses of the instruction templates are stored in different rows of the instruction dispatch table according to the operation codes of the corresponding virtual machine instructions, and wherein the addresses of the instruction templates are stored in different columns of the instruction dispatch table according to the output types of the corresponding virtual machine instructions.
10. the interpreter of claim 9, wherein at least one column of fill entries is added to the instruction dispatch table, and wherein the contents stored in the fill entries are empty; by increasing the number of columns of the fill table entry, the number of columns of the instruction dispatch table is a power of 2.
11. The interpreter of claim 10, wherein the row offset fetching module is specifically configured to fetch an offset bit number according to a column number of the instruction dispatch table and a preset value representing a processor address length; and moving the operation code of the first virtual machine instruction to the left by the offset bit number to obtain the row offset of the first virtual machine instruction on the instruction dispatch table, and storing the row offset in a row index register.
12. the interpreter of any one of claims 9 to 11, wherein the column offset fetching module is specifically configured to fetch a sequence number of a column occupied by an output type of the second virtual machine instruction in the instruction dispatch table; and obtaining the column offset of the first virtual machine instruction on the instruction dispatch table according to the sequence number and a preset numerical value representing the address length of the processor.
13. The interpreter of any one of claims 9 to 11, wherein addresses of instruction templates corresponding to virtual machine instructions of a no-output type, an integer type, a reference type, and a single-precision floating-point type are stored in 4 consecutive columns of the instruction dispatch table;
the output type of the virtual machine instruction is one of the following types: integer type, long integer type, single precision floating point type, double precision floating point type, reference type, and no output type.
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| US20060288338A1 (en) * | 2005-06-15 | 2006-12-21 | Jinzhan Peng | Offset threaded code |
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