CN107132554A - A kind of parallel code phase search device and the method for realizing parallel code phase search - Google Patents
A kind of parallel code phase search device and the method for realizing parallel code phase search Download PDFInfo
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- CN107132554A CN107132554A CN201610109528.1A CN201610109528A CN107132554A CN 107132554 A CN107132554 A CN 107132554A CN 201610109528 A CN201610109528 A CN 201610109528A CN 107132554 A CN107132554 A CN 107132554A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
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- G01S19/24—Acquisition or tracking or demodulation of signals transmitted by the system
- G01S19/30—Acquisition or tracking or demodulation of signals transmitted by the system code related
Abstract
The invention discloses a kind of parallel code phase search device and the method for realizing parallel code phase search, including：Saltus step processing is carried out respectively to the product obtained that is multiplied by parallel code phase search circuit multiplier by the hopping sequences of predetermined number, corresponding saltus step product is obtained；Each saltus step product to acquisition carries out coherent accumulation processing respectively, obtains corresponding coherent accumulation results；Real part to each coherent accumulation results carries out accumulation process respectively, the maximum hopping sequences of numerical value after accumulation process are determined, and the corresponding coherent accumulation results of the hopping sequences are carried out to be used as to export after Fourier inversion processing and modulus processing to carry out phase search；In technical solution of the present invention, after parallel code phase search circuit multiplier, random jump unit and coherent accumulation processing are eliminated by increasing, the complexity of parallel code phase search is reduced, avoid because saltus step occurs in related accumulation process, realize the phase search in the case of weak signal.
Description
Technical field
The present invention relates to signal processing technology, espespecially a kind of parallel code phase search device and the method for realizing parallel code phase search.
Background technology
GPS (GNSS) plays more and more irreplaceable important function in daily life, is especially more and more applied in fields such as navigation, timing, mappings.At present, the GPS mainly global positioning system (GPS) including the U.S., the Big Dipper (BD) system of China, the global navigational satellite alignment system (GLONASS) of Russia, and European Galileo (Galileo) system.In China and the Asian-Pacific area, GPS and dipper system are using relatively broad；And in Russia, with GPS and GLONASS using more.Because Galileo system is ripe far away, formal service can not be still provided.Positioned using GPS, timing etc. business when, it is necessary first to capture the wireless signal of at least four visible satellites, three-dimensional search algorithm realized by the wireless signal of capture, three-dimensional search algorithm includes：Satellite pseudo-code, code phase and Doppler frequency shift.
Common linear search method takes oversize according to one-dimensional, two-dimentional, three-dimensional order search one by one.In order to less time-consuming, parallel search method is developed, for example, parallel code phase search algorithm, and the used time can be obviously reduced.Fig. 1 is existing parallel code phase search circuit theory diagrams, as shown in Figure 1, after digital intermediate frequency input signal is mixed with the duplication sine and duplication cosine carrier signal of first band on same phase (I) branch road and orthogonal (Q) branch road respectively, the first Fourier transform unit progress Fourier transformation is passed through with the plural form with phase with orthogonal mixing results and obtains Fourier transformation result；Fourier transformation result and local code are conjugated result and (replicate the local code that thick capture (C/A) code generator is produced, the local code of duplication is obtained into local code conjugation result through the second Fourier transform unit and complex conjugate units processing) it is multiplied by multiplier, the product obtained will be multiplied by multiplier and carries out correlated results of the processing acquisition in time domain through Fourier inversion unit, the correlated results in the time domain of acquisition is carried out into detection after modulus by modulus unit judges that parallel code phase signal whether there is.After the search and detection to present band is completed, receiver then allows carrier wave digital controlled oscillator (NCO) to carry out second band sinusoidal carrier and cosine carrier is replicated, then the search and detection to other frequency bands is accomplished analogously, here, the numerical value of first band, second band and other frequency bands is the traversal frequency band used during parallel code phase search, is the common knowledge of those skilled in the art.In search procedure in same satellite-signal different frequency bands, replicating the phase of C/A codes can keep constant, and correspondingly its Fourier transformation and its conjugate also keep constant.When searching for another satellite-signal, receiver can allow C/A code generators to replicate another corresponding C/A code, then repeat the above-mentioned signal search process in each frequency band.
Above-mentioned parallel code phase search algorithm is only applicable to stronger navigation signal (digital intermediate frequency input signal), to the weaker above-mentioned parallel code phase search algorithm of navigation signal and does not apply to；Because, signal to noise ratio is higher (noise is weaker) when navigation signal is stronger；Noise is very strong when navigation signal is weaker, i.e., signal to noise ratio is relatively low, and very noisy greatly interferes with the search and capture of navigation signal, causes that correct navigation signal can not be searched out.For weak navigation signal (being referred to as weak signal herein), increase coherent integration length is usually taken to improve the signal to noise ratio of code acquisition scheme, and then improve the success rate of search and Acquisition Scheme, that is, increase the computing length N of the correlator in such scheme；But because above-mentioned traditional scheme employs the Digital Signal Processing of discrete Fourier transform, and discrete Fourier transform operation possesses larger complexity, for the larger transform sequence of length.For example, for stronger signal, correlator length is 1 millisecond (ms), and for weak signal, length is even up to the several seconds, at least also needs to reach several ms, such as 40ms.In summary, complexity is too high when above-mentioned parallel code phase search algorithm has progress weak signal search, i.e., above-mentioned parallel code phase search algorithm can not be applied to weak signal scene.
The content of the invention
In order to solve the above-mentioned technical problem, the method that the present invention provides a kind of device of frequency search and realizes frequency search, can reduce the complexity of Fourier transformation.
The embodiments of the invention provide a kind of parallel code phase search device, including：Eliminate random jump unit, coherent accumulator, compare selecting unit, Fourier inversion unit and modulus unit；Wherein,
Eliminate random jump unit to be connected with the multiplier of parallel code phase search circuit, corresponding saltus step processing is carried out respectively to the product obtained by multiplier multiplication received by the hopping sequences of predetermined number, the corresponding saltus step product of each hopping sequences is obtained；
Coherent accumulator is connected with eliminating random jump unit, and the corresponding saltus step product of each hopping sequences to acquisition carries out coherent accumulation processing respectively, obtains the corresponding coherent accumulation results of each hopping sequences；
Compare selecting unit to be connected with coherent accumulator, the accumulation process of real part is carried out respectively to the corresponding coherent accumulation results of each hopping sequences of reception, the coherent accumulation results of the maximum corresponding hopping sequences of real part accumulating values are selected, Fourier inversion unit is sent to；
The coherent accumulation results that Fourier inversion unit receives the maximum corresponding hopping sequences of real part accumulating values for comparing selecting unit transmission carry out Fourier inversion processing；
Modulus unit is connected with Fourier inversion unit, to carrying out phase search as output after the data that Fourier inversion unit Fourier inversion is handled carry out modulus processing；
It is described by multiplier be multiplied obtain product be：The local code of the Fourier transformation result of the parallel code phase search circuit and the parallel code phase search circuit is conjugated the product of result.
Optionally, the hopping sequences of the predetermined number are：
The predetermined number is used as using the sequence length M of digital intermediate frequency input signal and local code length N business；
It is the sequence that transition times are 0 to determine the first hopping sequences；
It is determined that other hopping sequences in addition to the first hopping sequences have and only occurred a saltus step.
Optionally, it is described elimination random jump unit specifically for,
The hopping sequences saltus step processing corresponding with the product progress by multiplier multiplication acquisition for carrying out predetermined number by the first default matrix unit, obtains the corresponding saltus step product of each hopping sequences；
The line number of the default matrix unit is local code length N, columns is equal with the predetermined number numerical value.
Optionally, the elimination random jump unit is additionally operable to,
The product for being multiplied and obtaining by multiplier described in receiving is cached by the second default matrix unit；
The line number of described second default matrix unit is local code length N, columns is equal with the predetermined number numerical value.
Optionally, coherent accumulation unit specifically for,
It is connected with eliminating random jump unit, default value sequence progress coherent accumulation processing is respectively adopted in the corresponding saltus step product of each hopping sequences to acquisition, obtains the corresponding coherent accumulation results of each hopping sequences.
Optionally, default value sequence be 0, M/N, 2M/N ..., (N-1) M/N.
On the other hand, the embodiment of the present invention additionally provides a kind of method for realizing parallel code phase search, including：
Corresponding saltus step processing is carried out respectively to the product obtained that is multiplied by parallel code phase search circuit multiplier by the hopping sequences of predetermined number, the corresponding saltus step product of each hopping sequences is obtained；
The corresponding saltus step product of each hopping sequences to acquisition carries out coherent accumulation processing respectively, obtains the corresponding coherent accumulation results of each hopping sequences；
Respectively to the carry out accumulation process of the real parts of the corresponding coherent accumulation results of each hopping sequences, the maximum corresponding coherent accumulation results of hopping sequences of real part accumulating values are determined；
The corresponding coherent accumulation results of the maximum hopping sequences of the real part accumulating values of determination are subjected to Fourier inversion processing, Fourier inversion processing data is obtained；
Fourier inversion processing data to acquisition is carried out after modulus processing as output progress phase search；
It is described by multiplier be multiplied obtain product be：The local code of the Fourier transformation result of the parallel code phase search circuit and the parallel code phase search circuit is conjugated the product of result.
Optionally, the hopping sequences of predetermined number are：
The predetermined number is used as using the sequence length M of digital intermediate frequency input signal and local code length N business；
It is the sequence that transition times are 0 to determine the first hopping sequences；
It is determined that other hopping sequences in addition to the first hopping sequences have and only occurred a saltus step.
Optionally, corresponding saltus step processing is carried out respectively to specifically include：
The hopping sequences saltus step processing corresponding with the product progress by multiplier multiplication acquisition for carrying out predetermined number by the first default matrix unit, obtains the corresponding saltus step product of each hopping sequences；
The line number of the default matrix unit is local code length N, columns is equal with the predetermined number numerical value.
Optionally, this method also includes：
The product for being multiplied and obtaining by multiplier described in receiving is cached by the second default matrix unit；
The line number of described second default matrix unit is local code length N, columns is equal with the predetermined number numerical value.
Optionally, carrying out coherent accumulation processing includes：
Default value sequence progress coherent accumulation processing is respectively adopted in the corresponding saltus step product of each hopping sequences to acquisition.
Optionally, default value sequence be 0, M/N, 2M/N ..., (N-1) M/N.
Compared with prior art, technical scheme includes：Corresponding saltus step processing is carried out respectively to the product obtained that is multiplied by parallel code phase search circuit multiplier by the hopping sequences of predetermined number, the corresponding saltus step product of each hopping sequences is obtained；The corresponding saltus step product of each hopping sequences to acquisition carries out coherent accumulation processing respectively, obtains the corresponding coherent accumulation results of each hopping sequences；Respectively to the carry out accumulation process of the real parts of the corresponding coherent accumulation results of each hopping sequences, the maximum corresponding coherent accumulation results of hopping sequences of real part accumulating values are determined；The corresponding coherent accumulation results of the maximum hopping sequences of the real part accumulating values of determination are subjected to Fourier inversion processing, Fourier inversion processing data is obtained；Fourier inversion processing data to acquisition is carried out after modulus processing as output progress phase search；In technical solution of the present invention, after parallel code phase search circuit multiplier, random jump unit and coherent accumulation processing are eliminated by increasing, the complexity of parallel code phase search is reduced, avoid because saltus step occurs in related accumulation process, realize the phase search in the case of weak signal.
Brief description of the drawings
Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the application, and schematic description and description of the invention is used to explain the present invention, does not constitute inappropriate limitation of the present invention.In the accompanying drawings：
Fig. 1 is existing parallel code phase search circuit theory diagrams；
Fig. 2 is the structured flowchart of parallel code phase search device of the embodiment of the present invention；
Fig. 3 is the flow chart for the method that the embodiment of the present invention realizes parallel code phase search.
Embodiment
For the object, technical solutions and advantages of the present invention are more clearly understood, embodiments of the invention are described in detail below in conjunction with accompanying drawing.It should be noted that in the case where not conflicting, the feature in embodiment and embodiment in the application can be mutually combined.
In order that present invention is readily appreciated, before statement scheme of the embodiment of the present invention, Theoretical Proof is carried out to parallel code phase search partial content；Parallel code phase search algorithm, come the related operation of Alternative digital correlator, will be proven below both equivalences actually using this Digital Signal Processing of Fourier transformation.Two length of note are that the periodic sequence of N points is l (n) and j (n), and its sequence of correlation values is d (n), wherein, n=0,1 ..., N-1 are represented by formula (1)：
Formula (1)
Discrete Fourier transform is carried out to above-mentioned sequence of correlation values d (n), d (n) discrete Fourier transform D (k) is obtained such as shown in formula (2)：
Formula (2)
Formula (3) is obtained in the discrete Fourier transform D (k) for the d (n) that the sequence of correlation values d (n) of formula (1) is substituted into formula (2)：
Formula (3)
Formula (3) can transform to formula (4)：
Formula (4)
Formula (4), which can simplify, is expressed as formula (5)：
Formula (5)
Wherein, L (k) and J (k) is respectively l (n) and j (n) discrete Fourier transform,Represent plural number J (k) conjugation.Above formula shows：Two sequence l (n) and j (n) carry out related calculation in time domain, and the discrete Fourier transform L (k) and J (k) equivalent to them (are Specifically J (k) conjugation) product calculation is done in frequency domain.Then turn around, productInverse discrete fourier transform be exactly that receiver needs the correlation d (n) at each code phase that is detected.Once receiver is calculated by Fourier inversion and obtains correlation d (n), so ensuing signal detection is the same with regard to collinearity code acquisition method, find out the auto-correlation amplitude in all search units | d (n) | peak value, and the peak value is compared with detection threshold value.If peak value exceedes detection threshold value, receiver acquisition has arrived signal, and also therefrom obtains two parameter values of frequency and code phase of the signal.It is pointed out that for GPS navigation system, j (n) sequences in the above-mentioned process of argumentation can be the local code sequence that C/A code generators are produced, and the sequence length of local code sequence is N=1023 chip, and time span is 1ms.
Fig. 2 is the structured flowchart of parallel code phase search device of the embodiment of the present invention, as shown in Fig. 2 including：
Eliminate random jump unit, coherent accumulator, compare selecting unit, Fourier inversion unit and modulus unit；Wherein,
Eliminate random jump unit to be connected with the multiplier of parallel code phase search circuit, corresponding saltus step processing is carried out respectively to the product obtained by multiplier multiplication received by the hopping sequences of predetermined number, the corresponding saltus step product of each hopping sequences is obtained；
Optionally, the hopping sequences of predetermined number are：
Predetermined number is used as using the sequence length M of digital intermediate frequency input signal and local code length N business；
It is the sequence that transition times are 0 to determine the first hopping sequences；
It is determined that other hopping sequences in addition to the first hopping sequences have and only occurred a saltus step.
It should be noted that transition times refer to the situation that saltus step does not occur for 0 sequence, so that length is 4 sequence as an example, sequence {+1 ,+1 ,+1 ,+1 } is the sequence that transition times are 0；Similarly, sequence { -1, -1, -1, -1 } is also the sequence that transition times are 0；If the first hopping sequences are sequence {+1 ,+1 ,+1 ,+1 }, then other hopping sequences in addition to the first hopping sequences can be expressed as：Occur the sequence {+1, -1, -1, -1 } of saltus step in second element of sequence, occur the sequence {+1 ,+1, -1, -1 } of saltus step in the 3rd element of sequence, occur the sequence {+1 ,+1 ,+1, -1 } of saltus step in the 4th element of sequence.Other hopping sequences i.e. in addition to the first hopping sequences have and only occurred a saltus step.The numerical value of sequence keeps constant after saltus step.The hopping sequences of above-mentioned predetermined number are the optimal hopping sequences of application effect, the number and transition times of increase hopping sequences do not influence the implementation of the embodiment of the present invention on this basis, and increase hopping sequences number and transition times can increase the work of parallel code phase search device.
Coherent accumulator is connected with eliminating random jump unit, and the corresponding saltus step product of each hopping sequences to acquisition carries out coherent accumulation processing respectively, obtains the corresponding coherent accumulation results of each hopping sequences；
Compare selecting unit to be connected with coherent accumulator, the accumulation process of real part is carried out respectively to the corresponding coherent accumulation results of each hopping sequences of reception, the coherent accumulation results of the maximum corresponding hopping sequences of real part accumulating values are selected, Fourier inversion unit is sent to；
The coherent accumulation results that Fourier inversion unit receives the maximum corresponding hopping sequences of real part accumulating values for comparing selecting unit transmission carry out Fourier inversion processing；
Modulus unit is connected with Fourier inversion unit, to carrying out phase search as output after the data that Fourier inversion unit Fourier inversion is handled carry out modulus processing；
By multiplier be multiplied obtain product be：The Fourier transformation result of parallel code phase search circuit is conjugated the product of result with the local code of parallel code phase search circuit.
Optionally, eliminate random jump unit specifically for,
The hopping sequences saltus step processing corresponding with the product progress by multiplier multiplication acquisition for carrying out predetermined number by the first default matrix unit, obtains the corresponding saltus step product of each hopping sequences；
The line number of default matrix unit is local code length N, columns is equal with predetermined number numerical value.
Optionally, random jump unit is eliminated to be additionally operable to,
The product of the acquisition that is multiplied by multiplier received by the second default matrix unit caching；
The line number of second default matrix unit is local code length N, columns is equal with predetermined number numerical value.
Optionally, coherent accumulation unit specifically for,
It is connected with eliminating random jump unit, default value sequence progress coherent accumulation processing is respectively adopted in the corresponding saltus step product of each hopping sequences to acquisition, obtains the corresponding coherent accumulation results of each hopping sequences.
Optionally, default value sequence be 0, M/N, 2M/N ..., (N-1) M/N.
Technical solution of the present invention is after parallel code phase search circuit multiplier, random jump unit and coherent accumulation processing are eliminated by increasing, reduce the complexity of parallel code phase search, it is to avoid because saltus step occurs in related accumulation process, realize the phase search in the case of weak signal.
Fig. 3 is the flow chart of the method for parallel code phase search of the embodiment of the present invention, as shown in figure 3, including：
Step 300, by the hopping sequences of predetermined number corresponding saltus step processing is carried out respectively to the product obtained that is multiplied by parallel code phase search circuit multiplier, obtain the corresponding saltus step product of each hopping sequences；Here, it is by the product of multiplier multiplication acquisition：The Fourier transformation result of parallel code phase search circuit is conjugated the product of result with the local code of parallel code phase search circuit.
Optionally, the hopping sequences of predetermined number are：
Predetermined number is used as using the sequence length M of digital intermediate frequency input signal and local code length N business；
It is the sequence that transition times are 0 to determine the first hopping sequences；
It is determined that other hopping sequences in addition to the first hopping sequences have and only occurred a saltus step.
In this step, corresponding saltus step processing is carried out respectively and is specifically included：
The hopping sequences saltus step processing corresponding with the product progress by multiplier multiplication acquisition for carrying out predetermined number by the first default matrix unit, obtains the corresponding saltus step product of each hopping sequences；
The line number of default matrix unit is local code length N, columns is equal with predetermined number numerical value.
Optionally, present invention method also includes：
The product of the acquisition that is multiplied by multiplier received by the second default matrix unit caching；
The line number of second default matrix unit is local code length N, columns is equal with predetermined number numerical value.
Step 301, the corresponding saltus step product of each hopping sequences respectively to acquisition carry out coherent accumulation processing, obtain the corresponding coherent accumulation results of each hopping sequences；
In this step, carrying out coherent accumulation processing respectively to the corresponding saltus step correlated results of each hopping sequences of acquisition includes：
Default value sequence progress coherent accumulation processing is respectively adopted in the corresponding saltus step product of each hopping sequences to acquisition.
Optionally, default value sequence be 0, M/N, 2M/N ..., (N-1) M/N.
Step 302, carry out accumulation process respectively to the real parts of the corresponding coherent accumulation results of each hopping sequences, determine the maximum corresponding coherent accumulation results of hopping sequences of real part accumulating values；
Step 303, the corresponding coherent accumulation results of the maximum hopping sequences of the real part accumulating values of determination are subjected to Fourier inversion processing, obtain Fourier inversion processing data.
Step 304, the Fourier inversion processing data to acquisition are carried out after modulus processing as output progress phase search.
In technical solution of the present invention, saltus step processing is first carried out, then carries out coherent accumulation processing, the complexity of parallel code phase search is reduced, have modified the saltus step being likely to occur in coherent accumulation processing procedure, realize the phase search of weak signal.
The inventive method is clearly described in detail below by way of using example, the statement present invention is only used for using example, is not intended to limit the present invention the protection domain of method.
Using example
Weak signal parallel code phase search scheme proposed by the present invention is described below in detail.
First, formula below derivation is carried out.
It is local code sequence to remember x (n), and x (n) is periodic sequence, and Cycle Length is N, n=0,1 ..., N-1.The navigation signal (digital intermediate frequency input signal) for remembering y (n) to receive, is the navigation signal mixed that multi-satellite is sent, and sequence length is infinitely great, i.e. n=0,1 ....Then the sequence of correlation values of the two can be expressed as formula (6)：
Formula (6)
Wherein, M=cN, c are positive integer, i.e. M is the numerical value for the integral multiple that one is N., can be by taking following value as an example, if N=1ms, M can be determined according to c values for gps system, such as c=40, then M=40ms.
Discrete Fourier transform is done to z (n) can obtain formula (7)
Formula (7)
Z (n) is substituted into formula (7) to obtain
Formula (8)
Progressively carry out variable replacement according to the following equation to formula (8) and obtain formula (12)：
Formula (9)
Formula (10)
Formula (11)
Formula (12)
Have periodically in view of x (n), and y (n) have it is approximately periodic (sequences y (n) include sequence x (n), gained is changed by x (n)), formula (12) is deformed and obtained：
Formula (13)
After form simplification is handled：Formula (14)
Wherein, X (k) is x (n) sequences that length is N through obtained by discrete Fourier transform, and Y (k) is y (n) sequences that length is M through obtained by discrete Fourier transform, i.e., discrete Fourier transform length is respectively N and M.
For weak signal, M can correspond to very long coherent integration length, such as 100ms, or even longer, and N only corresponds to 1ms.As a specific example, N can value 1023, M can value 1023 integral multiple, such as M=1023*100；Due to complexity issue, the length of discrete Fourier transform can not arbitrarily increase；Although i.e. above-mentioned formula derives and can search for capturing weak navigation signal, because the discrete Fourier transform complexity of M points is too high, such scheme in actual applications and can not be realized.
Found by inventor's analysis, for M points discrete Fourier transform sequence Y (k) actually only with part sample point result, i.e. sample point 0, M/N, 2M/N ..., (N-1) M/N, i.e. the discrete Fourier transform sequence Y (k) of M points only used value sequence；
Approximate formula (15) can be obtained by arranging：
Formula (15)
Pairing approximation formula (15) is explained as follows：
In formula (1), M/N=c, c is positive integer；The word IF input signals that count are y (n), take continuous y (n) sequence of M points, i.e. n=0,1 ..., M-1；The y that length is N points is remembered simultaneously1(n) (n=0,1 ..., N-1) sequence is y (m), m=0,1 ..., N-1；Remember the y that length is N points2(n) (n=0,1 ..., N-1) sequence is y (m), m=N, N+1 ..., 2N-1；By that analogy, note length is the y of N pointsc(n) (n=0,1 ..., N-1) sequence is y (m), m=(c-1) N, (c-1) N+1 ..., cN-1.
Meanwhile, Y (k) be y (n) M point discrete Fouriers in leaf transformation sequence, Yp(k) it is yp(n) leaf transformation sequence in N point discrete Fouriers, p=1,2 ..., c.
Formula (16) can be obtained based on described above and approximate formula (15) content,
Formula (16)
Formula (16) carries out corresponding saltus step processing respectively by the hopping sequences of predetermined number to the product obtained by multiplier multiplication received, obtains the corresponding saltus step product of each hopping sequences；
This application example, the product obtained that is multiplied by multiplier that can be received by the second default matrix unit caching；
The hopping sequences saltus step processing corresponding with the product progress by multiplier multiplication acquisition for carrying out predetermined number by the first default matrix unit, obtains the corresponding saltus step product of each hopping sequences；
The line number of first default matrix unit and the second default matrix unit is local code length N, columns is equal with predetermined number numerical value.Matrix unit carries out the ranks sequence of product can be adjusted according to be multiplied with the multiplier length of product of hopping sequences with procession.
The accumulation process of real part, the coherent accumulation results of the maximum corresponding hopping sequences of selection real part accumulating values are carried out respectively to the corresponding coherent accumulation results of each hopping sequences of reception；
The corresponding coherent accumulation results of the maximum hopping sequences of the real part accumulating values of determination are subjected to Fourier inversion processing, Fourier inversion processing data is obtained；
Fourier inversion processing data to acquisition is carried out after modulus processing as output progress phase search；
This application example is still so that the length of hopping sequences is 4 as an example, using in example, if saltus step does not occur, then hopping sequences are sequence {+1, when+1 ,+1 ,+1 }, the corresponding coherent accumulation results of each hopping sequences are carried out after the accumulation process of real part respectively, the coherent accumulation results of the maximum corresponding hopping sequences of real part accumulating values must be sequence {+1 ,+1 ,+1, + 1 } corresponding coherent accumulation results, that is sequence {+1 ,+1 ,+1, + 1 } corresponding coherent accumulation results will carry out Fourier inversion processing and modulus processing, with user's phase search.
This application example, second default matrix unit can be removed, directly carry out jumping product processing in the first matrix unit, follow-up coherent accumulation can continue to be calculated in the first default matrix unit, and the removal of the second default matrix unit can save memory space.
If can be modified it should be noted that existing in present invention application example coherent accumulation results and certainly existing a hopping sequences in the hopping sequences in saltus step, predetermined number to saltus step.By simulation analysis, this application example have modified the saltus step occurred in coherent accumulation processing procedure, realize the phase search in the case of weak signal while parallel code phase search is simplified.
Although disclosed herein embodiment as above, described content be only readily appreciate the present invention and use embodiment, be not limited to the present invention.Technical staff in any art of the present invention; do not depart from disclosed herein spirit and scope on the premise of; any modification and change, but the scope of patent protection of the present invention can be carried out in the form and details of implementation, still be should be subject to the scope of the claims as defined in the appended claims.
Claims (12)
1. a kind of parallel code phase search device, it is characterised in that including：Elimination random jump unit,
Coherent accumulator, compare selecting unit, Fourier inversion unit and modulus unit；Wherein,
Eliminate random jump unit to be connected with the multiplier of parallel code phase search circuit, pass through predetermined number
Hopping sequences respectively carried out to receiving the product that obtains of being multiplied by multiplier at corresponding saltus step
Reason, obtains the corresponding saltus step product of each hopping sequences；
Coherent accumulator is connected with eliminating random jump unit, the corresponding saltus step of each hopping sequences to acquisition
Product carries out coherent accumulation processing respectively, obtains the corresponding coherent accumulation results of each hopping sequences；
Compare selecting unit to be connected with coherent accumulator, to the corresponding coherent accumulation of each hopping sequences of reception
As a result the accumulation process of real part, the maximum corresponding saltus step of selection real part accumulating values are carried out respectively
The coherent accumulation results of sequence, are sent to Fourier inversion unit；
Fourier inversion unit receives the real part accumulating values maximum correspondence for comparing selecting unit transmission
Hopping sequences coherent accumulation results carry out Fourier inversion processing；
Modulus unit is connected with Fourier inversion unit, to anti-by Fourier inversion unit Fourier
The data of conversion process are carried out after modulus processing as output progress phase search；
It is described by multiplier be multiplied obtain product be：The Fourier of the parallel code phase search circuit
The local code of transformation results and the parallel code phase search circuit is conjugated the product of result.
2. parallel code phase search device according to claim 1, it is characterised in that described default
The hopping sequences of number are：
Preset using the sequence length M of digital intermediate frequency input signal and local code length N business as described
Number；
It is the sequence that transition times are 0 to determine the first hopping sequences；
It is determined that other hopping sequences in addition to the first hopping sequences have and only occurred a saltus step.
3. parallel code phase search device according to claim 2, it is characterised in that the elimination
Random jump unit specifically for,
The hopping sequences for carrying out predetermined number by the first default matrix unit are multiplied with described by multiplier
The product of acquisition carries out corresponding saltus step processing, obtains the corresponding saltus step product of each hopping sequences；
The line number of the default matrix unit is local code length N, columns and the predetermined number numerical value
It is equal.
4. the parallel code phase search device according to Claims 2 or 3, it is characterised in that described
Random jump unit is eliminated to be additionally operable to,
The product for being multiplied and obtaining by multiplier described in receiving is cached by the second default matrix unit；
The line number of described second default matrix unit is local code length N, columns and the predetermined number number
Value is equal.
5. the parallel code phase search device according to any one of claims 1 to 3, described relevant tired
Plus unit specifically for,
It is connected with eliminating random jump unit, the corresponding saltus step product of each hopping sequences to acquisition is adopted respectively
Coherent accumulation processing is carried out with default value sequence, the corresponding coherent accumulation results of each hopping sequences are obtained.
6. parallel code phase search device according to claim 5, the default value sequence is 0,
M/N、2M/N、…、(N-1)M/N。
7. a kind of method for realizing parallel code phase search, it is characterised in that including：
By the hopping sequences of predetermined number to being multiplied what is obtained by parallel code phase search circuit multiplier
Product carries out corresponding saltus step processing respectively, obtains the corresponding saltus step product of each hopping sequences；
The corresponding saltus step product of each hopping sequences to acquisition carries out coherent accumulation processing respectively, obtains each jump
Become the corresponding coherent accumulation results of sequence；
Respectively to the carry out accumulation process of the real parts of the corresponding coherent accumulation results of each hopping sequences, really
Determine the maximum corresponding coherent accumulation results of hopping sequences of real part accumulating values；
The corresponding coherent accumulation results of the maximum hopping sequences of the real part accumulating values of determination are subjected to Fu
In leaf inverse transformation handle, obtain Fourier inversion processing data；
The Fourier inversion processing data of acquisition is carried out after modulus processing searching into line phase as exporting
Rope；
It is described by multiplier be multiplied obtain product be：The Fourier of the parallel code phase search circuit
The local code of transformation results and the parallel code phase search circuit is conjugated the product of result.
8. method according to claim 7, it is characterised in that the hopping sequences of the predetermined number
For：
Preset using the sequence length M of digital intermediate frequency input signal and local code length N business as described
Number；
It is the sequence that transition times are 0 to determine the first hopping sequences；
It is determined that other hopping sequences in addition to the first hopping sequences have and only occurred a saltus step.
9. method according to claim 8, it is characterised in that described to carry out corresponding saltus step respectively
Processing is specifically included：
The hopping sequences for carrying out predetermined number by the first default matrix unit are multiplied with described by multiplier
The product of acquisition carries out corresponding saltus step processing, obtains the corresponding saltus step product of each hopping sequences；
The line number of the default matrix unit is local code length N, columns and the predetermined number numerical value
It is equal.
10. method according to claim 8 or claim 9, it is characterised in that this method also includes：
The product for being multiplied and obtaining by multiplier described in receiving is cached by the second default matrix unit；
The line number of described second default matrix unit is local code length N, columns and the predetermined number number
Value is equal.
11. the method according to any one of claim 7~9, the carry out coherent accumulation processing includes：
The corresponding saltus step product of each hopping sequences of acquisition is respectively adopted default value sequence carry out it is relevant tired
Plus processing.
12. method according to claim 11, the default value sequence be 0, M/N,
2M/N、…、(N-1)M/N。
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