CN107123673A - A kind of multi-Vt regulation and control method of the gate FinFET device of independence three - Google Patents
A kind of multi-Vt regulation and control method of the gate FinFET device of independence three Download PDFInfo
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- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
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Abstract
Regulate and control method the invention discloses a kind of multi-Vt of new FinFET that can be realized multiple threshold voltage control models and possess three independant gate structures, in the case of without additional electric potential source, supply voltage or ground connection are applied respectively to left side gate metal layer, right side gate metal layer, top grid metal level, five kinds of different threshold voltage control models are realized.The present invention is separately deposited to top grid dielectric layer with bottom grid dielectric layer, can realize the independent selection of top grid dielectric layer and bottom grid dielectric layer material and thickness；The present invention is separately deposited to top grid metal level with bottom grid metal level, can realize top grid metal level and the independent selection of bottom grid metal layer material, and the regulation and control to threshold voltage can be achieved in aforesaid way.
Description
Technical field
Adjusted the present invention relates to the multi-Vt of technical field of semiconductors, more particularly to a kind of gate FinFET device of independence three
Prosecutor method.
Background technology
As the characteristic size of semiconductor integrated circuit technique is constantly contracted to nanometer scale, conventional planar MOS device
Short-channel effect is more obvious, brings the problems such as decline, the degradation of subthreshold swing of threshold voltage, it is no longer expired
The requirement of sufficient industry.FinFET relies on its outstanding grid-control ability, and substitution conventional planar MOS device progressively becomes present
Main flow device.However, FinFET three-dimensional structure make device width and Fin height it is interrelated, cause be based on FinFET
Circuit design flexibility reduction.
In the case where FinFET breadth length ratio is relatively fixed, by changing the work function of gate metal come adjusting means
Threshold voltage realizes that circuit design requirements are the usual ways of industry with this.In addition, FinFET structure is changed
The flexibility for coming in increase circuit design always also is the focus of research, thus just occurs in that independent double grid FinFET device
Structure.The structure by chemically-mechanicapolish polishing the technique of (CMP) such that continuous grid (tied-gate) is changed into two phases originally
Mutual independent grid：Normal-gate (front gate), post tensioned unbonded prestressed concrete (back gate).Normal-gate is used as driving grid (drive
Gate), post tensioned unbonded prestressed concrete applies different size of voltage to post tensioned unbonded prestressed concrete, can arbitrarily changed as control gate (control gate)
Become the threshold voltage of device.However, because the addition of extra voltage source is unfavorable for the lifting of circuit level, independent double grid
FinFET is generally only with two kinds of pattern of threshold voltages：Single grid pattern (post tensioned unbonded prestressed concrete ground connection), double grid pattern (post tensioned unbonded prestressed concrete and front gate
Extremely it is connected), therefore the circuit design flexibility based on independent double grid FinFET still has much room for improvement.
The present invention proposes a kind of multi-Vt regulation and control of new FinFET for possessing three independant gate structures
Method, the device includes three independent gates, is different from the single continuous grid in existing finfet technology, the grid-control shown
Characteristic, can realize 5 kinds of different threshold voltage control models in the case of without additional electric potential source.In addition, by different-thickness,
Selection, the difference of different types of top and bottom gate metal layer respectively of different types of top and bottom gate dielectric layer
Choose, it is possible to achieve device threshold voltage is freely adjusted, the significant increase flexibility of circuit design.
The content of the invention
The present invention proposes a kind of multi-Vt regulation and control of new FinFET for possessing three independant gate structures
Method, the new FinFET includes：Substrate；Oxide skin(coating), it is located at the surface of the substrate；Fin structure, its position
In the surface of the oxide skin(coating), the channel region in center and source region and the drain region at two ends are formed；Gate dielectric layer, it is vertically arranged
On the channel region of the fin structure and surround the channel region；The gate dielectric layer includes：It is arranged on the fin-shaped knot
Left side gate dielectric layer on the left of structure, the right side gate dielectric layer being arranged on the right side of the fin structure and it is arranged on described
Top grid dielectric layer at the top of fin structure；Gate metal layer, it includes：Left side gate metal layer, it is located at the top
Between gate dielectric layer, the left side gate dielectric layer and the oxide skin(coating)；Right side gate metal layer, it is located at the top
Between gate dielectric layer, the right side gate dielectric layer and the oxide skin(coating)；Top grid metal level, it is located at the top
The top of gate dielectric layer；And side wall, it is arranged on the both sides of the gate dielectric layer and the gate metal layer；Without extra
In the case of voltage source, the left side gate metal layer, the right side gate metal layer, the top grid metal level are distinguished
Apply supply voltage or ground connection, realize five kinds of different threshold voltage control models.
In the multi-Vt regulation and control method proposed by the present invention, the left side gate dielectric layer and the right side grid
The dielectric layer material of dielectric layer is identical, and the top grid dielectric layer is situated between with the left side gate dielectric layer, the right side grid
The dielectric layer material of matter layer is identical or different, and the regulation and control to threshold voltage are realized with this.
In the multi-Vt regulation and control method proposed by the present invention, the left side gate dielectric layer and the right side grid
The thickness of dielectric layers of dielectric layer is identical, and the top grid dielectric layer is situated between with the left side gate dielectric layer, the right side grid
The thickness of dielectric layers of matter layer is identical or different, and the regulation and control to threshold voltage are realized with this.
In the multi-Vt regulation and control method proposed by the present invention, the left side gate metal layer and the right side grid
The metal layer material of metal level is identical, the top grid metal level and the left side gate metal layer, right side grid gold
The metal layer material for belonging to layer is identical or different, and the regulation and control to threshold voltage are realized with this.
The beneficial effects of the present invention are：It is proposed by the present invention to realize multiple threshold voltage control models and possess
The new FinFET of three independant gate structures, can realize 5 kinds of different threshold value electricity in the case of without additional electric potential source
Press control model.In addition, by different-thickness, the selection respectively of the top and bottom gate dielectric layer of different kinds material,
The selection respectively of the top and bottom gate metal layer of different kinds material, it is possible to achieve device threshold voltage is freely adjusted,
The significant increase flexibility of circuit design.
Brief description of the drawings
Fig. 1 is the institute of method and step one for the new FinFET for possessing three independant gate structures according to present invention manufacture
The finished product schematic diagram of manufacture.
Fig. 2 is the institute of method and step two for the new FinFET for possessing three independant gate structures according to present invention manufacture
The finished product schematic diagram of manufacture.
Fig. 3 is the institute of method and step three for the new FinFET for possessing three independant gate structures according to present invention manufacture
The finished product schematic diagram of manufacture.
Fig. 4 is the institute of method and step four for the new FinFET for possessing three independant gate structures according to present invention manufacture
The finished product schematic diagram of manufacture.
Fig. 5 is the institute of method and step five for the new FinFET for possessing three independant gate structures according to present invention manufacture
The finished product schematic diagram of manufacture.
Fig. 6 is the institute of method and step six for the new FinFET for possessing three independant gate structures according to present invention manufacture
The finished product schematic diagram of manufacture.
Fig. 7 shows the floor map for the core process step that three independant gate structures are formed according to the present invention.
Fig. 8 (a)~(e) shows 5 kinds of different threshold values of the new FinFET for possessing three independant gate structures
Voltage mode control.
Embodiment
With reference to specific examples below and accompanying drawing, the present invention is described in further detail.The process of the implementation present invention,
Condition, experimental method etc., are the universal knowledege and common knowledge of this area, this hair in addition to the following content specially referred to
It is bright that content is not particularly limited.
It is proposed by the present invention to realize multiple threshold voltage control models and possess three independences refering to Fig. 1 to Fig. 6
The new FinFET of grid structure includes following structure：Substrate 1；Oxide skin(coating) 2, it is located at the surface of the substrate 1；Fin
Shape structure 3, it is located at the surface of the oxide skin(coating) 2, forms the channel region in center and the source region 3a and drain region 3b at two ends；Grid
Dielectric layer 5, it is vertically set on the channel region of the fin structure 3 and surrounds the channel region；The gate dielectric layer 5 is wrapped
Include：It is arranged on the left side gate dielectric layer 5a in the left side of fin structure 3, is arranged on the right side grid on the right side of fin structure 3
The pole dielectric layer 5b and top grid dielectric layer 5c for being arranged on the top of fin structure 3；Gate metal layer 4, it includes：
Left side gate metal layer 4a, it is located at the top grid dielectric layer 5c, the left side gate dielectric layer 5a and the oxide
Between layer 2；Right side gate metal layer 4b, it is located at the top grid dielectric layer 5c, the right side gate dielectric layer 5b and institute
State between oxide skin(coating) 2；Top grid metal level 4c, it is located at the top of the top grid dielectric layer 5c；Side wall 6, it sets
Put the both sides in the gate dielectric layer 5 and the gate metal layer 4.
Multiple threshold voltage control models can be realized on the present invention and possess the new of three independant gate structures
The detailed process manufacturing step of FinFET refers to Fig. 1~Fig. 6, the floor map of core process step needed for the device
Referring to Fig. 7, comprise the following steps that：
Step one：As shown in figure 1, forming fin structure 3.The material of Semiconductor substrate 1 can be that the elements such as silicon, germanium are partly led
Body or other semi-conducting materials, such as Group III-V compound semiconductor GaAs.1. the deposited oxide on silicon substrate 1
Nitride layer 2.Oxide skin(coating) 2 generally is less than or equal to the material of silica (k=3.9) to reduce parasitic electricity from dielectric constant
Hold.2. the deposited semiconductor layer on oxide skin(coating) 2, forms the structure of silicon (SOI, silicon on isolator) on insulating barrier.
3. deposition mas, photoetching, etching, the masking part needed for retaining above fin structure are carried out to mask.4. semiconductor layer is entered
Row photoetching, etching, form fin structure 3.The central area of fin structure 3 is used for as channel region, and its two ends is used to be formed
Source region 3a and drain region 3b.5. etching mask.The present invention, as substrate, can also equally select body silicon (bulk) conduct from SOI
Substrate.Deposition described above and follow-up described can be that PVD can also be CVD, for example evaporation, sputtering, LPCVD,
PECVD, MBE etc., according to specific material and device architecture characteristic reasonable selection.
Step 2：As shown in Fig. 2 being formed and fin structure contour gate dielectric layer 5a, 5b.1. gate dielectric layer is deposited
5, its material can be the material of the high-ks such as silicon nitride or hafnium oxide.2. by chemically mechanical polishing (CMP,
Chemical mechanical polish) mode, eliminate the gate dielectric layer at the top of fin structure 3 so that grid is situated between
The top and the top of fin structure 3 of matter layer 5 are contour.3. deposition mas, photoetching, etching are carried out to mask, retains fin structure 3
Central area namely channel region and ultra-thin gate dielectric layer around it above mask.4. light is carried out to gate dielectric layer 5
Carve, etching, only retain ultra-thin gate dielectric layer 5a, 5b around channel region.5. etching mask.
Step 3：As shown in figure 3, being formed and contour gate metal layer 4a, 4b of fin structure.1. gate metal layer is deposited
4, its material can be the metals such as polysilicon or Cu, Al.2. the grid above channel region is removed by way of CMP
Metal level 4, gate dielectric layer 5a, right side gate dielectric layer 5b, left side gate metal layer 4a on the left of the both sides formation of channel region
With right side gate metal layer 4b.Two gate metal layers 4a, 4b are separate in Fig. 3.
Step 4：As shown in figure 4, forming top grid dielectric layer 5c and top grid metal level 4c.1. in total
Upper deposition has certain thickness gate dielectric layer 5c, and its material can be identical with bottom grid dielectric layer 5a, 5b with thickness,
Can be different.2. photoetching, etching are carried out, only retains gate metal layer 4a, 4b, gate dielectric layer 5a, 5b and fin structure 3
Gate dielectric layer 5c above channel region.3. top grid metal level 4c is deposited over the entire structure, and its material can be with bottom
Gate metal layer 4a, 4b is identical, can also be different.4. photoetching, etching are carried out, only retains the top above top grid dielectric layer 5c
Portion gate metal layer 4c.5. top grid metal level 4c upper surface is caused to keep smooth by CMP.Three grid gold in Fig. 4
Belong to layer 4a, 4b, 4c separate.
Step 5：As shown in figure 5, forming the side wall 6 of gate metal layer both sides.In order to suppress hot carrier's effect (HCE,
Hot carrier effect) influence to gate metal layer, deposit side wall in the both sides of gate metal layer 4, fin structure 3
(spacer) 6, its material is the material of the high-ks such as silicon nitride.
Step 6：As shown in fig. 6, forming source region 3a and drain region 3b at the two ends of fin structure 3.1. deposit over the entire structure
Relatively thin metal level, its material can be cobalt (Co), nickel (Ni) or nickel platinum alloy.2. self-aligned silicide process is carried out
(Salicide), the intrinsic silicon at the two ends of fin structure 3 reacts to form metal silicide with metal level, and etching remainder is not
The metal level of reaction, just can obtain the source region 3a and drain region 3b being made up of metal silicide outside side wall 6.3. to source region 3a and
Drain region 3b is doped, and adulterate the atoms such as P, As, Te to N-type device；To atoms such as P-type device doping B, Al, Ga, In.
Above-mentioned technological process and the technological process for preparing HKMG FinFET in industry using preceding grid technique (gate-first)
Roughly the same, the main distinction is concentrated on Step 2: three, four.Fig. 7 illustrates present invention manufacture with the mode of planar technology figure can
Realize multiple threshold voltage control models and possess unique work needed for the new FinFET of three independant gate structures
Skill.
The present invention proposes that a kind of regulation and control realized from circuit aspect possess the new FinFET of three independant gate structures
The mode of the threshold voltage of device, in the case of without additional electric potential source, by being independently controlled to three gate metal layers,
At most 5 kinds different threshold voltage control models can be achieved.Fig. 8 gives this 5 kinds different threshold voltage control models, respectively
Represented with (a)~(e).
1. shown in the first threshold voltage control model such as Fig. 8 (a).Device only top grid metal level 4c connects power supply electricity
Press (VDD).In order to preferably suppress short-channel effect, in FinFET fin structure (fin), fin height is typically long-range
Fin height is taken as 42 nanometers in fin width, such as intel 14nm FinFET, and fin width is taken as 8 nanometers, therefore
Channel region only has the zone controlled system at top in Fig. 8 (a), and the top width of channel region is very narrow, now the grid-control energy of device
Power is worst, and threshold voltage reaches the maximum in 5 kinds of threshold voltage control models.
2. shown in second of threshold voltage control model such as Fig. 8 (b).Device only has left side gate metal layer 4a to connect high electricity
Flat, channel region only has the zone controlled system in left side, and the grid-control ability of device is slightly better than Fig. 8 (a), and now the threshold voltage of device is same
Sample is very big, only more smaller than Fig. 8 (a).
3. shown in the third threshold voltage control model such as Fig. 8 (c).The left side gate metal layer 4a and top grid of device
Metal level 4c connects high level, and the left side of channel region and the region at top are controlled, and the grid-control ability of device is significantly increased, threshold value
Voltage is less than Fig. 8 (b).
4. shown in the 4th kind of threshold voltage control model such as Fig. 8 (d).The left side gate metal layer 4a of device and right side grid
Metal level 4b connects high level, and the left side of channel region and the region on right side are controlled, and the grid-control ability of device is better than Fig. 8 (c), because
This threshold voltage is again smaller than Fig. 8 (c).
5. shown in the 5th kind of threshold voltage control model such as Fig. 8 (e).Three gate metal layers of device connect high level,
The region in the left side of channel region, right side and top is controlled, and the grid-control ability of device reaches most strong, and now threshold voltage also reaches
To the minimum value in 5 kinds of threshold voltage control models.
In summary, in 5 kinds of different threshold voltage control models, because the grid-control ability of device is different, threshold value electricity
The sequence of pressure size is followed successively by：(a)>(b)>(c)>(d)>(e).
During due to preparing device in technique, the left side gate metal layer 4a and right side gate metal layer 4b of device are symmetrical,
So above-mentioned 5 kinds different threshold voltage control models have ignored following two situations：1. device only has right side grid gold
Category layer 4b connects high level (identical with Fig. 8 (b))；2. the right side gate metal layer 4b and top grid metal level 4c of device connect high electricity
Flat (identical with Fig. 8 (c)).In addition, when three gate metal layers of device are grounded, device is off state, does not deposit
In threshold voltage.Therefore, the new FinFET for possessing three independant gate structures can at most provide 5 kinds of different threshold values
Voltage mode control.
The present invention also proposes that three kinds of regulation and control realized from technique aspect possess the new of three independant gate structures
The mode of the threshold voltage of FinFET：
1. top grid dielectric layer 5c and left side gate dielectric layer 5a, the kind of right side gate dielectric layer 5b dielectric layer material
Class is chosen different.Because the material selection difference of gate dielectric layer influences whether effective gate oxide thickness (EOT), therefore change
The material of gate dielectric layer can make a big impact to the grid-control ability of device, and then have influence on the size of threshold voltage.In Fig. 7
In, because top grid dielectric layer 5c and left side gate dielectric layer 5a, right side gate dielectric layer 5b are separately deposited, therefore can
With by selecting the material category of the different gate dielectric layers of top and bottom to realize the regulation and control of device threshold voltage, such as left side grid
Pole dielectric layer 5a and right side gate dielectric layer 5b are from material of the hafnium oxide as dielectric layer, and top grid dielectric layer 5c
From material of the silicon nitride as dielectric layer.
2. top grid dielectric layer 5c and left side gate dielectric layer 5a, right side gate dielectric layer 5b thickness of dielectric layers are chosen
It is different.With 1. similarly, the threshold voltage influence of different gate dielectric layer thickness on device is very big.Therefore can be by selecting to push up
The thickness of portion's gate dielectric layer different from bottom realizes the regulation and control of device threshold voltage, for example left side gate dielectric layer 5a and right side
Gate dielectric layer 5b thickness of dielectric layers is 5 nanometers, and top grid dielectric layer 5c thickness of dielectric layers is 4 nanometers.
3. top grid metal level 4c and left side gate metal layer 4a, the material kind of right side gate metal layer 4b metal level
Class is chosen different.Because the material selection difference of gate metal layer influences whether metal work function (work-function) no
Together, and then the size of threshold voltage is had influence on.In the figure 7, due to top grid metal level 4c be with left side gate metal layer 4a,
Right side gate metal layer 4b is separately deposited, therefore can be by selecting the material category of the different gate metal layer of top and bottom
The regulation and control of device threshold voltage are realized, for example left side gate metal layer 4a, right side gate metal layer 4b are made from metal " aluminium "
For the material of metal level, and top grid metal level 4c is from material of the metal " tungsten " as metal level.
The protection content of the present invention is not limited to above example.Under the spirit and scope without departing substantially from inventive concept, this
Art personnel it is conceivable that change and advantage be all included in the present invention, and using appended claims as protect
Protect scope.
Claims (4)
1. a kind of multi-Vt regulation and control method of new FinFET for possessing three independant gate structures, its feature exists
In the new FinFET includes：
Substrate (1)；
Oxide skin(coating) (2), it is located at the surface of the substrate (1)；
Fin structure (3), it is located at the surface of the oxide skin(coating) (2), forms the channel region in center and the source region (3a) at two ends
With drain region (3b)；
Gate dielectric layer (5), it is vertically set on the channel region of the fin structure (3) and surrounds the channel region；It is described
Gate dielectric layer (5) includes：It is arranged on the left side gate dielectric layer (5a) on the left of the fin structure (3), is arranged on the fin
Right side gate dielectric layer (5b) on the right side of shape structure (3) and the top grid medium being arranged at the top of the fin structure (3)
Layer (5c)；
Gate metal layer (4), it includes：
Left side gate metal layer (4a), its be located at the top grid dielectric layer (5c), the left side gate dielectric layer (5a) and
Between the oxide skin(coating) (2)；
Right side gate metal layer (4b), its be located at the top grid dielectric layer (5c), the right side gate dielectric layer (5b) and
Between the oxide skin(coating) (2)；
Top grid metal level (4c), it is located at the top of the top grid dielectric layer (5c)；And
Side wall (6), it is arranged on the both sides of the gate dielectric layer (5) and the gate metal layer (4)；
In the case of without additional electric potential source, to the left side gate metal layer (4a), the right side gate metal layer (4b), institute
State top grid metal level (4c) and apply supply voltage (VDD) or ground connection respectively, realize five kinds of different threshold voltage control moulds
Formula.
2. multi-Vt as claimed in claim 1 regulates and controls method, it is characterised in that the left side gate dielectric layer (5a) with
The dielectric layer material of the right side gate dielectric layer (5b) is identical, and the top grid dielectric layer (5c) is situated between with the left side grid
Matter layer (5a), the right side gate dielectric layer (5b) dielectric layer material it is identical or different, the tune to threshold voltage is realized with this
Control.
3. multi-Vt as claimed in claim 1 regulates and controls method, it is characterised in that the left side gate dielectric layer (5a) with
The thickness of dielectric layers of the right side gate dielectric layer (5b) is identical, and the top grid dielectric layer (5c) is situated between with the left side grid
Matter layer (5a), the right side gate dielectric layer (5b) thickness of dielectric layers it is identical or different, the tune to threshold voltage is realized with this
Control.
4. multi-Vt as claimed in claim 1 regulates and controls method, it is characterised in that the left side gate metal layer (4a) with
The metal layer material of the right side gate metal layer (4b) is identical, the top grid metal level (4c) and left side grid gold
Belong to layer (4a), the right side gate metal layer (4b) metal layer material it is identical or different, the tune to threshold voltage is realized with this
Control.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110190111A (en) * | 2019-05-06 | 2019-08-30 | 清华大学 | A kind of multiple-grid three-dimensional manometer line transistor and preparation method thereof |
| CN110544717A (en) * | 2019-08-08 | 2019-12-06 | 宁波大学 | Three independent gate FinFET devices |
| US10886393B2 (en) * | 2017-10-17 | 2021-01-05 | Mitsubishi Electric Research Laboratories, Inc. | High electron mobility transistor with tunable threshold voltage |
| FR3114686A1 (en) * | 2020-09-30 | 2022-04-01 | Stmicroelectronics (Rousset) Sas | Triple-gate MOS transistor and method of manufacturing such a transistor |
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|---|---|---|---|---|
| CN103165459A (en) * | 2011-12-15 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Fin field effect transistor and manufacturing method of the same |
| CN106206689A (en) * | 2016-07-27 | 2016-12-07 | 华东师范大学 | It is applicable to the FinFET possessing independent three grid structures of memory element |
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2017
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103165459A (en) * | 2011-12-15 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Fin field effect transistor and manufacturing method of the same |
| CN106206689A (en) * | 2016-07-27 | 2016-12-07 | 华东师范大学 | It is applicable to the FinFET possessing independent three grid structures of memory element |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10886393B2 (en) * | 2017-10-17 | 2021-01-05 | Mitsubishi Electric Research Laboratories, Inc. | High electron mobility transistor with tunable threshold voltage |
| CN110190111A (en) * | 2019-05-06 | 2019-08-30 | 清华大学 | A kind of multiple-grid three-dimensional manometer line transistor and preparation method thereof |
| CN110544717A (en) * | 2019-08-08 | 2019-12-06 | 宁波大学 | Three independent gate FinFET devices |
| CN110544717B (en) * | 2019-08-08 | 2023-03-10 | 宁波大学 | Three independent gate FinFET devices |
| FR3114686A1 (en) * | 2020-09-30 | 2022-04-01 | Stmicroelectronics (Rousset) Sas | Triple-gate MOS transistor and method of manufacturing such a transistor |
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