CN107123636B - Integrated circuit device - Google Patents
Integrated circuit device Download PDFInfo
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- CN107123636B CN107123636B CN201610104420.3A CN201610104420A CN107123636B CN 107123636 B CN107123636 B CN 107123636B CN 201610104420 A CN201610104420 A CN 201610104420A CN 107123636 B CN107123636 B CN 107123636B
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- pad
- line
- integrated circuit
- wire
- bonding wire
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
Abstract
The invention discloses an integrated circuit device, which comprises a transmission line, wherein the transmission line comprises a first grounding wire and a first signal wire. The first grounding wire comprises a first pad, a second pad and a first bonding wire, wherein the first bonding wire is a routing structure and is connected with the first pad and the second pad. The first signal line comprises a third pad, a fourth pad and a second bonding wire, wherein the second bonding wire is a routing structure and is connected with the third pad and the fourth pad. Thus, the transmission line occupies only a small amount of integrated circuit area and can provide a sufficiently low characteristic impedance.
Description
Technical Field
The present invention relates to integrated circuit devices, and more particularly to a transmission line in an integrated circuit device.
Background
Ordinary cables are sufficient to carry low frequency ac and acoustic signals, and transmission lines use special structures and impedance matching methods to carry the electromagnetic signals to the receiving end with minimal reflection and minimal power loss. A significant feature of most transmission lines is that they have uniform cross-sectional dimensions along their length, so that the transmission lines have a uniform impedance, known as the characteristic impedance, thereby preventing reflections from occurring. Transmission lines have various forms such as parallel lines (ladder lines, twisted pair lines), coaxial cables, strip lines, and microstrip lines. The frequency of the electromagnetic wave is inversely proportional to the wavelength. When the length of the cable is comparable to the wavelength of the transmitted signal, a transmission line must be used.
Transmission lines are also used in integrated circuit devices, which are typically fabricated as coplanar waveguide structures with signal lines parallel to ground lines, or as stripline structures with signal lines surrounded by ground lines. However, to maintain a sufficiently low characteristic impedance of the transmission line, the transmission line must occupy a sufficiently large area. As the size of integrated circuits is made smaller and smaller, the parasitic capacitance is increased and larger due to advanced processes, and it becomes more and more difficult to design transmission lines in the integrated circuits.
Disclosure of Invention
In view of the above, it is an object of the present invention to fabricate a transmission line of an integrated circuit device that does not occupy or occupies only a small amount of integrated circuit area and can provide a sufficiently low characteristic impedance.
An embodiment of the present invention provides an integrated circuit device, which includes a transmission line including a first ground line and a first signal line. The first ground wire includes a first pad, a second pad and a first bonding wire, which is a wire bonding structure connecting the first pad and the second pad. The first signal line comprises a third pad, a fourth pad and a second bonding wire, which is a wire bonding structure and connects the third pad and the fourth pad.
An embodiment of the present invention provides an integrated circuit device, including a transmission line including a signal line and a ground line, wherein one of the signal line and the ground line includes a first pad, a second pad and a first bonding wire, which is a wire bonding structure connecting the first pad and the second pad, and wherein the other of the signal line and the ground line includes a top metal layer disposed on a dielectric layer.
The invention has the advantages that part or all of the grounding wires and/or signal wires of the transmission line of the embodiment of the invention adopt the bonding wire structure in a routing mode, the structure can save the space occupied by the transmission line of the integrated circuit, and can realize low characteristic impedance and larger Q value than the traditional chip transmission line. The smaller the size of the integrated circuit is made, the more the variation of the integrated circuit design can be increased, so that the characteristics of the integrated circuit device are not reduced due to the smaller size, the difficulty of the integrated circuit design can be reduced, and the flexibility of the integrated circuit design can be increased. In addition, the transmission line and the chip metal line in a routing mode have less coupling (coupling) effect.
Drawings
Fig. 1 is a perspective view of a transmission line of an integrated circuit device according to an embodiment of the invention.
Fig. 2 is a schematic perspective view of a transmission line of an integrated circuit device according to an embodiment of the invention.
Fig. 3 is a perspective view of a transmission line of an integrated circuit device according to an embodiment of the invention.
Fig. 4 is a perspective view of a transmission line of an integrated circuit device according to an embodiment of the invention.
Fig. 5 is a schematic perspective view of a transmission line of an integrated circuit device according to an embodiment of the invention.
Fig. 6 is a schematic perspective view of a transmission line of an integrated circuit device according to an embodiment of the invention.
Fig. 7 is a perspective view of a transmission line of an integrated circuit device according to an embodiment of the invention.
Fig. 8 shows the measured inductance versus frequency.
FIG. 9A is a schematic plan view of a transmission line of an integrated circuit device according to an embodiment of the invention.
FIG. 9B is a cross-sectional view of a transmission line of an integrated circuit device according to an embodiment of the invention.
FIG. 10A is a schematic plan view of a transmission line of an integrated circuit device according to an embodiment of the invention.
FIG. 10B is a cross-sectional view of a transmission line of an integrated circuit device according to an embodiment of the invention.
Wherein the reference numerals are as follows:
102: transmission line
104: grounding wire
106: signal line
108: first pad
110: second pad
112: first bonding wire
114: third pad
116: fourth pad
118: second bonding wire
202: first grounding wire
204: second grounding wire
206: signal line
208: first pad
210: second pad
212: first bonding wire
214: third pad
216: fourth pad
218: second bonding wire
219: fifth pad
220: sixth pad
222: third bonding wire
302: first grounding wire
304: first signal line
306: second signal line
308: second grounding wire
310: first pad
312: second pad
314: first bonding wire
316: third pad
318: fourth pad
320: second bonding wire
322: fifth pad
324: sixth pad
326: third bonding wire
328: seventh pad
330: eighth pad
332: fourth bonding wire
402: grounding wire
404: signal line
406: first pad
408: second pad
410: first bonding wire
412: second bonding wire
414: fourth pad
416: second bonding wire
502: first grounding wire
504: signal line
506: second grounding wire
508: first pad
510: second pad
512: first bonding line
514: third pad
516: fourth pad
518: second bonding wire
520: fifth pad
522: sixth pad
524: third bonding wire
602: grounding wire
604: signal line
606: a first outer part
608: a first inner part
610: first pad
612: second pad
614: first bonding wire
616: dielectric layer
618: first conductive line
620: second outer part
622: second inner part
624: third pad
626: fourth pad
628: second bonding wire
630: second conductive line
702: grounding wire
704: signal line
706: a first outer part
708: a first inner part
710: first pad
712: first bonding wire
714: second pad
716: dielectric layer
718: first conductive line
720: second outer part
722: second inner part
724: third pad
726: fourth pad
728: second bonding wire
730: second conductive line
902: first grounding wire
904: signal line
906: second grounding wire
908: first pad
910: second pad
912: first bonding wire
914: third pad
916: fourth pad
918: second bonding wire
920: dielectric layer
922: a first metal layer
924: second metal layer
926: a third metal layer
928: a fourth metal layer
930: fifth metal layer
932: a sixth metal layer
1002: signal line
1004: grounding wire
1006: first pad
1008: second pad
1010: first bonding wire
1012: first opening
1013: dielectric layer
1014: second opening
1016: a first metal layer
1018: second metal layer
1020: a third metal layer
1022: a fourth metal layer
1024: fifth metal layer
1026: a sixth metal layer
1028: the first conductive connection
1030: second conductive connection
1032: third conductive connection
1034: the fourth conductive connection
1036: the fifth conductive connection
1038: the sixth conductive connection
Detailed Description
The following embodiments of the present disclosure relating to "transmission line of integrated circuit device" will be described by specific examples, and the following embodiments will further describe the related art of the present disclosure in detail, but the disclosure is not intended to limit the technical scope of the present disclosure.
The present invention discloses a transmission line inside an integrated circuit chip, which is formed by a signal line with a metal layer, a plurality of metal layers and a conductive grounding line, but in order to maintain a sufficiently low characteristic impedance, and with the miniaturization of the integrated circuit size, the transmission line of the above type occupies a relatively large area inside the integrated circuit, so that the integrated circuit design becomes relatively difficult. Therefore, the invention makes the grounding wire and the signal wire of the integrated circuit transmission line or one of the grounding wire and the signal wire into a routing structure, which does not occupy the area of the internal area of the integrated circuit, and makes the design of the integrated circuit easier.
(first embodiment)
Fig. 1 is a perspective view of a transmission line of an integrated circuit device according to the present embodiment, as shown in fig. 1, the transmission line includes a ground line 104 and a signal line 106, the ground line 104 includes a first pad 108, a second pad 110 and a first bonding wire (bonding wire)112, wherein the first bonding wire 112 is in a wire bonding structure and connects the first pad 108 and the second pad 110. The signal line 106 includes a third pad 114, a fourth pad 116, and a second bonding wire 118, wherein the second bonding wire 118 is a wire bonding structure and connects the third pad 114 and the fourth pad 116.
Although fig. 1 shows only one GS-type transmission line 102 including a ground line 104 and a signal line 106, in practice, several such transmission lines 102 may be included in an integrated circuit, depending on design requirements, and the number, length and size of the transmission lines are not particularly limited. The preferred lengths used are 500-1500 μm, wire diameters 18-25 μm and pitches 5-15 μm. In addition, the present invention is not particularly limited to the GS type transmission line of fig. 1. As shown in fig. 2, the transmission line 100 of the present invention may also be a GSG type according to another embodiment of the present invention, that is, the transmission line of the present embodiment includes two ground lines 202 and 204 and a signal line 206 between the two ground lines 202 and 204. More specifically, the transmission line of the present embodiment includes a first ground line 202, a signal line 206 and a second ground line 204, wherein the signal line 206 is disposed between the first ground line 202 and the second ground line 204. The first ground line 202 includes a first pad 208, a second pad 210, and a first bonding wire 212, wherein the first bonding wire 212 is in a wire bonding structure and connects the first pad 208 and the second pad 210. The signal line 206 includes a third pad 214, a fourth pad 216, and a second bonding wire 218, wherein the second bonding wire 218 is a wire bonding structure and connects the third pad 214 and the fourth pad 216. The second ground line 204 includes a fifth pad 219, a sixth pad 220, and a third bonding wire 222, wherein the third bonding wire 222 is a wire bonding structure and connects the fifth pad 219 and the sixth pad 220.
As shown in fig. 3, another embodiment of the present invention may also be a GSSG type transmission line, that is, the transmission line of the present embodiment includes two ground lines and two signal lines, and the signal line is located between the two ground lines. More specifically, the transmission line of the present embodiment includes a first ground line 302, a first signal line 304, a second signal line 306, and a second ground line 308, which are sequentially arranged along a direction. The first ground line 302 includes a first pad 310, a second pad 312, and a first bonding wire 314, wherein the first bonding wire 314 is in a wire bonding structure and connects the first pad 310 and the second pad 312. The first signal line 306 includes a third pad 316, a fourth pad 318, and a second bonding wire 320, wherein the second bonding wire 320 is a wire bonding structure and connects the third pad 316 and the fourth pad 318. The second ground line 308 includes a fifth pad 322, a sixth pad 324, and a third bonding wire 326, wherein the third bonding wire 326 is a wire bonding structure and connects the fifth pad 322 and the sixth pad 324. The second signal line 306 includes a seventh pad 328, an eighth pad 330, and a fourth bonding wire 332, wherein the fourth bonding wire 332 is a bonding wire structure connecting the seventh pad 328 and the eighth pad 330.
The ground lines and the signal lines of the transmission lines of fig. 1, 2 and 3 are arranged in parallel, but the present invention is not limited to this. Fig. 4 is a perspective view of a transmission line according to another embodiment of the invention, as shown in fig. 4, the transmission line of this embodiment includes a ground line 402 and a signal line 404, wherein the ground line 402 and the signal line 404 of this embodiment are arranged longitudinally, such that a first pad 406 and a second pad 408 of the ground line 402 are located on the same straight line as a third pad 412 and a fourth pad 414 of the signal line 404, and the first bonding wire 410 and the second bonding wire 412 are also arranged longitudinally. In more detail, the first bonding wire 410 and the second bonding wire 412 are not parallel, but have a top-bottom relationship. As shown in fig. 4, in the state where the signal line 404 is located inside the ground line 402, the first bonding wire 410 is located substantially above the second bonding wire 416.
Fig. 5 is a schematic perspective view of a transmission line according to another embodiment of the present invention, as shown in fig. 5, the transmission line of the present embodiment is a GSG type transmission line, and the transmission line includes a first ground line 502, a signal line 504 and a second ground line 506, in the present embodiment, the first ground line 502 and the signal line 504 are arranged longitudinally, and the second ground line 506 and the signal line 504 are arranged horizontally. In more detail, the first pad 508 and the second pad 510 of the first ground line 502 are located on the same straight line as the third pad 514 and the fourth pad 516 of the signal line 504, and the first bonding wire 512 and the second bonding wire 518 are also arranged longitudinally, so that a part of the first bonding wire 512 and the second bonding wire 518 are in a top-bottom relationship. The fifth pad 520 of the second ground line 506 is horizontally disposed with the third pad 514 of the signal line 504, the sixth pad 522 of the second ground line 506 is horizontally disposed with the fourth pad 516 of the signal line 504, and the third bonding wire 524 of the second ground line 506 is parallel to the second bonding wire 518 of the signal line 504.
(second embodiment)
Fig. 6 is a schematic perspective view of a transmission line of the present embodiment, which is different from the embodiment of fig. 1 in that the ground line and the signal line of the transmission line of the embodiment of fig. 1 are entirely in the form of bonding wires on an integrated circuit, and in comparison, the ground line and a part of the signal line of the transmission line of the present embodiment are in the form of conductive wires on a dielectric layer of the integrated circuit, and a part of the signal line is in the form of bonding wires on the integrated circuit.
Referring to fig. 6, the transmission line of the present embodiment includes a ground line 602 and a signal line 604, the ground line 602 includes a first outer portion 606 and a first inner portion 608, wherein the first outer portion 606 includes a first pad 610, a second pad 612 and a first bonding wire 614, the first bonding wire 614 is a wire bonding structure and connects the first pad 610 and the second pad 612, and the first inner portion 608 is a first conductive line 618 disposed on a dielectric layer 616. The signal line 604 includes a second outer portion 620 and a second inner portion 622, wherein the second outer portion 620 includes a third pad 624, a fourth pad 626 and a second bonding wire 628, the second bonding wire 628 is a wire bonding structure and connects the third pad 624 and the fourth pad 626, and the second inner portion 622 is a second conductive wire 630 disposed on the dielectric layer 616.
This embodiment is more flexible in the design of the integrated circuit by having a portion of the ground line 602 and a portion of the signal line 604 in the form of conductive lines 618, 630 of the integrated circuit on the dielectric layer 616 and a portion in the form of bonding wires 614, 628 on the integrated circuit.
Fig. 7 is a schematic perspective view of another embodiment of a transmission line, which is different from the embodiment of fig. 6 in that a first bonding wire 614 of a ground line 602 of the embodiment of fig. 6 is disposed in parallel with a second bonding wire 628 of a signal line 604, and the first bonding wire of the ground line and the second bonding wire of the signal line are disposed alternately. In more detail, as shown in fig. 7, the transmission line of the present embodiment includes a ground line 702 and a signal line 704, the ground line 702 includes a first outer portion 706 and a first inner portion 708, wherein the first outer portion 706 includes a first pad 710, a second pad 714 and a first bonding wire 712, the first bonding wire 712 is a wire bonding structure and connects the first pad 710 and the second pad 714, and the first inner portion 708 is a first conductive wire 718 disposed on the dielectric layer 716. The signal line 704 includes a second outer portion 720 and a second inner portion 722, wherein the second outer portion 720 includes a third pad 724, a fourth pad 726 and a second bonding wire 728, the second bonding wire 728 is a wire bonding structure and connects the third pad 724 and the fourth pad 726, and the second inner portion 722 is a second conductive wire 730 disposed on the dielectric layer 716. In the present embodiment, the first bonding wires 712 of the ground line 702 are staggered from the second bonding wires 728 of the signal line 704.
In view of whether the transmission line of the present invention generates radiation, an electric pole is disposed below the transmission line of the embodiment of fig. 1, and a relationship diagram of measured inductance and frequency and a Q value are shown in fig. 8, as shown in fig. 8, the inductance measured by the electric pole disposed below the transmission line of the embodiment of fig. 1 is not attenuated, and only affects about 3% of the Q value.
(third embodiment)
Unlike the above embodiments in which the ground lines and the signal lines are both in the form of bonding wires, the present embodiment only uses the form of bonding wires for the ground lines, and uses the form of integrated circuit wires for the signal lines. Fig. 9A shows a plan view of the transmission line of the present embodiment, and fig. 9B shows a schematic cross-sectional view taken along a hatching of IXB-IXB of fig. 9A. Referring to fig. 9A and 9B, the present embodiment is illustrated by using an example of a GSG transmission line, the transmission line of the present embodiment includes a first ground line 902, a signal line 904, and a second ground line 906, the first ground line 902 includes a first pad 908, a second pad 910, and a first bonding wire 912, and the first bonding wire 912 is a wire bonding structure and connects the first pad 908 and the second pad 910. The second ground line 906 includes a third pad 914, a fourth pad 916, and a second bonding wire 918, and the second bonding wire 918 is a wire bonding structure and connects the third pad 914 and the fourth pad 916. The signal line 904 is a top metal layer on a dielectric layer 920 of the integrated circuit. As shown in fig. 9A and 9B, in the present embodiment, the first pad 908, the second pad 910, the third pad 914 and the fourth pad 916 may be located at the same layer as the top metal layer 904, but the present invention is not limited thereto, and the first pad 908, the second pad 910, the third pad 914 and the fourth pad 916 may be located at a different layer from the top metal layer 904. As shown in fig. 9B, the signal line 904 includes a plurality of metal layers in the dielectric layer 920, such as a first metal layer 922, a second metal layer 924, a third metal layer 926, a fourth metal layer 928, a fifth metal layer 930, and a sixth metal layer 932 from bottom to top in sequence. However, the above is merely an example and fig. 9B is a schematic diagram, in fact, the signal line 904 of the integrated circuit device may include more or less metal layers, logic units such as transistors may be disposed below the metal layers, and memory units such as capacitors may be included.
It should be noted that the bonding wire structure of the transmission line of the present invention belongs to an internal circuit in a chip, and the size and the purpose of the bonding wire structure are different from those of the bonding wire used for connecting the metal pad and the lead frame.
(fourth embodiment)
Fig. 10A shows a plan view of the transmission line of the present embodiment, and fig. 10B shows a schematic cross-sectional view taken along an XB-XB section line of fig. 10A. Referring to fig. 10A and 10B, the present embodiment is illustrated by using an example of a GS transmission line, the transmission line of the present embodiment includes a signal line 1002 and a ground line 1004, the signal line 1002 includes a first pad 1006, a second pad 1008 and a first bonding wire 1010, and the first bonding wire 1010 is a wire bonding structure and connects the first pad 1006 and the second pad 1008. Ground line 1004 is shown in set 10A, with ground line 1004 (top metal layer) surrounding first pad 1006 and surrounding second pad 1008. In more detail, a first opening 1012 and a second opening 1014 are formed in the ground line 1004 (top metal layer), and the first pad 1006 of the signal line 1002 is located in the first opening 1012 and the second pad 1008 of the signal line 1002 is located in the second opening 1014. As shown in fig. 10B, a plurality of metal layers located in the dielectric layer 1013 are formed under the top metal layer 1004, such as a first metal layer 1016, a second metal layer 1018, a third metal layer 1020, a fourth metal layer 1022, a fifth metal layer 1024 and a sixth metal layer 1026, and a first conductive link 1028, a second conductive link 1030, a third conductive link 1032, a fourth conductive link 1034, a fifth conductive link 1036 and a sixth conductive link 1038 are located in the dielectric layer 1013 to connect the metal layers on the upper and lower sides.
(possible technical effects of the embodiment)
In summary, the present invention has the beneficial effects that part or all of the ground lines and/or signal lines of the transmission line in the embodiment of the present invention adopt a bonding line structure in a wire bonding manner, which can save the space occupied by the transmission line of the integrated circuit and can realize low characteristic impedance and a larger Q value than the conventional chip transmission line. The smaller the size of the integrated circuit is made, the more the variation of the integrated circuit design can be increased, so that the characteristics of the integrated circuit device are not reduced due to the smaller size, the difficulty of the integrated circuit design can be reduced, and the flexibility of the integrated circuit design can be increased. In addition, the transmission line and the chip metal line in a routing mode have less coupling (coupling) effect.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, so that equivalent technical changes made by using the contents of the present specification and the drawings are included in the scope of the present invention.
Claims (9)
1. An integrated circuit device, comprising:
a transmission line comprising:
a first ground line, comprising:
a first pad;
a second pad; and
a first bonding wire, which is a wire bonding structure, connecting the first pad and the second pad;
a first signal line, comprising:
a third pad;
a fourth pad; and
a second bonding wire, which is a wire bonding structure and connects the third pad and the fourth pad; wherein the integrated circuit device comprises a chip, and the transmission line is located inside the chip, and the length of the transmission line is 500-1500 μm.
2. The integrated circuit device of claim 1, the transmission line further comprising a second ground line comprising:
a fifth pad;
a sixth pad; and
a third bonding wire, which is a wire bonding structure, connecting the fifth pad and the sixth pad.
3. The integrated circuit device of claim 2, the transmission line further comprising a second signal line comprising:
a seventh pad;
an eighth pad; and
a fourth bonding wire, which is a wire bonding structure, connecting the seventh pad and the eighth pad.
4. The integrated circuit device of claim 1, wherein the first ground line is arranged in parallel with the first signal line.
5. The integrated circuit device of claim 1, wherein the first ground line and the first signal line are arranged vertically.
6. The integrated circuit device of claim 2, wherein the first ground line and the first signal line are arranged longitudinally, and the second ground line and the first signal line are arranged in parallel.
7. The integrated circuit device of claim 1, wherein the first ground line further comprises a first inner portion that is a first conductive line formed on a dielectric layer, and the first signal line further comprises a second inner portion that is a second conductive line formed on the dielectric layer.
8. The integrated circuit device of claim 1, wherein the first ground line is interleaved with the first signal line.
9. The integrated circuit device according to claim 1, further comprising a third bond wire connected to a lead frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610104420.3A CN107123636B (en) | 2016-02-25 | 2016-02-25 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610104420.3A CN107123636B (en) | 2016-02-25 | 2016-02-25 | Integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107123636A CN107123636A (en) | 2017-09-01 |
| CN107123636B true CN107123636B (en) | 2020-01-10 |
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|---|---|---|---|
| CN201610104420.3A Active CN107123636B (en) | 2016-02-25 | 2016-02-25 | Integrated circuit device |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6812580B1 (en) * | 2003-06-09 | 2004-11-02 | Freescale Semiconductor, Inc. | Semiconductor package having optimized wire bond positioning |
| CN104143541A (en) * | 2013-05-09 | 2014-11-12 | 矽品精密工业股份有限公司 | Wire bonding structure |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1290185C (en) * | 2001-12-21 | 2006-12-13 | 矽统科技股份有限公司 | Integrated circuit package device and its manufacturing method |
| TWM242851U (en) * | 2002-10-11 | 2004-09-01 | Siliconware Precision Industries Co Ltd | Electrically and thermally enhanced semiconductor device |
| JP4533173B2 (en) * | 2004-02-24 | 2010-09-01 | キヤノン株式会社 | Semiconductor integrated circuit device |
| KR100586278B1 (en) * | 2004-12-07 | 2006-06-08 | 삼성전자주식회사 | Printed circuit board with bonding wire shield structure for high speed semiconductor package |
| TW201032486A (en) * | 2009-02-23 | 2010-09-01 | Ralink Technology Corp | Chip and transmitter for wireless communication system |
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2016
- 2016-02-25 CN CN201610104420.3A patent/CN107123636B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6812580B1 (en) * | 2003-06-09 | 2004-11-02 | Freescale Semiconductor, Inc. | Semiconductor package having optimized wire bond positioning |
| CN104143541A (en) * | 2013-05-09 | 2014-11-12 | 矽品精密工业股份有限公司 | Wire bonding structure |
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| Publication number | Publication date |
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| CN107123636A (en) | 2017-09-01 |
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