CN107103251B - Processor including a mapping access interface - Google Patents
Processor including a mapping access interface Download PDFInfo
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- CN107103251B CN107103251B CN201710282701.2A CN201710282701A CN107103251B CN 107103251 B CN107103251 B CN 107103251B CN 201710282701 A CN201710282701 A CN 201710282701A CN 107103251 B CN107103251 B CN 107103251B
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- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/74—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information operating in dual or compartmented mode, i.e. at least one secure mode
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- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
- G06F21/62—Protecting access to data via a platform, e.g. using keys or access control rules
- G06F21/6218—Protecting access to data via a platform, e.g. using keys or access control rules to a system of files or objects, e.g. local or distributed file system or database
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Abstract
The invention provides a processor including a mapping access interface. The processor includes: the system comprises an instruction execution unit, a first mode resource storage unit, a second mode resource storage unit and a mapping access interface, wherein the instruction execution unit is connected with the first mode resource storage unit, the second mode resource storage unit and the mapping access interface, and the first mode resource storage unit is used for storing resource information of a processor in a first mode; the second mode resource storage unit is used for storing the resource information of the processor in a second mode; and the mapping access interface is connected with the second mode resource storage unit. The invention can improve the working efficiency of the processor and reduce the power consumption of the processor.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a processor including a mapping access interface.
Background
With the continuous development of informatization, the reliability of a system becomes more and more important, the traditional software-level-based reliability protection has lower and lower security, and hackers can directly attack an operating system beyond software protection and then steal sensitive software and hardware resources; therefore, in order to make up for the shortfall of the trustworthiness protection at the software level, a trusted framework is proposed which aims to provide the system with an underlying hardware protection mechanism outside the software.
The specific idea of the trusted framework design is as follows: adding a credible mode in the running mode of the processor, abstracting a credible kernel in the system, and dividing the processor in the credible mode, the system IP with credible attribute and other sensitive and important software and hardware resources in the system into the credible kernel; furthermore, the hardware mechanism ensures that the resources in the trusted kernel can only be accessed by the trusted mode, thereby realizing the isolation of the trusted kernel and the untrusted kernel and ensuring the confidentiality and the integrity of the trusted resources.
Meanwhile, a mapping access interface is arranged in the processor, and the mapping access interface can enable the trusted kernel to safely access resources under the untrusted kernel, so that the safe interaction of kernel resources is realized; the processor comprising the mapping access interface virtualizes a trusted kernel and an untrusted kernel in a physical kernel, and separates a super user mode and a common user mode from the virtualized kernels respectively. In general, the resources in each mode cannot access the resources in the other modes, so that the security of the system is guaranteed on hardware. When the processor needs to access the resources in other modes from the high-credibility mode, the processor needs to access the resources in other modes after the processor is saved to the field switching mode in the current mode and is switched to the other modes.
In the process of implementing the invention, the inventor finds that at least the following technical problems exist in the prior art: the processor reads resources in other modes in a mode of continuously switching the modes, the working efficiency is low, and the power consumption of the processor is large.
Disclosure of Invention
The processor comprising the mapping access interface can improve the working efficiency of the processor and reduce the power consumption of the processor.
In a first aspect, the present invention provides a processor including a map access interface, comprising:
an instruction execution unit, a first mode resource storage unit, a second mode resource storage unit, and a mapping access interface, wherein,
the instruction execution unit is connected with the first mode resource storage unit, the second mode resource storage unit and the mapping access interface and is used for reading resource information of the mapping access interface or rewriting the resource information of the mapping access interface according to a received external instruction;
a first mode resource storage unit for storing resource information of the processor in a first mode, and the instruction execution unit has access to the resource of the first mode resource storage unit only when the processor is in the first mode;
a second mode resource storage unit for storing resource information of the processor in a second mode, and the instruction execution unit has access to the resource of the second mode resource storage unit only when the processor is in the second mode;
and the mapping access interface is connected with the second mode resource storage unit and used for reading the resource of the second mode resource storage unit in real time and storing the resource as the resource information of the mapping access interface, and when the processor is in the first mode, the mapping access interface returns the resource information according to the request of the instruction execution unit for reading the resource information, rewrites the resource information according to the request of the instruction execution unit for rewriting the resource information, and sends the rewritten resource information to a resource register in the second mode resource storage unit.
Optionally, the first mode resource storage unit is a trusted super user mode resource storage unit, and the second mode resource storage unit is a trusted normal user mode resource storage unit.
Optionally, the first mode resource storage unit is a trusted super user mode resource storage unit, and the second mode resource storage unit is an untrusted super user mode resource storage unit.
Optionally, the first mode resource storage unit is a trusted super user mode resource storage unit, and the second mode resource storage unit is an untrusted ordinary user mode resource storage unit.
Optionally, the first mode resource storage unit is an untrusted super user mode resource storage unit, and the second mode resource storage unit is an untrusted ordinary user mode resource storage unit.
Optionally, the resource register is an exception base register, an exception backup register, or a stack register.
Optionally, the mapping access interface is at least one control register or at least one memory address.
According to the processor comprising the mapping access interface provided by the embodiment of the invention, the instruction execution unit is in the user mode with high authority, and the resource in the user mode with low authority can be directly accessed through the mapping access interface without switching the mode of the processor, so that the working efficiency of the processor can be improved, and the power consumption of the processor can be reduced.
Drawings
FIG. 1 is a block diagram of a processor including a map access interface according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating mode switching of a processor program status register according to an embodiment of the present invention;
FIG. 3 is a diagram of a processor including a map access interface according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating an embodiment of the present invention in which a high level privilege mode accesses a low level privilege mode dedicated resource.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a processor comprising a mapping access interface, as shown in fig. 1, the processor comprising:
an instruction execution unit 11, a first pattern resource storage unit 12, a second pattern resource storage unit 13, and a mapping access interface 14, wherein,
the instruction execution unit 11 is connected to the first mode resource storage unit 12, the second mode resource storage unit 13, and the mapping access interface 14, and configured to read resource information of the mapping access interface 14 or rewrite resource information of the mapping access interface 14 according to a received external instruction;
a first mode resource storage unit 12, configured to store resource information of the processor in a first mode, and the instruction execution unit 11 has access to the resource of the first mode resource storage unit 12 only when the processor is in the first mode;
a second mode resource storage unit 13, configured to store resource information of the processor in the second mode, and the instruction execution unit 11 has access to the resource of the second mode resource storage unit 13 only when the processor is in the second mode;
and the mapping access interface 14 is connected to the second mode resource storage unit 13, and is configured to read and store the resource of the second mode resource storage unit 13 in real time, and rewrite the resource of the resource register in the second mode resource storage unit 13 according to the rewrite information sent by the instruction execution unit 11 when the processor is in the first mode.
According to the processor comprising the mapping access interface provided by the embodiment of the invention, the instruction execution unit is in the user mode with high authority, and the resource in the user mode with low authority can be directly accessed through the mapping access interface without switching the mode of the processor, so that the working efficiency of the processor can be improved, and the power consumption of the processor can be reduced.
Optionally, as shown in fig. 2, a schematic diagram of mode switching of a processor program status register is shown; the processor is provided with a trusted kernel and an untrusted kernel which are logically independent, and the trusted kernel is divided into a trusted super user mode and a trusted common user mode according to two standards of a programming mode; and dividing the untrusted kernel into an untrusted super user mode and an untrusted ordinary user mode. When the SE bit of the program state register is 1, the processor is indicated to be currently under a trusted kernel, at the moment, the processor adopts a trusted program state register (SEPSR) as the program state register, when the S bit of the trusted program state register is 1, the processor is indicated to be currently under a trusted super user mode, and when the S bit of the trusted program state register is 0, the processor is indicated to be currently under a trusted common user mode; when the SE bit of the program status register is 0, it indicates that the processor is currently in the untrusted kernel, and at this time, the processor uses an untrusted program status register (NSPSR) as the program status register, and when the S bit of the untrusted program status register is 1, it indicates that the processor is currently in the untrusted supervisor mode, and when the S bit of the untrusted program status register is 0, it indicates that the processor is currently in the untrusted normal user mode.
Alternatively, as shown in FIG. 3, four modes of the processor: the trusted super user mode, the trusted common user mode, the untrusted super user mode and the untrusted common user mode have different authorities, wherein the trusted super user mode has the highest authority and can access resources in the trusted common user mode, the untrusted super user mode and the untrusted common user mode through the mapping access interface; the authority of the non-trusted super user mode is higher than that of the non-trusted common user mode, and resources in the non-trusted common user mode can be accessed through the mapping access interface; the trusted common user mode can only access the resources in the trusted common user mode, and does not have the authority to access the resources in other modes; the non-trusted common user mode can only access the resources in the non-trusted user mode, and does not have the authority to access the resources in other modes.
Optionally, when the processor operates in the trusted super-user mode and has a need to read the stack register of the trusted normal user mode, after the instruction execution unit of the processor acquires and identifies the instruction, the instruction execution unit of the processor directly acquires a mapping resource through the mapping access interface, where the mapping resource is a resource of the stack register of the trusted normal user mode, and the mapping access interface stores the resource of the stack register of the trusted normal user mode in its own control register in real time, so as to achieve the purpose of reading the stack register of the trusted normal user in the trusted super-user mode.
Optionally, when the processor operates in the trusted super-user mode and has a need to read the stack register of the untrusted normal user mode, after the instruction execution unit of the processor obtains and identifies the instruction, the instruction execution unit directly obtains a mapping resource through the mapping access interface, where the mapping resource is a resource of the stack register of the untrusted normal user mode, and the mapping access interface stores the resource of the stack register of the untrusted normal user mode in its own control register in real time, so as to achieve a purpose of reading the stack register of the untrusted normal user mode in the trusted super-user mode.
Optionally, when the processor operates in the trusted super-user mode and has a need to read the stack register of the untrusted super-user mode, after the instruction execution unit of the processor acquires and identifies the instruction, the instruction execution unit of the processor directly acquires a mapping resource through the mapping access interface, where the mapping resource is a resource of the stack register of the untrusted super-user mode, and the mapping access interface stores the resource of the stack register of the untrusted super-user mode in its own control register in real time, so as to achieve the purpose of reading the stack register of the untrusted super-user mode in the trusted super-user mode.
Optionally, when the processor runs in the untrusted super user mode in the untrusted kernel and has a need to read the stack register of the untrusted normal user mode in the untrusted kernel, the instruction execution unit of the processor obtains and identifies the instruction, and then directly obtains the mapping resource through the mapping access interface, where the mapping resource is a resource of the stack register of the untrusted normal user mode, and the mapping access interface stores the resource of the stack register of the untrusted normal user mode in its own control register in real time, so as to achieve the purpose of reading the stack register of the untrusted super user in the trusted super user mode.
Optionally, when the processor operates in the trusted super user mode or the untrusted super user mode and there is a need to rewrite the untrusted ordinary user stack register, the instruction execution unit sends the write address and the write data to the mapping access interface, and the mapping access interface rewrites the content in the control register and then sends the rewritten content to the untrusted ordinary user stack register. Thereby enabling the processor to achieve the goal of rewriting resources.
Optionally, when the processor operates in the trusted super user mode and there is a need to rewrite the untrusted super user stack register, the instruction execution unit sends a write address and write data to the mapping access interface, and the mapping access interface rewrites contents in the control register and then sends the rewritten contents to the untrusted super user stack register. Thereby enabling the processor to achieve the goal of rewriting resources.
Optionally, when the processor operates in the trusted supervisor mode and there is a need to rewrite the trusted normal user stack register, the instruction execution unit sends a write address and write data to the mapping access interface, and the mapping access interface rewrites contents in the control register and then sends the rewritten contents to the trusted normal user stack register. Thereby enabling the processor to achieve the goal of rewriting resources.
Optionally, the stack register may also be an exception base register, an exception backup register, or a stack register.
Optionally, the first mode resource storage unit is a trusted super user mode resource storage unit, and the second mode resource storage unit is a trusted normal user mode resource storage unit.
Optionally, the first mode resource storage unit is a trusted super user mode resource storage unit, and the second mode resource storage unit is an untrusted super user mode resource storage unit.
Optionally, the first mode resource storage unit is a trusted super user mode resource storage unit, and the second mode resource storage unit is an untrusted ordinary user mode resource storage unit.
Optionally, the first mode resource storage unit is an untrusted super user mode resource storage unit, and the second mode resource storage unit is an untrusted ordinary user mode resource storage unit.
Optionally, the resource register is an exception base register, an exception backup register, or a stack register, but is not limited thereto.
Specifically, the trusted kernel and the untrusted kernel have independent exception service mechanisms, the SEVBR is an exception base register special for the trusted kernel, and all entry addresses are stored in an exception vector table with the SEVBR as a base address; the NSVBR is an abnormal entry mechanism register special for the untrusted kernel, and all entry addresses are stored in an abnormal vector table with the NSVBR as a base address. When the processor runs in the trusted supervisor mode, the exception entry base register of the untrusted kernel can be accessed by accessing the mapping access interface in the trusted supervisor mode.
Specifically, the SEEPSR is an abnormal state reservation register dedicated to the trusted kernel, and is used for storing PSR information of the trusted kernel when the processor is in a safety interruption or safety abnormality, so as to facilitate the field recovery of the processor; NSEPSR is an abnormal state reserved register special for the non-trusted kernel, and when the processor is subjected to non-secure interruption or non-secure abnormality, PSR information of the operation of the non-trusted kernel is stored so as to facilitate the field recovery of the processor. When the processor runs in the trusted supervisor mode, the exception reservation state register of the non-trusted kernel can be accessed by accessing the mapping access interface in the trusted supervisor mode.
Specifically, the seppc is an exception retention program counter dedicated to the trusted kernel, and when the CPU is in an exception state or a security interrupt state in the trusted kernel, the CPU stores information in the trusted kernel into the seppc for field recovery of the CPU; the NSEPC is an abnormal reserved program counter special for the untrusted kernel, and when the CPU generates abnormality or safety interruption in the untrusted kernel, the CPU stores information under the untrusted kernel into the SEEPC for field recovery of the CPU; when the processor runs in the trusted supervisor mode, the exception-preserving program counter of the non-trusted kernel can be accessed by accessing the mapping access interface in the trusted supervisor mode.
Optionally, the mapping access interface is at least one control register or at least one memory address.
Alternatively, as shown in FIG. 4, a diagram of accessing low level privilege mode specific resources for a high level privilege mode;
when the processor is in the first user mode and needs to read the second user mode resource, the special resource is stored in the general register through the mapping access interface, and the special resource stored in the general register is processed by the instruction execution unit.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (7)
1. A processor including a map access interface, comprising: an instruction execution unit, a first mode resource storage unit, a second mode resource storage unit, and a mapping access interface, wherein,
the instruction execution unit is connected with the first mode resource storage unit, the second mode resource storage unit and the mapping access interface and is used for reading resource information of the mapping access interface or rewriting the resource information of the mapping access interface according to a received external instruction;
a first mode resource storage unit for storing resource information of the processor in a first mode, and the instruction execution unit has access to the resource of the first mode resource storage unit only when the processor is in the first mode;
a second mode resource storage unit for storing resource information of the processor in a second mode, and the instruction execution unit has access to the resource of the second mode resource storage unit only when the processor is in the second mode;
and the mapping access interface is connected with the second mode resource storage unit and used for reading the resource of the second mode resource storage unit in real time and storing the resource as the resource information of the mapping access interface, and when the processor is in the first mode, the mapping access interface returns the resource information according to the request of the instruction execution unit for reading the resource information, rewrites the resource information according to the request of the instruction execution unit for rewriting the resource information, and sends the rewritten resource information to a resource register in the second mode resource storage unit.
2. The processor of claim 1, wherein the first mode resource store is a trusted supervisor mode resource store, and wherein the second mode resource store is a trusted normal user mode resource store.
3. The processor of claim 1, wherein the first mode resource store is a trusted supervisor mode resource store, and wherein the second mode resource store is an untrusted supervisor mode resource store.
4. The processor of claim 1, wherein the first mode resource store is a trusted supervisor mode resource store, and wherein the second mode resource store is an untrusted normal user mode resource store.
5. The processor of claim 1, wherein the first mode resource store is an untrusted supervisor mode resource store, and wherein the second mode resource store is an untrusted normal user mode resource store.
6. The processor of claim 1, wherein the resource register is an exception base register, an exception backup register, or a stack register.
7. The processor of claim 1, wherein the map access interface comprises at least one control register or at least one memory address for storing the resource information.
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| CN105356998A (en) * | 2015-09-28 | 2016-02-24 | 宇龙计算机通信科技(深圳)有限公司 | TrustZone-based domain space switching system and method |
| CN106156044A (en) * | 2015-03-26 | 2016-11-23 | 阿里巴巴集团控股有限公司 | Data base's changing method and device |
| CN106156618A (en) * | 2015-04-17 | 2016-11-23 | 国民技术股份有限公司 | A kind of safety chip, mobile terminal and the method realizing mobile terminal system safety |
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Patent Citations (4)
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| CN102859530A (en) * | 2010-06-03 | 2013-01-02 | 株式会社东芝 | Access control device and recording medium |
| CN106156044A (en) * | 2015-03-26 | 2016-11-23 | 阿里巴巴集团控股有限公司 | Data base's changing method and device |
| CN106156618A (en) * | 2015-04-17 | 2016-11-23 | 国民技术股份有限公司 | A kind of safety chip, mobile terminal and the method realizing mobile terminal system safety |
| CN105356998A (en) * | 2015-09-28 | 2016-02-24 | 宇龙计算机通信科技(深圳)有限公司 | TrustZone-based domain space switching system and method |
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