CN107102966B - Multi-core processor chip, interrupt control method and controller - Google Patents
Multi-core processor chip, interrupt control method and controller Download PDFInfo
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- CN107102966B CN107102966B CN201610096697.6A CN201610096697A CN107102966B CN 107102966 B CN107102966 B CN 107102966B CN 201610096697 A CN201610096697 A CN 201610096697A CN 107102966 B CN107102966 B CN 107102966B
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Abstract
The embodiment of the invention provides a multi-core processor chip, an interrupt control method and a controller. The interrupt control method is applied to a processor comprising at least two processor cores, and comprises the following steps: determining a target interrupt mode matched with the first interrupt request according to the interrupt type of the received first interrupt request; obtaining a historical distribution result of a second interrupt request which has occurred and is the same as the interrupt type of the first interrupt request; and determining a processor core which is allocated to the first interrupt request in the at least two processor cores according to the target interrupt mode and the historical allocation result. The embodiment can improve the efficiency of the multi-core processor system for processing the interrupt request.
Description
Technical Field
The embodiment of the invention relates to the field of computers, in particular to a multi-core processor chip, an interrupt control method and a controller.
Background
The multi-core system is a system integrating a plurality of processor cores on one computer, wherein the processor cores share a system bus, most hardware in the computer is shared, and the system bus and the shared hardware cooperate with each other to complete designated work.
In a multi-core system, in order to execute an interrupt service program, an interrupt request is generally required to be sent to any one of a plurality of processor cores, when a processor core executing a main program receives the interrupt request, the processor core interrupts the executed main program, executes the interrupt service program corresponding to the interrupt request, and returns to execute the terminated main program after the interrupt service program is executed. In the current multi-core processor system, a static allocation mechanism is mostly adopted, each interrupt request is fixedly processed by one processor core under the mechanism, and the mechanism can ensure that the interrupt requests are processed orderly.
However, when interrupt requests allocated to the same processor core frequently occur, the interrupt processing delay is too long, and the efficiency of the whole multi-core system for processing the interrupt requests is affected.
Disclosure of Invention
The embodiment of the invention provides a multi-core processor chip, an interrupt control method and a controller, which are used for improving the efficiency of a multi-core processor system for processing interrupt requests.
In a first aspect, the present invention provides an interrupt control method applied to a processor including at least two processor cores, the method including:
determining a target interrupt mode matched with the first interrupt request according to the interrupt type of the received first interrupt request;
obtaining a historical distribution result of a second interrupt request which has occurred and is the same as the interrupt type of the first interrupt request;
and determining a processor core which is allocated to the first interrupt request in the at least two processor cores according to the target interrupt mode and the historical allocation result.
In a second aspect, the present invention provides a controller comprising:
the interrupt request configuration module is used for determining a target interrupt mode matched with the first interrupt request according to the interrupt type of the received first interrupt request;
the interrupt request history recording module is used for acquiring a history distribution result of a second interrupt request which has occurred and is the same as the interrupt type of the first interrupt request;
and the interrupt request arbitration module is used for determining the processor core allocated to the first interrupt request in the at least two processor cores according to the target interrupt mode and the historical allocation result.
In a third aspect, the present invention provides a multicore processor chip comprising: a controller as described above.
According to the multi-core processor chip, the interrupt control method and the controller provided by the embodiment, the target interrupt mode matched with the first interrupt request is determined according to the interrupt type of the received first interrupt request; acquiring a historical distribution result of a second interrupt request which has occurred and is the same as the interrupt type of the first interrupt request; and determining a processor core allocated to the first interrupt request from the at least two processor cores according to the target interrupt mode and the historical allocation result. The embodiment first determines a target interrupt mode matched with the first interrupt request, so that the requirements of interrupt delay and/or interrupt frequency of the first interrupt request can be met, determines the processor cores allocated to the first interrupt request through the target interrupt mode, can balance the processing of checking the interrupt request by each processor, and can simplify the time sequence and logic processing overhead of hardware by combining a mode of allocating the processor cores to the interrupt request according to a historical allocation result, thereby improving the efficiency of the multi-core system for processing the interrupt request.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic diagram of an application scenario of the interrupt control method according to the present invention;
FIG. 2 is a flowchart of a first embodiment of an interrupt control method according to the present invention;
FIG. 3 is a flowchart of a second embodiment of an interrupt control method according to the present invention;
FIG. 4 is a flowchart of a third embodiment of an interrupt control method according to the present invention;
FIG. 5 is a flowchart of a fourth embodiment of an interrupt control method according to the present invention;
fig. 6 is a schematic diagram of a first embodiment of the controller according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The interrupt control method provided by the embodiment of the invention can flexibly adopt various interrupt modes according to the application environment of the computer system and the requirements of the interrupt request source corresponding to each interrupt request, and sends the interrupt request to the processor core by combining the historical distribution result. For interrupt sources with low interrupt processing delay requirements, a static routing distribution mode can be adopted, so that the software processing overhead can be saved; interrupt sources with certain requirements on interrupt processing time delay adopt a fixed interrupt balanced distribution mode; when the interrupt source has high requirement on the interrupt processing efficiency, an interrupt balanced distribution busy mode or an interrupt balanced distribution idle mode is adopted, so that the processing of interrupt requests by all processors is balanced, and meanwhile, the time sequence and logic processing overhead of hardware can be simplified by combining a mode of distributing processor cores for the interrupt requests according to historical distribution results.
Fig. 1 is a schematic view of an application scenario of the interrupt control method according to the present invention. The interrupt control method of the embodiment is applicable to a multi-core processor, namely, a processor including at least two processor cores. The interrupt control method of the present embodiment may be executed by a controller, and specifically, the controller may be an interrupt controller. As shown in fig. 1, the computer system includes a plurality of processor cores, which are CPU0 and CPU1 … … CPUn in sequence. The interrupt source capable of sending the interrupt request in this embodiment may be an I/O device, a fault source, a software-set interrupt source, and the like, and the embodiment is not particularly limited in this respect as to the implementation form of the interrupt source. When receiving an interrupt request sent by an interrupt source, the interrupt controller allocates a processor core for the interrupt request. For example, when interrupt controller receives interrupt request 0, processor core CUP1 is allocated for interrupt request 0.
The following describes the interrupt control method provided by the present invention in detail by using a specific embodiment.
Fig. 2 is a flowchart of a first embodiment of the interrupt control method according to the present invention, where an execution main body of the present embodiment is the controller shown in fig. 1, and the controller is implemented by software and hardware. As shown in fig. 2, the method of this embodiment may include:
Specifically, when the controller receives a first interrupt request sent by an interrupt source, a target interrupt mode matched with the first interrupt request is determined according to the requirement of the interrupt type of the first interrupt request on the interrupt delay or the interrupt frequency. The target interrupt mode is specifically one or more of the following: a static route distribution mode, a fixed interrupt balance distribution mode, an interrupt balance distribution busy mode and an interrupt balance distribution idle mode. The requirement of the interrupt type on the interrupt delay or the interrupt frequency refers to whether the interrupt delay required under the interrupt type is strict, such as whether the interrupt delay requirement is large or small; or whether the frequency of interrupts generated is frequent, such as more or less frequent interrupts. Therefore, corresponding to the requirements on the interrupt time delay or the interrupt frequency of different interrupt types, the interrupt time delay of the interrupt request corresponding to each mode is reduced in sequence according to the arrangement sequence of each mode; and/or the interrupt frequency of the interrupt request corresponding to each mode is sequentially increased according to the arrangement sequence of the modes.
For example, the interrupt type of the first interrupt request is a graphics card interrupt request, and the interrupt frequency corresponding to the graphics card interrupt request is relatively frequent, so that the interrupt mode matched with the first interrupt request is determined to be an interrupt balance distribution busy mode or an interrupt balance distribution idle mode.
the first interrupt request and the second interrupt request are interrupt requests of the same interrupt type and occurring at different moments. In this embodiment, the second interrupt request occurs first, and then the first interrupt request occurs, for example, the interrupt request is a graphics card interrupt request, the second interrupt request occurs at 9:32, and the first interrupt request occurs at 9: 40. And after receiving the first interrupt request, obtaining a historical distribution result, wherein the historical distribution result records a processor core distribution result distributed to a second interrupt request belonging to the interrupt type.
And combining the historical allocation result and the target interrupt mode to allocate the processor core to the first interrupt request. For example, according to the historical allocation result, the processor core allocated to the second interrupt request is determined to be the first processor core, then whether the first processor core is in an idle state or not is judged, if yes, the first processor core is allocated to the first interrupt request, and if not, the second processor core is allocated to the first interrupt request.
Further, after step 203, the controller also updates the historical allocation result of the interrupt type to which it (i.e., the first interrupt request) belongs with the processor core allocation result of the first interrupt request. That is, only the processor core allocation result of the first interrupt request belonging to the interrupt type is recorded in the updated historical allocation result, and the processor core allocation result of the second interrupt request belonging to the interrupt type is deleted.
In the interrupt control method provided in this embodiment, a target interrupt mode matching a first interrupt request is determined according to an interrupt type of the received first interrupt request; acquiring a historical distribution result of a second interrupt request which has occurred and is the same as the interrupt type of the first interrupt request; and determining a processor core allocated to the first interrupt request from the at least two processor cores according to the target interrupt mode and the historical allocation result. The embodiment first determines a target interrupt mode matched with the first interrupt request, so that the requirements of interrupt delay and/or interrupt frequency of the first interrupt request can be met, determines the processor cores allocated to the first interrupt request through the target interrupt mode, can balance the processing of checking the interrupt request by each processor, and can simplify the time sequence and logic processing overhead of hardware by combining a mode of allocating the processor cores to the interrupt request according to a historical allocation result, thereby improving the efficiency of the multi-core system for processing the interrupt request.
Step 203 in fig. 2 is described in detail below with reference to fig. 3 to 5 by using a specific embodiment, in which at least two processor cores are available for processing an interrupt request.
In the embodiments described below, when referring to the vector numbers of the processor cores, the vector numbers are sorted in ascending or descending order, the second vector number is sorted after the first vector number, and if the first vector number is the last vector number sorted, the second vector number is the first vector number sorted; or the vector numbers are sorted in ascending or descending order, the second vector number is sorted before the first vector number, and if the first vector number is the vector number sorted first, the second vector number is the vector number sorted last.
Fixed interrupt balanced distribution mode
FIG. 3 is a flowchart of a second embodiment of an interrupt control method according to the present invention. As shown in fig. 3, the method includes:
step 301, determining a processor core allocated to the second interrupt request as a first processor core according to a historical allocation result;
In this embodiment, when a first interrupt request enters the interrupt controller, the interrupt controller allocates, to the first interrupt request, a second processor core that satisfies a preset condition, excluding the first processor core, according to the processor core available for processing the interrupt request and the first processor core that processed the interrupt request (second interrupt request) last time.
The second processor core meeting the preset condition may be any processor core except the first processor core, or the processor cores may be numbered, and then the first interrupt request is routed to the next processor core according to the number.
Optionally, each processor core corresponds to a vector number, and when a second processor core meeting a preset condition is determined, a second vector number meeting a preset ordering relation with the first vector number can be determined according to the first vector number of the first processor core; in a processor core configured to process interrupt requests, a second processor core corresponding to a second vector number is determined to be allocated to a first interrupt request.
For example, in a four-core processor, the interrupt pattern matched by interrupt request 1 is a fixed interrupt balanced distribution pattern, and the vector numbers of the processor cores for processing the interrupt requests are 0, 1 and 3. Then, when the interrupt request 1 enters the interrupt controller for the first time, the interrupt controller allocates the processor core 0 for the interrupt request 1 and sends the interrupt request 1 to the processor core 0 for processing, when the interrupt request 1 enters the interrupt controller for the second time, the interrupt controller allocates the processor core 1 for the interrupt request 1 and sends the interrupt request 1 to the processor core 1 for processing, when the interrupt request 1 enters the interrupt controller for the third time, the interrupt controller allocates the processor core 3 for the interrupt request 1 and sends the interrupt request 1 to the processor core 3 for processing, when the interrupt request 1 is sent to the processor core 0 for processing for the fourth time, and so on, this embodiment is not described herein again.
It can be understood by those skilled in the art that if the interrupt request 1 enters the interrupt controller for the second time is the current time, the interrupt request 1 enters the interrupt controller for the first time is the historical time, that is, the interrupt request 1 entering the interrupt controller for the first time is equivalent to the second interrupt request, the interrupt request 1 entering the interrupt controller for the second time is equivalent to the first interrupt request, and so on, which is not described herein again.
In this embodiment, when the interrupt request has a certain requirement on the time delay and/or the interrupt frequency is relatively low, the interrupt requests of the same interrupt type are sequentially allocated to different processor cores to be processed, so that the processing of the interrupt requests checked by each processor can be balanced.
Interrupt balanced distribution busy mode
Fig. 4 is a flowchart of a third embodiment of the interrupt control method of the present invention. As shown in fig. 4, the method includes:
step 401, determining that the processor core allocated to the second interrupt request is the first processor core according to the historical allocation result;
In this embodiment, after the first interrupt request enters the controller, the controller determines, according to the historical allocation result, the processor core allocated to the interrupt request (the second interrupt request) last time as the first processor core; and then judging whether a first processor core allocated by the last interrupt request (second interrupt request) is busy or not according to the historical state record of the first processor core, if the first processor core corresponding to the second interrupt request has an incomplete interrupt request (currently busy), sending the first interrupt request to the second processor core meeting the preset condition, and if the first processor core corresponding to the second interrupt request does not have an incomplete interrupt request, sending the first interrupt request to the first processor core.
Optionally, each processor core corresponds to a vector number, an incomplete interrupt request exists on the first processor core, and when a second processor core meeting a preset condition is determined, a second vector number meeting a preset ordering relation with the first vector number can be determined according to the first vector number of the first processor core; in a processor core configured to process interrupt requests, a second processor core corresponding to a second vector number is determined to be allocated to a first interrupt request.
For example, in a four-core processor system, interrupt request 0 configures processor cores available for processing interrupt requests to be 0, 1 and 3, then for the first time interrupt request 0 enters the controller, it is first required to detect whether there is an outstanding interrupt request on processor core 0 at this time, if there is an outstanding interrupt request, then the interrupt request 0 will be allocated to processor core 1 (regardless of whether processor core 1 is busy at this time), if there is no outstanding interrupt request, then processor core 0 will process interrupt request 0. And the nth time interrupt request 0 entering the controller, assuming that the historical processor core is processor core 3, then if processor core 3 is busy at this time, the interrupt request 0 is processed by processor core 0 (regardless of whether processor core 0 is busy at this time), and if processor core 3 is idle at this time, the interrupt request is processed by processor core 3.
In this embodiment, when the requirement of the interrupt request on the time delay is high and/or the interrupt frequency is relatively high, for the interrupt request of the same interrupt type, the interrupt request is preferentially allocated to the idle historical processor core, and when the historical processor core is in a busy state, the interrupt request is allocated to the other processor cores for processing, so that not only can the time sequence and logic processing overhead of hardware be simplified, but also the processing of the interrupt request checked by each processor can be balanced.
Interrupt balanced distribution idle mode
Fig. 5 is a flowchart of a fourth embodiment of the interrupt control method according to the present invention. As shown in fig. 5, the method includes:
step 501, determining a processor core allocated to the second interrupt request as a first processor core according to a historical allocation result;
step 506, if not, determines to allocate the first processor core to the first interrupt request.
In this embodiment, when a first interrupt request enters the controller, the controller determines, according to a historical allocation result, that a processor core allocated to the interrupt request (a second interrupt request) last time is a first processor core; then, according to the history state record of the first processor core, the controller judges whether the first processor core allocated by the last interrupt request (second interrupt request) is busy or not, and if the first processor core corresponding to the second interrupt request does not have an incomplete interrupt request, the controller sends the first interrupt request to the first processor core. If the first processor core corresponding to the second interrupt request has an uncompleted interrupt request (currently busy), detecting whether the next processor core available for processing the interrupt request has an uncompleted interrupt request, if not, interrupting the processor core, and allocating the processor core to the first interrupt request; if there are outstanding interrupt requests, the next processor core available to process the interrupt request continues to be detected. And so on, until all processor cores available for processing the interrupt request are checked, if there is still no idle processor core, the interrupt request will be processed on the historical processor core, regardless of whether there is an unprocessed interrupt request in the processor core.
Optionally, each processor core corresponds to a vector number, and when traversing all the processor cores except the first processor core, all the processor cores except the first processor core may be traversed according to the preset sorting order of the vector numbers.
For example: in a four-core processor system, the processor cores which are configured by an interrupt request 0 and can be used for processing the interrupt request are 0, 1 and 3, when the interrupt request 0 enters a controller for the first time, whether the processor core 0 has an incomplete interrupt request is detected, if not (idle) the processor core 0 processes the interrupt request, otherwise, whether the processor core 1 is idle is detected, if the processor core 1 is idle, the processor core 1 processes the interrupt request, otherwise, the processor core 3 is idle, if the processor core 3 is idle, the processor core 3 processes the interrupt request, if the processor core 3 is busy at the moment, namely, all routable processor cores configured by the interrupt request 0 are not in an idle state, and the processor core 0 processes the interrupt request 0. And for the interrupt request 0 entering the controller for the nth time, assuming that the historical processor core is the processor core 3, if the processor core 3 is idle, the processor core 3 is used for processing, otherwise, whether the processor core 0 is idle is detected, if the processor core 0 is idle, the processor core 0 is used for processing the interrupt request 0, if the processor core 0 is busy, the state of the processor core 1 is continuously detected, if the processor core 1 is idle, the interrupt request 0 is processed, otherwise, the historical processor core 3 is used for processing the interrupt request.
In this embodiment, when the requirement of the interrupt request on the time delay is high and/or the interrupt frequency is relatively high, for the interrupt request of the same interrupt type, the interrupt request is preferentially allocated to the idle historical processor core, and when the historical processor core is in a busy state, the interrupt request is allocated to the idle processor core for processing, so that not only can the time sequence and logic processing overhead of hardware be simplified, but also the processing of the interrupt request checked by each processor can be balanced.
Further, as can be understood by those skilled in the art, in the interrupt balance distribution busy mode and the interrupt balance distribution idle mode described above, the present embodiment also performs the operation of updating the history status record. The method comprises the following specific steps:
after the first processing core or the second processing core is allocated to any interrupt request, the historical state record of the first processor core or the second processor core of the controller is updated by using the busy state of the first processor core or the second processor core of the controller (namely, the controller records the busy state information of the second processor core on the historical state record of the first processor core or the second processor core, so as to update the historical state record);
after the first processor core of the controller or the second processor core of the controller completes processing of an interrupt event corresponding to any interrupt request, receiving an interrupt event processing completion notification message sent by the first processor core of the controller or the second processor core of the controller, and updating the history state record of the first processor core of the controller or the second processor core of the controller by using the idle state of the first processor core of the controller or the second processor core of the controller (namely, the controller records the idle state information of the second processor core to the history state record of the first processor core or the second processor core, so as to realize continuous updating of the history state record).
That is, in this embodiment, the controller further records the state of each processor core, and when the processor core is in a busy state, it indicates that the processor core is processing an interrupt event corresponding to an interrupt request, and when the processor core is in an idle state, it indicates that the processor core is not currently processing any interrupt event corresponding to an interrupt request. The controller can acquire the state of each processor core according to the historical state record of each processor core, and excessive signaling interaction with the processor cores is not needed, so that the communication between the controller and each processor core is reduced, the information feedback timeliness is stronger, and the interrupt processing efficiency of the whole multi-core system is more favorably improved.
Static route allocation pattern
When all interrupt balancing modes are not enabled, the target interrupt mode matched with the first interrupt request is a static route allocation mode. There is only one and only one processor core that can handle the interrupt request at this time. And when the processor core allocated to the second interrupt request is determined to be the first processor core according to the historical allocation result, directly allocating the first processor core to the first interrupt request.
Fig. 6 is a schematic diagram of a first structural embodiment of the controller of the present invention, as shown in fig. 6, the controller includes:
an interrupt request configuration module 601, configured to determine, according to the interrupt type of the received first interrupt request, a target interrupt mode matched with the first interrupt request;
an interrupt request history module 602, configured to obtain a history allocation result of an occurred second interrupt request that is the same as the interrupt type of the first interrupt request;
an interrupt request arbitration module 603, configured to determine, according to the target interrupt mode and the historical allocation result, a processor core allocated to the first interrupt request from among the at least two processor cores.
Optionally, the interrupt request configuration module 601 is specifically configured to:
receiving the first interrupt request, and determining a target interrupt mode matched with the first interrupt request according to the requirement of the interrupt type of the first interrupt request on interrupt delay or interrupt frequency;
wherein the target interrupt mode is specifically one of the following:
a static route distribution mode, a fixed interrupt balance distribution mode, an interrupt balance distribution busy mode and an interrupt balance distribution idle mode.
Optionally, the interruption request arbitration module 603 is specifically configured to at least one of:
the target interrupt mode matched with the first interrupt request is a fixed interrupt balanced distribution mode, and at least two processor cores configured for processing interrupt requests are provided; the interrupt request arbitration module is specifically configured to determine, according to the historical allocation result, that the processor core allocated to the second interrupt request is the first processor core; determining to distribute a second processor core, which is except the first processor core and meets a preset condition, to the first interrupt request in the processor cores configured for processing the interrupt request;
the target interrupt mode matched with the first interrupt request is an interrupt balanced distribution busy mode, and at least two processor cores are configured for processing interrupt requests; the interrupt request arbitration module is specifically configured to determine, according to the historical allocation result, that the processor core allocated to the second interrupt request is the first processor core; judging whether the first processor core is in a busy state or not according to the historical state record of the first processor core; if not, determining to distribute the first processor core to the first interrupt request; if yes, determining to distribute a second processor core which is except the first processor core and meets a preset condition to the first interrupt request in configured processor cores for processing the interrupt request;
the target interrupt mode matched with the first interrupt request is an interrupt balanced distribution idle mode, and at least two configured processor cores for processing the interrupt request are provided; the interrupt request arbitration module is specifically configured to determine, according to the historical allocation result, that the processor core allocated to the second interrupt request is the first processor core; judging whether the first processor core is in a busy state or not according to the historical state record of the first processor core; if not, determining to distribute the first processor core to the first interrupt request; if so, traversing all the processor cores except the first processor core in the configured processor cores for processing the interrupt request according to the historical state records of the processor cores, if the second processor core is in an idle state, determining to distribute the second processor core to the first interrupt request, and if the second processor core is not in the idle state, determining to distribute the first processor core to the first interrupt request.
Optionally, each processor core corresponds to a vector number; the interrupt request arbitration module 603 is further specifically configured to,
according to the historical state records of the processor cores, traversing all the processor cores except the first processor core in the configured processor cores for processing the interrupt request according to the preset sorting sequence of the vector numbers.
Optionally, the interrupt request history module 602 is further configured to,
updating the historical allocation result of the interrupt type to which the first interrupt request belongs by using the allocation result of the processor core of the first interrupt request; and/or.
The interrupt request history module 602 is further configured to:
updating a historical state record of the first processor core or the second processor core with a busy state of the first processor core or the second processor core; after the first processor core or the second processor core finishes processing the interrupt event, receiving an interrupt event processing completion notification message sent by the first processor core or the second processor core, and updating the historical state record of the first processor core or the second processor core by using the idle state of the first processor core or the second processor core.
The controller provided in this embodiment may be used to implement the embodiment of the interrupt control method, which has similar implementation principle and technical effect, and this embodiment is not described herein again.
The embodiment also provides a multi-core processor chip comprising the controller.
Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (13)
1. An interrupt control method applied to a processor including at least two processor cores, the method comprising:
determining a target interrupt mode matched with a first interrupt request according to the interrupt type of the received first interrupt request;
obtaining a historical distribution result of a second interrupt request which has occurred and is the same as the interrupt type of the first interrupt request;
determining a processor core which is allocated to the first interrupt request in the at least two processor cores according to the target interrupt mode and the historical allocation result;
wherein the target interrupt mode is specifically one of the following:
a static routing distribution mode, a fixed interruption equilibrium distribution mode, an interruption equilibrium distribution busy mode and an interruption equilibrium distribution idle mode;
the target interrupt mode matched with the first interrupt request is an interrupt balanced distribution busy mode, and at least two processor cores are configured for processing interrupt requests;
the determining, among the at least two processor cores, a processor core to which the first interrupt request is allocated according to the target interrupt mode and the historical allocation result includes:
determining the processor core allocated to the second interrupt request as a first processor core according to the historical allocation result;
judging whether the first processor core is in a busy state or not according to the historical state record of the first processor core;
if not, determining to distribute the first processor core to the first interrupt request;
and if so, determining to distribute a second processor core, which is except the first processor core and meets a preset condition, to the first interrupt request in the configured processor cores for processing the interrupt request.
2. The method of claim 1, wherein determining a target interrupt pattern matching the first interrupt request according to the received interrupt type of the first interrupt request comprises:
and receiving the first interrupt request, and determining a target interrupt mode matched with the first interrupt request according to the requirement of the interrupt type of the first interrupt request on interrupt delay or interrupt frequency.
3. The method of claim 2, wherein the first interrupt request matches a target interrupt pattern that is a fixed interrupt equal distribution pattern, and wherein there are at least two processor cores configured to process interrupt requests;
the determining, among the at least two processor cores, a processor core to which the first interrupt request is allocated according to the target interrupt mode and the historical allocation result includes:
determining the processor core allocated to the second interrupt request as a first processor core according to the historical allocation result;
in the processor cores configured for processing the interrupt request, determining to distribute a second processor core, which is except the first processor core and meets a preset condition, to the first interrupt request.
4. A method as claimed in any one of claims 1 to 3, wherein each processor core corresponds to a vector number; the determining, among the processor cores configured to process an interrupt request, to allocate, to the first interrupt request, a second processor core, other than the first processor core, that satisfies a preset condition includes:
determining a second vector number meeting a preset ordering relation with the first vector number according to the first vector number of the first processor core;
determining, in the processor cores configured to process interrupt requests, that the first interrupt request is assigned to the second processor core corresponding to the second vector number.
5. The method of claim 2, wherein the first interrupt request matches a target interrupt pattern that is an interrupt balanced distribution idle pattern, and wherein there are at least two processor cores configured to process interrupt requests;
the determining, among the at least two processor cores, a processor core to which the first interrupt request is allocated according to the target interrupt mode and the historical allocation result includes:
determining the processor core allocated to the second interrupt request as a first processor core according to the historical allocation result;
judging whether the first processor core is in a busy state or not according to the historical state record of the first processor core;
if not, determining to distribute the first processor core to the first interrupt request;
if so, traversing all the processor cores except the first processor core in the configured processor cores for processing the interrupt request according to the historical state records of the processor cores, if the second processor core is in an idle state, determining to distribute the second processor core to the first interrupt request, and if the second processor core is not in the idle state, determining to distribute the first processor core to the first interrupt request.
6. The method of claim 5, wherein each processor core corresponds to a vector number; traversing, in a processor core configured to process an interrupt request, all processor cores except the first processor core according to the history of the processor cores, including:
according to the historical state records of the processor cores, traversing all the processor cores except the first processor core in the configured processor cores for processing the interrupt request according to the preset sorting sequence of the vector numbers.
7. The method of any one of claims 1, 2, 3, or 5, further comprising:
and updating the historical allocation result of the interrupt type to which the processor core allocation result of the first interrupt request belongs.
8. The method of claim 1 or 5, further comprising:
updating a historical state record of the first processor core or the second processor core with a busy state of the first processor core or the second processor core;
after the first processor core or the second processor core finishes processing the interrupt event, receiving an interrupt event processing completion notification message sent by the first processor core or the second processor core, and updating the historical state record of the first processor core or the second processor core by using the idle state of the first processor core or the second processor core.
9. A controller, comprising:
the interrupt request configuration module is used for determining a target interrupt mode matched with a first interrupt request according to the interrupt type of the received first interrupt request;
the interrupt request history recording module is used for acquiring a history distribution result of a second interrupt request which has occurred and is the same as the interrupt type of the first interrupt request;
an interrupt request arbitration module, configured to determine, according to the target interrupt mode and the historical allocation result, a processor core allocated to the first interrupt request from among the at least two processor cores;
wherein the target interrupt mode is specifically one of the following:
a static routing distribution mode, a fixed interruption equilibrium distribution mode, an interruption equilibrium distribution busy mode and an interruption equilibrium distribution idle mode;
the target interrupt mode matched with the first interrupt request is an interrupt balanced distribution busy mode, and at least two processor cores are configured for processing interrupt requests; the interrupt request arbitration module is specifically configured to determine, according to the historical allocation result, that the processor core allocated to the second interrupt request is the first processor core; judging whether the first processor core is in a busy state or not according to the historical state record of the first processor core; if not, determining to distribute the first processor core to the first interrupt request; and if so, determining to distribute a second processor core, which is except the first processor core and meets a preset condition, to the first interrupt request in the configured processor cores for processing the interrupt request.
10. The controller according to claim 9, wherein the interrupt request configuration module is specifically configured to:
and receiving the first interrupt request, and determining a target interrupt mode matched with the first interrupt request according to the requirement of the interrupt type of the first interrupt request on interrupt delay or interrupt frequency.
11. The controller of claim 10, wherein the interrupt request arbitration module is specifically configured to at least one of:
the target interrupt mode matched with the first interrupt request is a fixed interrupt balanced distribution mode, and at least two processor cores configured for processing interrupt requests are provided; the interrupt request arbitration module is specifically configured to determine, according to the historical allocation result, that the processor core allocated to the second interrupt request is the first processor core; determining to distribute a second processor core, which is except the first processor core and meets a preset condition, to the first interrupt request in the processor cores configured for processing the interrupt request;
the target interrupt mode matched with the first interrupt request is an interrupt balanced distribution idle mode, and at least two configured processor cores for processing the interrupt request are provided; the interrupt request arbitration module is specifically configured to determine, according to the historical allocation result, that the processor core allocated to the second interrupt request is the first processor core; judging whether the first processor core is in a busy state or not according to the historical state record of the first processor core; if not, determining to distribute the first processor core to the first interrupt request; if so, traversing all the processor cores except the first processor core in the configured processor cores for processing the interrupt request according to the historical state records of the processor cores, if the second processor core is in an idle state, determining to distribute the second processor core to the first interrupt request, and if the second processor core is not in the idle state, determining to distribute the first processor core to the first interrupt request.
12. The controller according to any one of claims 9 to 11,
the interrupt request history recording module is further used for updating the history distribution result of the interrupt type to which the first interrupt request belongs by using the distribution result of the processor core of the first interrupt request; and/or
The interrupt request history module is further configured to: updating a historical state record of the first processor core or the second processor core with a busy state of the first processor core or the second processor core; after the first processor core or the second processor core finishes processing the interrupt event, receiving an interrupt event processing completion notification message sent by the first processor core or the second processor core, and updating the historical state record of the first processor core or the second processor core by using the idle state of the first processor core or the second processor core.
13. A multicore processor chip comprising the controller of any of claims 9 to 12.
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| CN111415291B (en) * | 2020-02-21 | 2021-09-21 | 华为技术有限公司 | Multi-core chip and scheduling method thereof |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101354664A (en) * | 2008-08-19 | 2009-01-28 | 中兴通讯股份有限公司 | Method and apparatus for interrupting load equilibrium of multi-core processor |
| KR20130112180A (en) * | 2012-04-03 | 2013-10-14 | 주식회사 알투소프트 | Method for scheduling of mobile multi-core virtualization system to guarantee real time process |
| CN103544125A (en) * | 2012-07-12 | 2014-01-29 | 深圳市中兴微电子技术有限公司 | Interrupt control method, interrupt processing method, interrupt controller and processor |
| CN103765399A (en) * | 2011-08-23 | 2014-04-30 | 三星电子株式会社 | Method and apparatus for allocating interrupts in multi-core system |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101354664A (en) * | 2008-08-19 | 2009-01-28 | 中兴通讯股份有限公司 | Method and apparatus for interrupting load equilibrium of multi-core processor |
| CN103765399A (en) * | 2011-08-23 | 2014-04-30 | 三星电子株式会社 | Method and apparatus for allocating interrupts in multi-core system |
| KR20130112180A (en) * | 2012-04-03 | 2013-10-14 | 주식회사 알투소프트 | Method for scheduling of mobile multi-core virtualization system to guarantee real time process |
| CN103544125A (en) * | 2012-07-12 | 2014-01-29 | 深圳市中兴微电子技术有限公司 | Interrupt control method, interrupt processing method, interrupt controller and processor |
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