CN107102955B - 用于存储子系统的关联和原子回写高速缓冲存储系统和方法 - Google Patents
用于存储子系统的关联和原子回写高速缓冲存储系统和方法 Download PDFInfo
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- CN107102955B CN107102955B CN201710087102.5A CN201710087102A CN107102955B CN 107102955 B CN107102955 B CN 107102955B CN 201710087102 A CN201710087102 A CN 201710087102A CN 107102955 B CN107102955 B CN 107102955B
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
- G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
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- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
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- G06F12/122—Replacement control using replacement algorithms of the least frequently used [LFU] type, e.g. with individual count value
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- G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
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- G06F2212/10—Providing a specific technical effect
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- G06F2212/1024—Latency reduction
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- G06F2212/62—Details of cache specific to multiprocessor cache arrangements
- G06F2212/621—Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
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- G06F2212/65—Details of virtual memory and virtual address translation
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- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/70—Details relating to dynamic memory management
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/048,080 US10169232B2 (en) | 2016-02-19 | 2016-02-19 | Associative and atomic write-back caching system and method for storage subsystem |
| US15/048,080 | 2016-02-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107102955A CN107102955A (zh) | 2017-08-29 |
| CN107102955B true CN107102955B (zh) | 2020-03-13 |
Family
ID=59629440
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710087102.5A Active CN107102955B (zh) | 2016-02-19 | 2017-02-17 | 用于存储子系统的关联和原子回写高速缓冲存储系统和方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US10169232B2 (enExample) |
| JP (1) | JP6832187B2 (enExample) |
| KR (1) | KR102805147B1 (enExample) |
| CN (1) | CN107102955B (enExample) |
Families Citing this family (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20180004668A1 (en) * | 2016-06-30 | 2018-01-04 | Intel Corporation | Searchable hot content cache |
| US10657049B2 (en) * | 2016-10-17 | 2020-05-19 | SK Hynix Inc. | Memory system and operating method thereof |
| US10282301B2 (en) * | 2017-05-18 | 2019-05-07 | Avago Technologies International Sales Pte. Limited | Method and system for hardware accelerated read-ahead caching |
| US10528438B2 (en) * | 2017-05-25 | 2020-01-07 | Avago Technologies International Sales Pte. Limited | Method and system for handling bad blocks in a hardware accelerated caching solution |
| US10565109B2 (en) * | 2017-09-05 | 2020-02-18 | International Business Machines Corporation | Asynchronous update of metadata tracks in response to a cache hit generated via an I/O operation over a bus interface |
| CN107577439B (zh) * | 2017-09-28 | 2020-10-20 | 苏州浪潮智能科技有限公司 | 分配处理资源的方法、装置、设备及计算机可读存储介质 |
| US10819647B2 (en) * | 2017-12-06 | 2020-10-27 | Marvell Israel (M.I.S.L) Ltd. | Network device having reduced latency |
| US10705969B2 (en) * | 2018-01-19 | 2020-07-07 | Samsung Electronics Co., Ltd. | Dedupe DRAM cache |
| US11755499B2 (en) * | 2018-05-31 | 2023-09-12 | Secturion Systems, Inc. | Locally-stored remote block data integrity |
| US10628072B2 (en) | 2018-08-21 | 2020-04-21 | Samsung Electronics Co., Ltd. | Scalable architecture enabling large memory system for in-memory computations |
| KR102795565B1 (ko) * | 2019-02-19 | 2025-04-15 | 에스케이하이닉스 주식회사 | 메모리 시스템의 맵 데이터 관리 방법 및 장치 |
| US11106609B2 (en) * | 2019-02-28 | 2021-08-31 | Micron Technology, Inc. | Priority scheduling in queues to access cache data in a memory sub-system |
| US10908821B2 (en) * | 2019-02-28 | 2021-02-02 | Micron Technology, Inc. | Use of outstanding command queues for separate read-only cache and write-read cache in a memory sub-system |
| CN114746848B (zh) | 2019-12-03 | 2023-08-04 | 美光科技公司 | 用于存储装置的高速缓存架构 |
| US11245774B2 (en) * | 2019-12-16 | 2022-02-08 | EMC IP Holding Company LLC | Cache storage for streaming data |
| US11157193B2 (en) * | 2019-12-16 | 2021-10-26 | Micron Technology, Inc. | Coherency issue resolution in logical to physical page translation in a memory sub-system |
| CN112988623B (zh) * | 2019-12-17 | 2021-12-21 | 北京忆芯科技有限公司 | 加速sgl处理的方法与存储设备 |
| CN111159065B (zh) * | 2019-12-31 | 2025-09-16 | 厦门鑫忆讯科技有限公司 | 带有关键字的硬件缓存管理单元(bmu) |
| US11210168B1 (en) | 2020-06-25 | 2021-12-28 | Micron Technology, Inc. | Error handling optimization in memory sub-system mapping |
| CN115407942B (zh) * | 2022-08-29 | 2023-07-14 | 深圳市锦锐科技股份有限公司 | 一种适用于单片机芯片的数据处理方法 |
| CN116303138B (zh) * | 2023-05-08 | 2023-08-29 | 北京云脉芯联科技有限公司 | 一种缓存架构及缓存方法、电子设备 |
| CN117609314A (zh) * | 2024-01-22 | 2024-02-27 | 北京象帝先计算技术有限公司 | 一种缓存数据处理方法、缓存控制器、芯片及电子设备 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6845426B2 (en) * | 2001-03-15 | 2005-01-18 | Nec Corporation | Disk cache control for servicing a plurality of hosts |
| CN1604055A (zh) * | 2003-09-30 | 2005-04-06 | 国际商业机器公司 | 利用永久历史页表数据预取数据到高速缓存的装置和方法 |
| CN104956311A (zh) * | 2013-10-09 | 2015-09-30 | 株式会社日立制作所 | 存储系统以及存储控制方法 |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7124243B2 (en) * | 2003-05-16 | 2006-10-17 | Pillar Data Systems, Inc. | Methods and systems of cache memory management and snapshot operations |
| US20060090016A1 (en) * | 2004-10-27 | 2006-04-27 | Edirisooriya Samantha J | Mechanism to pull data into a processor cache |
| JP4420351B2 (ja) * | 2005-09-30 | 2010-02-24 | 富士通株式会社 | 階層ストレージシステム、制御方法及びプログラム |
| JP2010160544A (ja) * | 2009-01-06 | 2010-07-22 | Core Micro Systems Inc | キャッシュメモリシステム及びキャッシュメモリの制御方法 |
| US8495299B2 (en) | 2009-11-16 | 2013-07-23 | Microsoft Corporation | Non-blocking data transfer via memory cache manipulation |
| US10013354B2 (en) | 2010-07-28 | 2018-07-03 | Sandisk Technologies Llc | Apparatus, system, and method for atomic storage operations |
| JP2013097416A (ja) * | 2011-10-28 | 2013-05-20 | Hitachi Ltd | 記憶装置および計算機 |
| KR20130064518A (ko) * | 2011-12-08 | 2013-06-18 | 삼성전자주식회사 | 저장 장치 및 그것의 동작 방법 |
| US9384072B2 (en) * | 2012-12-20 | 2016-07-05 | Oracle International Corporation | Distributed queue pair state on a host channel adapter |
| US20140344503A1 (en) * | 2013-05-17 | 2014-11-20 | Hitachi, Ltd. | Methods and apparatus for atomic write processing |
| US9430396B2 (en) * | 2014-12-22 | 2016-08-30 | Intel Corporation | Updating persistent data in persistent memory-based storage |
| US9910797B2 (en) * | 2015-10-05 | 2018-03-06 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Space efficient formats for scatter gather lists |
-
2016
- 2016-02-19 US US15/048,080 patent/US10169232B2/en active Active
-
2017
- 2017-02-17 KR KR1020170021794A patent/KR102805147B1/ko active Active
- 2017-02-17 JP JP2017028194A patent/JP6832187B2/ja not_active Expired - Fee Related
- 2017-02-17 CN CN201710087102.5A patent/CN107102955B/zh active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6845426B2 (en) * | 2001-03-15 | 2005-01-18 | Nec Corporation | Disk cache control for servicing a plurality of hosts |
| CN1604055A (zh) * | 2003-09-30 | 2005-04-06 | 国际商业机器公司 | 利用永久历史页表数据预取数据到高速缓存的装置和方法 |
| CN104956311A (zh) * | 2013-10-09 | 2015-09-30 | 株式会社日立制作所 | 存储系统以及存储控制方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| US10169232B2 (en) | 2019-01-01 |
| CN107102955A (zh) | 2017-08-29 |
| KR102805147B1 (ko) | 2025-05-08 |
| US20170242794A1 (en) | 2017-08-24 |
| JP6832187B2 (ja) | 2021-02-24 |
| KR20170098187A (ko) | 2017-08-29 |
| JP2017151982A (ja) | 2017-08-31 |
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