CN107093593B - A kind of encapsulation chip and packaging method - Google Patents
A kind of encapsulation chip and packaging method Download PDFInfo
- Publication number
- CN107093593B CN107093593B CN201710148504.1A CN201710148504A CN107093593B CN 107093593 B CN107093593 B CN 107093593B CN 201710148504 A CN201710148504 A CN 201710148504A CN 107093593 B CN107093593 B CN 107093593B
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- CN
- China
- Prior art keywords
- chip
- printed circuit
- hole
- circuit board
- encapsulation
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
Abstract
The present invention relates to chip encapsulation technology fields, provide a kind of encapsulation chip and packaging method, the encapsulation chip include printed circuit board, set on the printed circuit board upper surface chip and be used to encapsulate the packing colloid of the chip set on the printed circuit board upper surface, the printed circuit board lower surface and with the packing colloid corresponding position be equipped with the first tin ball, the chip is fixed on the printed circuit board by the second tin ball, the printed circuit board is equipped with through-hole, and the through-hole is located at the beneath chips.In the present invention, on a printed circuit and correspond to setting through-hole at chip, in secondary SMT, the air between chip and printed circuit board in through-hole by being discharged, to avoid the second tin ball from bursting or printed circuit board generation bulge phenomenon, the yields of encapsulation chip is improved.
Description
Technical field
The present invention relates to chip encapsulation technology fields, are to be related to a kind of encapsulation chip and packaging method more specifically.
Background technique
Existing BGA (Ball Grid Array, ball array encapsulation) encapsulation chip, since the lower section of bga chip is arranged
There is tin ball, therefore at molding (mold), packing colloid stream into the lower section of bga chip or cannot not filled up under bga chip
The space of side forms a closed space, when carrying out secondary SMT, the envelope between such bga chip and printed circuit board
The residual air meeting expanded by heating for closing space, so that the tin ball of surrounding bursts or printed circuit board is made to generate bulge etc. no
Good phenomenon.And in order to solve this technical problem, it is general using in the chip it is external increase heat sink material heat is quickly dispersed from
And the air heats in enclosure space is avoided to expand.In this way, not only increasing the cost of chip, the body of encapsulation chip is also increased
Product.
Summary of the invention
The purpose of the present invention is to provide a kind of encapsulation chip and packaging methods, it is intended to solve BGA package in the prior art
Chip is in secondary SMT, the problem of tin ball easily bursts or printed circuit board is also easy to produce bulge.
In order to solve the above technical problems, the technical scheme is that providing a kind of encapsulation chip, including printed circuit
Plate, set on the chip of the printed circuit board upper surface and set on the printed circuit board upper surface for encapsulating the chip
Packing colloid, the printed circuit board lower surface and be equipped with the first tin ball with the packing colloid corresponding position, the chip is logical
It crosses the second tin ball to be fixed on the printed circuit board, the printed circuit board is equipped with through-hole, and the through-hole is located at the core
Below piece.
Preferably, the chip is set between two parties on the printed circuit board, and it is placed in the middle that the through-hole is located at the beneath chips
Position.
Preferably, the printed circuit board upper surface and be located at the chip around be equipped with baffle.
Preferably, the chip is the dram chip for being provided with the second tin ball.
Preferably, the chip be it is multiple, the through-hole be it is multiple, be respectively equipped with the through-hole under each chip.
Preferably, the through-hole is one, and the diameter of the through-hole is 1.27 ± 0.05mm.
Preferably, the through-hole is multiple, and multiple through-holes are uniformly distributed, the diameter of each through-hole is 0.3 ±
0.05mm。
Preferably, the through-hole is nine.
The present invention also provides a kind of packaging methods for encapsulating chip, comprising the following steps:
Through-hole is set on a printed circuit；
Chip is placed in the printed circuit board upper surface and is located above the through-hole；
In the printed circuit board upper surface is arranged packing colloid and is molded into the chip.
Preferably, when the chip is arranged, the gap between the chip and the printed circuit board is less than 0.1mm.
Preferably, when the chip is arranged, baffle is set around Yu Suoshu chip.
In the present invention, on a printed circuit and correspond to setting through-hole at chip, in secondary SMT, chip and printing
Air between circuit board in through-hole by being discharged, so that the explosion of the second tin ball or printed circuit board is avoided to generate bulge phenomenon,
Improve the yields of encapsulation chip.
Detailed description of the invention
Fig. 1 is the cross-sectional view of encapsulation chip provided in an embodiment of the present invention；
Fig. 2 is the bottom view of encapsulation chip provided in an embodiment of the present invention；
Fig. 3 is the packaging method flow chart of encapsulation chip provided in an embodiment of the present invention.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
It should be noted that it can be directly another when element is referred to as " being fixed on " or " being set to " another element
On one element or indirectly on another element.When an element is known as " being connected to " another element, it can
To be directly to another element or be indirectly connected on another element.
It should also be noted that, the positional terms such as left and right, upper and lower in the present embodiment, be only each other relative concept or
It is reference with the normal operating condition of product, and should not be regarded as restrictive.
Referring to Fig.1, Fig. 2 the embodiment of the invention provides a kind of encapsulation chip, including printed circuit board 10, is set to printing
The chip 20 of 10 upper surface of circuit board and the packing colloid 30 for being used to encapsulate chip 20 set on 10 upper surface of printed circuit board, print
10 lower surface of printed circuit board and it is equipped with the first tin ball 40 with 30 corresponding position of packing colloid, chip 20 is fixed on by the second tin ball 50
On printed circuit board 10, printed circuit board 10 is equipped with through-hole 11, and through-hole 11 is located at 20 lower section of chip.
In the present embodiment, on the printed circuit board 10 and correspond to setting through-hole 11 at chip 20, in secondary SMT, core
Air between piece 20 and printed circuit board 10 in through-hole 11 by being discharged, to avoid the explosion of the second tin ball 50 or printed circuit
Plate 10 generates bulge phenomenon, improves the yields of encapsulation chip.
Preferably, in the present embodiment, chip 20 is set to 10 upper surface of printed circuit board between two parties, and through-hole 11 is located at chip 20
Centered beneath position, which is that through-hole 11 is corresponding, to be located at 20 center of chip.Through-hole 11 is set to this, in secondary SMT, residual
It can be preferably discharged after air heats between chip 20 and printed circuit board 10.
Further, in this embodiment 10 upper surface of printed circuit board and be located at chip 20 around be equipped with baffle (in figure not
It shows).In mold, baffle can block packing colloid 30, avoid packing colloid 30 from flowing into 20 lower space of chip and then flow
Enter through-hole 11 and causes residual air that cannot be discharged the closure of through-hole 11.
Referring to Fig. 2, in the present embodiment, chip 20 is DRAM (the Dynamic Random for being provided with the second tin ball 50
Access Memory, i.e. dynamic random access memory chip.Using this chip 20, second on chip 20 is directly utilized
Chip 20 is fixed on printed circuit board 10 by tin ball 50.
In the present embodiment, chip 20 is one, and through-hole 11 is one, and the diameter of through-hole 11 is 1.27 ± 0.05mm.As
Multiple relatively small through-holes 11 also can be set in alternative solution, and multiple small through hole 11 are uniformly distributed, the diameter of each small through hole 11
For 0.3 ± 0.05mm.Specifically, through-hole 11 can be set 9.
As an alternative, chip 20 or multiple, through-hole 11 be also it is multiple, be respectively provided with below each chip 20 logical
Hole 11, to ensure that inner air can be discharged by the through-hole 11 of lower section in each chip 20.
In the present embodiment, packing colloid 30 is the biggish packing colloid of particle, this 30 mobility of bulky grain packing colloid
Difference effectively prevent packing colloid 30 to flow into through-hole 11 and block up so that packing colloid 30 difficultly flows into 20 lower section of chip in mold
Plug through-hole 11 causes internal gas that cannot be discharged.
Referring to Fig. 3, the embodiment of the invention also provides a kind of packaging methods for encapsulating chip, comprising the following steps:
S1, through-hole 11 is set on a printed circuit；
S2, chip 20 is placed in 10 upper surface of printed circuit board and is located at 11 top of through-hole；
S3, packing colloid 30 is set in 10 upper surface of printed circuit board and is molded into chip 20 interior.
In S1 step, chip 20 is set to the middle position of printed circuit board 10, in this way, leading to when through-hole 11 is arranged
Hole 11 is also disposed on the middle position of printed circuit board 10.It certainly, can also be according to chip 20 when 20 position change of chip
Position is arranged through-hole 11.Setting principle is, after chip 20 is arranged, through-hole 11 is corresponding to be located at 20 center of chip, in this way,
The air that can be effectively ensured between chip 20 and printed circuit board 10 is completely exhausted out.
In the present embodiment, a through-hole 11 is set.The diameter of through-hole 11 is 1.27 ± 0.05mm.As an alternative,
Multiple relatively small through-holes 11 can be set, multiple small through hole 11 are uniformly distributed, and the diameter of each small through hole 11 is 0.3 ±
0.05mm.Specifically, through-hole 11 can be set 9.
In the present embodiment, a chip 20 is set in S2 step.Certainly, chip 20 also can be set multiple, through-hole 11
It is also provided with multiple, a through-hole 11 is respectively provided with below each chip 20, to ensure that each chip 20 can be by the through-hole of lower section
11 discharge inner airs.
In the present embodiment, chip 20 is DRAM (the Dynamic Random Access for being provided with the second tin ball 50
Memory, i.e. dynamic random access memory chip 20.Using this chip 20, the second tin ball 50 on chip 20 is directly utilized
Chip 20 is fixed on printed circuit board 10.
When chip 20 is arranged, the gap between 10 upper surface of chip 20 and printed circuit board is small as far as possible, and specific gap can
Less than 0.1mm.Simultaneously in step s3, bulky grain packing colloid 30 is selected.This bulky grain packing colloid poor fluidity, thus
In mold, packing colloid 30 difficultly flows into 20 lower section of chip, and packing colloid 30 is effectively prevent to flow into through-hole 11 and block through-hole
11 cause internal gas that cannot be discharged.
In the present embodiment, when chip 20 is arranged, baffle is set in 20 surrounding of chip.In mold, baffle can be blocked
Packing colloid 30 avoids packing colloid 30 from flowing into 20 lower space of chip and then flows into through-hole 11 and cause the closure of through-hole 11 residual
Gas of leaving a blank cannot be discharged.
The above is merely preferred embodiments of the present invention, be not intended to limit the invention, it is all in spirit of the invention and
Made any modifications, equivalent replacements, and improvements etc., should all be included in the protection scope of the present invention within principle.
Claims (9)
1. a kind of encapsulation chip, including printed circuit board, set on the chip of the printed circuit board upper surface and set on described
Printed circuit board upper surface is used to encapsulate the packing colloid of the chip, the printed circuit board lower surface and with the packaging plastic
Body corresponding position is equipped with the first tin ball, and the chip is fixed on the printed circuit board by the second tin ball, it is characterised in that: institute
Printed circuit board is stated equipped with through-hole, the through-hole is located at the beneath chips, the printed circuit board upper surface and positioned at institute
It states and is equipped with baffle around chip.
2. encapsulation chip as described in claim 1, it is characterised in that: the chip is set between two parties on the printed circuit board,
The through-hole is located at the beneath chips middle position.
3. encapsulation chip as described in claim 1, it is characterised in that: the chip is the DRAM core for being provided with the second tin ball
Piece.
4. as described in claim 1 encapsulation chip, it is characterised in that: the chip be it is multiple, the through-hole be multiple, each institute
It states and is respectively equipped with the through-hole under chip.
5. encapsulation chip as described in claim 1, it is characterised in that: the through-hole is one, and the diameter of the through-hole is
1.27±0.05mm。
6. as described in claim 1 encapsulation chip, it is characterised in that: the through-hole be it is multiple, multiple through-holes uniformly divide
Cloth, the diameter of each through-hole are 0.3 ± 0.05mm.
7. encapsulation chip as claimed in claim 6, it is characterised in that: the through-hole is nine.
8. a kind of packaging method for encapsulating chip, it is characterised in that: the following steps are included:
Through-hole is set on a printed circuit；
Chip is placed in the printed circuit board upper surface and is located above the through-hole, when the chip is arranged, the core
Gap between piece and the printed circuit board is less than 0.1mm；
In the printed circuit board upper surface is arranged packing colloid and is molded into the chip.
9. the packaging method of encapsulation chip as claimed in claim 8, it is characterised in that: when the chip is arranged, Yu Suoshu
Baffle is set around chip.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710148504.1A CN107093593B (en) | 2017-03-14 | 2017-03-14 | A kind of encapsulation chip and packaging method |
| PCT/CN2017/117764 WO2018166264A1 (en) | 2017-03-14 | 2017-12-21 | Packaged chip and packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710148504.1A CN107093593B (en) | 2017-03-14 | 2017-03-14 | A kind of encapsulation chip and packaging method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107093593A CN107093593A (en) | 2017-08-25 |
| CN107093593B true CN107093593B (en) | 2019-08-13 |
Family
ID=59646278
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710148504.1A Active CN107093593B (en) | 2017-03-14 | 2017-03-14 | A kind of encapsulation chip and packaging method |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN107093593B (en) |
| WO (1) | WO2018166264A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107093593B (en) * | 2017-03-14 | 2019-08-13 | 深圳市江波龙电子股份有限公司 | A kind of encapsulation chip and packaging method |
| CN107393838A (en) * | 2017-04-20 | 2017-11-24 | 北京时代民芯科技有限公司 | A kind of plate level reinforcement means for improving the ceramic QFP228 encapsulation anti-random vibration performance of chip |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997001865A1 (en) * | 1995-06-28 | 1997-01-16 | Hitachi, Ltd. | Semiconductor device and method of manufacturing the same |
| CN101459155A (en) * | 2007-12-12 | 2009-06-17 | 三星电子株式会社 | Circuit board having bypass pad |
| CN201298552Y (en) * | 2008-11-18 | 2009-08-26 | 好德科技股份有限公司 | Ball-bar array packaged chip |
| CN101945530A (en) * | 2009-07-09 | 2011-01-12 | 佛山市顺德区顺达电脑厂有限公司 | Printed circuit board with pad provided with exhaust through holes |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080157342A1 (en) * | 2007-01-03 | 2008-07-03 | Advanced Chip Engineering Technology Inc. | Package with a marking structure and method of the same |
| CN107093593B (en) * | 2017-03-14 | 2019-08-13 | 深圳市江波龙电子股份有限公司 | A kind of encapsulation chip and packaging method |
-
2017
- 2017-03-14 CN CN201710148504.1A patent/CN107093593B/en active Active
- 2017-12-21 WO PCT/CN2017/117764 patent/WO2018166264A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997001865A1 (en) * | 1995-06-28 | 1997-01-16 | Hitachi, Ltd. | Semiconductor device and method of manufacturing the same |
| CN101459155A (en) * | 2007-12-12 | 2009-06-17 | 三星电子株式会社 | Circuit board having bypass pad |
| CN201298552Y (en) * | 2008-11-18 | 2009-08-26 | 好德科技股份有限公司 | Ball-bar array packaged chip |
| CN101945530A (en) * | 2009-07-09 | 2011-01-12 | 佛山市顺德区顺达电脑厂有限公司 | Printed circuit board with pad provided with exhaust through holes |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107093593A (en) | 2017-08-25 |
| WO2018166264A1 (en) | 2018-09-20 |
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Address after: 518000 A, B, C, D, E, F1, 8 Building, Financial Services Technology Innovation Base, No. 8 Kefa Road, Nanshan District, Shenzhen City, Guangdong Province Applicant after: Shenzhen jiangbolong electronic Limited by Share Ltd Address before: 518057 8 building, 1 finance base, 8 KFA Road, Nanshan District, Shenzhen, Guangdong. Applicant before: Shenzhen jiangbolong Electronic Co., Ltd. |
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