CN107060903A - Turbine emergency interrupting system based on FPGA - Google Patents
Turbine emergency interrupting system based on FPGA Download PDFInfo
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- CN107060903A CN107060903A CN201611225835.2A CN201611225835A CN107060903A CN 107060903 A CN107060903 A CN 107060903A CN 201611225835 A CN201611225835 A CN 201611225835A CN 107060903 A CN107060903 A CN 107060903A
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- 238000004891 communication Methods 0.000 claims abstract description 22
- 230000008054 signal transmission Effects 0.000 claims description 17
- 230000005540 biological transmission Effects 0.000 claims description 15
- 230000004044 response Effects 0.000 abstract description 6
- 238000005516 engineering process Methods 0.000 abstract description 3
- 238000010276 construction Methods 0.000 abstract 1
- 239000000523 sample Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F01—MACHINES OR ENGINES IN GENERAL; ENGINE PLANTS IN GENERAL; STEAM ENGINES
- F01D—NON-POSITIVE DISPLACEMENT MACHINES OR ENGINES, e.g. STEAM TURBINES
- F01D21/00—Shutting-down of machines or engines, e.g. in emergency; Regulating, controlling, or safety means not otherwise provided for
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F01—MACHINES OR ENGINES IN GENERAL; ENGINE PLANTS IN GENERAL; STEAM ENGINES
- F01D—NON-POSITIVE DISPLACEMENT MACHINES OR ENGINES, e.g. STEAM TURBINES
- F01D21/00—Shutting-down of machines or engines, e.g. in emergency; Regulating, controlling, or safety means not otherwise provided for
- F01D21/003—Arrangements for testing or measuring
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F01—MACHINES OR ENGINES IN GENERAL; ENGINE PLANTS IN GENERAL; STEAM ENGINES
- F01D—NON-POSITIVE DISPLACEMENT MACHINES OR ENGINES, e.g. STEAM TURBINES
- F01D21/00—Shutting-down of machines or engines, e.g. in emergency; Regulating, controlling, or safety means not otherwise provided for
- F01D21/02—Shutting-down responsive to overspeed
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F05—INDEXING SCHEMES RELATING TO ENGINES OR PUMPS IN VARIOUS SUBCLASSES OF CLASSES F01-F04
- F05D—INDEXING SCHEME FOR ASPECTS RELATING TO NON-POSITIVE-DISPLACEMENT MACHINES OR ENGINES, GAS-TURBINES OR JET-PROPULSION PLANTS
- F05D2270/00—Control
- F05D2270/01—Purpose of the control system
- F05D2270/02—Purpose of the control system to control rotational speed (n)
- F05D2270/021—Purpose of the control system to control rotational speed (n) to prevent overspeed
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F05—INDEXING SCHEMES RELATING TO ENGINES OR PUMPS IN VARIOUS SUBCLASSES OF CLASSES F01-F04
- F05D—INDEXING SCHEME FOR ASPECTS RELATING TO NON-POSITIVE-DISPLACEMENT MACHINES OR ENGINES, GAS-TURBINES OR JET-PROPULSION PLANTS
- F05D2270/00—Control
- F05D2270/01—Purpose of the control system
- F05D2270/09—Purpose of the control system to cope with emergencies
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F05—INDEXING SCHEMES RELATING TO ENGINES OR PUMPS IN VARIOUS SUBCLASSES OF CLASSES F01-F04
- F05D—INDEXING SCHEME FOR ASPECTS RELATING TO NON-POSITIVE-DISPLACEMENT MACHINES OR ENGINES, GAS-TURBINES OR JET-PROPULSION PLANTS
- F05D2270/00—Control
- F05D2270/40—Type of control system
- F05D2270/46—Type of control system redundant, i.e. failsafe operation
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- Engineering & Computer Science (AREA)
- Mechanical Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Small-Scale Networks (AREA)
Abstract
A kind of turbine emergency interrupting system based on FPGA, is related to steam turbine technology field, and what is solved is to speed up the technical problem of response speed.The system, including multiple ETS votings card, multiple tach signal cards, multiple switch signal distribution card；The ETS votings card includes FPGA votings module, IOP processing modules, the first connector；Each ETS voting cards are interconnected by communication port；The tach signal card includes FPGA rotating speed modules, IOP processing modules, the second connector；The LVDS sending ports of every speed signal card are coupled with the LVDS receiving ports of each ETS voting cards；The switching signal distribution card includes FPGA distribute modules, IOP processing modules, the 3rd connector；The LVDS sending ports of each switching signal distribution card are coupled with the LVDS receiving ports of each ETS voting cards.The system that the present invention is provided, simple in construction and fast response time.
Description
Technical field
The present invention relates to steam turbine technology, the skill of more particularly to a kind of turbine emergency interrupting system based on FPGA
Art.
Background technology
ETS systems（Turbine emergency interrupting system）In the steam turbine operation control room for being all disposed within thermal power plant, nuclear power plant.
At present, ETS systems all realize the running protection to steam turbine by configuration using safety PLC, with response speed slowly lack
Fall into, when steam turbine goes wrong, easily because response speed is slow and caused by Steam Turbine Over-speed Accident or the major accident that can not shut down.
The content of the invention
For defect present in above-mentioned prior art, the technical problems to be solved by the invention are to provide a kind of response speed
The fast turbine emergency interrupting system based on FPGA of degree.
In order to solve the above-mentioned technical problem, a kind of turbine emergency interrupting system based on FPGA provided by the present invention,
Including multiple ETS votings card, multiple tach signal cards, multiple switch signal distribution card；
The ETS votings card includes FPGA votings module, the first IOP processing modules, the first connector；
FPGA voting module, the first connector respectively have multi-path digital signal input port, multi-path digital signal output port,
Multi-path serial communication port, 1 road LVDS sending ports, multichannel LVDS receiving ports；Each railway digital signal of first connector is defeated
Inbound port is each to be coupled with each railway digital signal input port that FPGA decides by vote module, first through a digital signal transmission passage
Each railway digital signal output port of connector is each to be coupled with each of FPGA voting modules through a digital signal transmission passage
Railway digital signal output port, each road communication port of the first connector is respectively coupled with FPGA tables through a serial-port
Certainly each road communication port of module, the LVDS sending ports of the first connector are connected to FPGA votings through a LVDS transmission channels
The LVDS sending ports of module, each road LVDS receiving ports of the first connector are respectively coupled with through a LVDS transmission channel
FPGA decides by vote each road LVDS receiving ports of module；
Provided with the first FPGA processing submodule, the first CPU submodules, the first FPGA therein in the first IOP processing modules
Submodule is handled through data wire and FPGA voting module interconnections, and the first FPGA processing submodules are defeated provided with multi-path digital signal
Inbound port, each railway digital signal input port of the first connector is each to be coupled with first through a digital signal transmission passage
FPGA handles each railway digital signal input port of submodule, and the first FPGA processing submodules and the first CPU submodules are through data
Bus bar；
First connector of each ETS voting cards is interconnected by communication port；
The tach signal card includes FPGA rotating speed modules, the 2nd IOP processing modules, the second connector；
The FPGA rotating speed modules, the second connector respectively have 1 road tach signal input port, multichannel tach signal forwarding port, 2
Road LVDS sending ports；The tach signal input port of second connector is connected to FPGA rotating speeds through a tach signal transmission channel
The tach signal input port of module, each transmitted through a tach signal in each road tach signal forwarding port of the second connector is led to
Road is coupled with each road tach signal forwarding port of FPGA rotating speed modules, and 2 road LVDS sending ports of the second connector are respectively passed through
One LVDS transmission channel is coupled with 2 road LVDS sending ports of FPGA rotating speed modules；
Provided with the 2nd FPGA processing submodule, the 2nd CPU submodules, the 2nd FPGA therein in the 2nd IOP processing modules
Handle submodule to interconnect through data wire and FPGA rotating speed modules, the 2nd FPGA processing submodules and the 2nd CPU submodules are through data
Bus bar；
2 road LVDS sending ports of the second connector of every speed signal card are coupled with the first company of each ETS voting cards
The LVDS receiving ports of fitting；
The switching signal distribution card includes FPGA distribute modules, the 3rd IOP processing modules, the 3rd connector；
The FPGA distribute modules, the 3rd connector respectively have multi-path digital signal input port, 2 road LVDS sending ports；3rd
Each railway digital signal input port of connector is each to be coupled with each of FPGA distribute modules through a digital signal transmission passage
Railway digital signal input port, 2 road LVDS sending ports of the 3rd connector are respectively coupled with through a LVDS transmission channel
2 road LVDS sending ports of FPGA distribute modules；
Provided with the 3rd FPGA processing submodule, the 3rd CPU submodules, the 3rd FPGA therein in the 3rd IOP processing modules
Handle submodule to interconnect through data wire and FPGA distribute modules, the 3rd FPGA processing submodules and the 3rd CPU submodules are through data
Bus bar；
2 road LVDS sending ports of the 3rd connector of each switching signal distribution card are coupled with the of each ETS voting cards
The LVDS receiving ports of a connection piece.
The turbine emergency interrupting system based on FPGA that the present invention is provided, system tray is protected using the ETS based on communication
Structure, greatly reduces the line of internal system, and system architecture is relatively easy, the characteristics of with fast response time.
Brief description of the drawings
Fig. 1 is that the structure of the ETS voting cards in the turbine emergency interrupting system based on FPGA of the embodiment of the present invention is shown
It is intended to；
Fig. 2 is the structural representation of the tach signal card in the turbine emergency interrupting system based on FPGA of the embodiment of the present invention
Figure；
Fig. 3 is that the structure of the switching signal distribution card in the turbine emergency interrupting system based on FPGA of the embodiment of the present invention is shown
It is intended to.
Embodiment
Embodiments of the invention are described in further detail below in conjunction with brief description of the drawings, but the present embodiment is not used to limit
The system present invention, every similar structure using the present invention and its similar change, all should be included in protection scope of the present invention, the present invention
In pause mark represent the relation of sum.
A kind of turbine emergency interrupting system based on FPGA that the embodiment of the present invention is provided, including multiple ETS votings
Card, multiple tach signal cards, multiple switch signal distribution card；
As shown in figure 1, the ETS votings card includes FPGA voting modules U11, the first IOP processing modules U12（At input and output
Manage module）, the first connector J1；
The FPGA voting modules U11, the first connector J1 respectively have multi-path digital signal input port, multi-path digital signal output
Port, multi-path serial communication port, 1 road LVDS sending ports（Low-voltage differential signal sending port）, multichannel LVDS receiving terminals
Mouthful（Low-voltage differential signal receiving port）；First connector J1 each railway digital signal input port is each through a data signal
Transmission channel DI is coupled with FPGA voting modules U11 each railway digital signal input port, the first connector J1 each way
Each each railway digital signal that FPGA voting modules U11 is coupled with through a numeral signal transmission passage DO of word signal output port
Output port, the first connector J1 each road communication port is each to be coupled with FPGA voting modules through a serial-port
U11 each road communication port, the first connector J1 LVDS sending ports are connected to FPGA through a LVDS transmission channels L_TX
Decide by vote module U11 LVDS sending ports, the first connector J1 each road LVDS receiving ports are each through a LVDS transmission channel
L_RX is coupled with FPGA voting modules U11 each road LVDS receiving ports；
Provided with the first FPGA processing submodules U121, the first CPU submodules U122 in the first IOP processing modules U12（Micro- place
Manage device submodule）, the first FPGA therein processing submodule is through data wire and FPGA voting module interconnections, and at the first FPGA
Manage submodule and be provided with multi-path digital signal input port, each railway digital signal input port of the first connector is each through a numeral
Signal transmission passage is coupled with each railway digital signal input port that the first FPGA handles submodule, the first FPGA processing submodules
Block is interconnected with the first CPU submodules through data/address bus；
First connector J1 of each ETS voting cards is interconnected by communication port；
As shown in Fig. 2 the tach signal card includes FPGA rotating speed modules U21, the 2nd IOP processing modules U22, the second connector
J2；
The FPGA rotating speed modules U21, the second connector J2 respectively have 1 road tach signal input port, the forwarding of multichannel tach signal
Port, 2 road LVDS sending ports；Second connector J2 tach signal input port connects through a tach signal transmission channel Z1
To FPGA rotating speed modules U21 tach signal input port, the second connector J2 each road tach signal forwarding port is respectively through one
Individual tach signal transmission channel Z2 is coupled with FPGA rotating speed modules J21 each road tach signal forwarding port, the second connector
Each 2 road LVDS transmitting terminals that FPGA rotating speed modules U21 is coupled with through a LVDS transmission channel of J2 2 road LVDS sending ports
Mouthful；
Provided with the 2nd FPGA processing submodules U221, the 2nd CPU submodule U222 in the 2nd IOP processing modules U22, wherein
The 2nd FPGA processing submodules interconnected through data wire and FPGA rotating speed modules, the 2nd FPGA processing submodules and the 2nd CPU
Module is interconnected through data/address bus；
2 road LVDS sending ports of the second connector of every speed signal card are coupled with the first company of each ETS voting cards
The LVDS receiving ports of fitting；
As shown in figure 3, the switching signal distribution card includes FPGA distribute modules U31, the 3rd IOP processing modules U32, the 3rd company
Fitting J3；
The FPGA distribute modules U31, the 3rd connector J3 respectively have multi-path digital signal input port, 2 road LVDS sending ports；
3rd connector J3 each railway digital signal input port is each to be coupled with FPGA distribution through a numeral signal transmission passage DI
Module U31 each railway digital signal input port, each transmitted through a LVDS of the 3rd connector J3 2 road LVDS sending ports is led to
Road L_TX is coupled with FPGA distribute modules U31 2 road LVDS sending ports；
Provided with the 3rd FPGA processing submodules U321, the 3rd CPU submodule U322 in the 3rd IOP processing modules U32, wherein
The 3rd FPGA processing submodules interconnected through data wire and FPGA distribute modules, the 3rd FPGA processing submodules and the 3rd CPU
Module is interconnected through data/address bus；
2 road LVDS sending ports of the 3rd connector of each switching signal distribution card are coupled with the of each ETS voting cards
The LVDS receiving ports of a connection piece.
In the embodiment of the present invention, the digital data transmission passage, serial-port, LVDS transmission channels, tach signal are passed
Defeated passage is prior art, and digital data transmission passage is the signal circuit for transmitting data signal, serial-port
It is the signal circuit for transmitting serial communication data, LVDS transmission channels are used to transmit LVDS signals（Low voltage difference
Signal）, tach signal transmission channel is for transmitting the tach signal that speed probe is gathered.
In the embodiment of the present invention, the IOP processing modules（First, second, third IOP processing modules）For prior art,
IOP processing modules are one piece of general processor plates, can be widely used among different types of IO cards.
The operation principle of the embodiment of the present invention is as follows：
1）Tach signal card
Tach signal card accesses the tach signal that speed probe is gathered by the tach signal input port of the second connector,
And after being handled by FPGA rotating speed modules, send to ETS to decide by vote by the LVDS sending ports of the second connector and block, pass through
The tach signal forwarding port of second connector is sent to other tach signal cards；
In the 2nd IOP processing modules of tach signal card, the 2nd FPGA processing submodules mainly undertake I/O signal（Input and output
Signal）Processing, communicated by data/address bus with the 2nd CPU submodules, realize the friendship of on-site signal and the 2nd CPU submodules
Mutually, the 2nd CPU submodules are responsible for the functions such as configuration, the network service of FPGA rotating speed modules and the 2nd FPGA processing submodules.
2）Switching signal distribution card
Switching signal distribution card accesses pending signal by each railway digital signal input port of the 3rd connector, by FPGA points
Incoming level is normalized with module, logic ' 1 ' is normalized to higher than high-level threshold, is returned less than low level threshold value
One turns to logic ' 0 ', then is sent result to ETS voting cards by the LVDS sending ports of the 3rd connector；
In the 3rd IOP processing modules that switching signal distributes card, the 3rd FPGA processing submodules mainly undertake I/O signal（Input
Output signal）Processing, communicated by data/address bus with the 3rd CPU submodules, realize on-site signal and the 3rd CPU submodules
Interaction, the 3rd CPU submodules are responsible for the functions such as configuration, the network service of FPGA distribute modules and the 3rd FPGA processing submodules.
3）ETS voting cards
ETS votings card receives tach signal card by the LVDS receiving ports of the first connector and switching signal distributes card input
Signal, and analyzed and processed by FPGA votings module, FPGA decides by vote module according to result, passes through the first connector
The corresponding control signal of digital signal output end mouthful output, control relay module action, so as to control in turbine system
The operation of relevant device；
In the first IOP processing modules that ETS decides by vote card, the first FPGA processing submodules mainly undertake I/O signal（Input and output
Signal）Processing, communicated by data/address bus with the first CPU submodules, realize the friendship of on-site signal and the first CPU submodules
Mutually, the first CPU submodules are responsible for the functions such as configuration, the network service of FPGA voting modules and the first FPGA processing submodules.
Each ETS votings card mutually passes the letter of tach signal card and switching signal distribution card input by serial communication mode
Number, redundant input signal is swapped between sequence, this mutual communication pattern passed using point-to-point, any one link event
Barrier does not result in whole communication link fails to cause thrashing.
The embodiment of the present invention is greatly reduced the line of internal system, is using the ETS protection system architectures based on communication
Structure of uniting is relatively easy, and by taking tach signal as an example, traditional each sequence of ETS systems will receive the defeated of three road tach signals
Enter, then carry out hypervelocity voting, and system architecture, each redundant sequence are protected by the ETS based on communication of the embodiment of the present invention
The input of tach signal all the way is only needed to, the input for getting other 2 road tach signals by communication modes is compared, to every
2/3rds are reduced for individual redundant sequence（Triplex level redundancy is inputted）Or 3/4ths（Quadded redundancy is inputted）Input signal,
Simultaneously for voting output signal, it can also mutually be passed by the communication link, greatly reduce the number of line between sequence
Amount, the system risk that the complicated line of reduction is introduced, reduces the failure triggered because of cable mistake.
Claims (1)
1. a kind of turbine emergency interrupting system based on FPGA, including it is multiple ETS votings card, multiple tach signal cards, multiple
Switching signal distribution card；
The ETS votings card includes FPGA votings module, the first IOP processing modules, the first connector；
FPGA voting module, the first connector respectively have multi-path digital signal input port, multi-path digital signal output port,
Multi-path serial communication port, 1 road LVDS sending ports, multichannel LVDS receiving ports；Each railway digital signal of first connector is defeated
Inbound port is each to be coupled with each railway digital signal input port that FPGA decides by vote module, first through a digital signal transmission passage
Each railway digital signal output port of connector is each to be coupled with each of FPGA voting modules through a digital signal transmission passage
Railway digital signal output port, each road communication port of the first connector is respectively coupled with FPGA tables through a serial-port
Certainly each road communication port of module, the LVDS sending ports of the first connector are connected to FPGA votings through a LVDS transmission channels
The LVDS sending ports of module, each road LVDS receiving ports of the first connector are respectively coupled with through a LVDS transmission channel
FPGA decides by vote each road LVDS receiving ports of module；
Provided with the first FPGA processing submodule, the first CPU submodules, the first FPGA therein in the first IOP processing modules
Submodule is handled through data wire and FPGA voting module interconnections, and the first FPGA processing submodules are defeated provided with multi-path digital signal
Inbound port, each railway digital signal input port of the first connector is each to be coupled with first through a digital signal transmission passage
FPGA handles each railway digital signal input port of submodule, and the first FPGA processing submodules and the first CPU submodules are through data
Bus bar；
First connector of each ETS voting cards is interconnected by communication port；
The tach signal card includes FPGA rotating speed modules, the 2nd IOP processing modules, the second connector；
The FPGA rotating speed modules, the second connector respectively have 1 road tach signal input port, multichannel tach signal forwarding port, 2
Road LVDS sending ports；The tach signal input port of second connector is connected to FPGA rotating speeds through a tach signal transmission channel
The tach signal input port of module, each transmitted through a tach signal in each road tach signal forwarding port of the second connector is led to
Road is coupled with each road tach signal forwarding port of FPGA rotating speed modules, and 2 road LVDS sending ports of the second connector are respectively passed through
One LVDS transmission channel is coupled with 2 road LVDS sending ports of FPGA rotating speed modules；
Provided with the 2nd FPGA processing submodule, the 2nd CPU submodules, the 2nd FPGA therein in the 2nd IOP processing modules
Handle submodule to interconnect through data wire and FPGA rotating speed modules, the 2nd FPGA processing submodules and the 2nd CPU submodules are through data
Bus bar；
2 road LVDS sending ports of the second connector of every speed signal card are coupled with the first company of each ETS voting cards
The LVDS receiving ports of fitting；
The switching signal distribution card includes FPGA distribute modules, the 3rd IOP processing modules, the 3rd connector；
The FPGA distribute modules, the 3rd connector respectively have multi-path digital signal input port, 2 road LVDS sending ports；3rd
Each railway digital signal input port of connector is each to be coupled with each of FPGA distribute modules through a digital signal transmission passage
Railway digital signal input port, 2 road LVDS sending ports of the 3rd connector are respectively coupled with through a LVDS transmission channel
2 road LVDS sending ports of FPGA distribute modules；
Provided with the 3rd FPGA processing submodule, the 3rd CPU submodules, the 3rd FPGA therein in the 3rd IOP processing modules
Handle submodule to interconnect through data wire and FPGA distribute modules, the 3rd FPGA processing submodules and the 3rd CPU submodules are through data
Bus bar；
2 road LVDS sending ports of the 3rd connector of each switching signal distribution card are coupled with the of each ETS voting cards
The LVDS receiving ports of a connection piece.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611225835.2A CN107060903A (en) | 2016-12-27 | 2016-12-27 | Turbine emergency interrupting system based on FPGA |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611225835.2A CN107060903A (en) | 2016-12-27 | 2016-12-27 | Turbine emergency interrupting system based on FPGA |
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