CN107039058B - Memory device - Google Patents
Memory device Download PDFInfo
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- CN107039058B CN107039058B CN201710003711.8A CN201710003711A CN107039058B CN 107039058 B CN107039058 B CN 107039058B CN 201710003711 A CN201710003711 A CN 201710003711A CN 107039058 B CN107039058 B CN 107039058B
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- core
- memory
- pin
- circuit
- memory device
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
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Abstract
A kind of memory device, including multiple pins and multiple memory dices.Each memory dice couples these pins, and each memory dice includes match circuit and core circuit.During powering on, according to the voltage quasi position of data pin position or control foot position, match circuit can automatically select institute's memory dice to be started.When core enable signal enable, core circuit is operated, and when core enable signal forbidden energy, core circuit stops operating.When the core circuit of one of these memory dices is operated, the core circuit of remaining memory dice is to stop operating.Memory device provided by the invention can automatically select institute's memory dice to be started according to the voltage level of data pin position or control foot position, therefore be increased without the pin of selection tube core, to reduce the hardware cost of memory device.
Description
Technical field
The present invention relates to a kind of memory device more particularly to a kind of memory devices with multiple memory dices.
Background technique
With the development of semiconductor technology, the area of integrated circuit (IC) is significantly reduced, and is connect using tandem periphery
The communication protocol of mouthful (Serial Peripheral Interface, SPI) is by becoming mainstream, such as low foot position counts (Low
Pin Count, LPC).Advantage is encapsulated brought by the low pin number of tandem perimeter interface in order to enjoy, is increasing capacity or backup
Demand under can consider several tube cores (DIE) or integrated circuit vertical stacking together.However, in order to select to be stacked
Tube core or integrated circuit out of the ordinary, tube core or integrated circuit out of the ordinary chip selection (CS) foot position need independent control.In other words,
The number of pins of the piling IC counted using low foot position can be more than 8, not be available the packaged type of 8 foot positions, therefore palpus
Bigger encapsulation, such as 16 foot positions or 24 foot positions are selected, so that the cost of integrated circuit can not reduce.
Summary of the invention
The present invention provides a kind of memory device, the foot position of selection tube core can be increased without, to reduce memory device
Hardware cost.
Memory device of the invention, including multiple pins and multiple memory dices.Each memory dice couples this
A little pins, and each memory dice includes match circuit and core circuit.Match circuit couples these pins, and powers on
During according to these pins at least one of voltage level provide core enable signal it is to be started to select
Crystal grain.Core circuit couples these pins and match circuit, to receive core enable signal.When core enable signal enable,
Core circuit is operated, and when core enable signal forbidden energy, core circuit stops operating.When these memory dices wherein
One of core circuit when being operated, the core circuit of remaining memory dice is to stop operating.
Based on above-mentioned, the memory device of the embodiment of the present invention, match circuit provides core according to the voltage level of pin
Heart enable signal, with the core circuit in some memory dice of enable.Whereby, memory device is being increased without pin
In the case of, one of automatically starting multiple cores circuit.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make
Carefully it is described as follows.
Detailed description of the invention
Fig. 1 is the system schematic of the memory device of an embodiment according to the present invention；
Fig. 2 is the system schematic of the match circuit of an embodiment according to the present invention；
Fig. 3 is the system schematic of the memory device of another embodiment according to the present invention.
Appended drawing reference:
/ CS: chip selects pin；
/ HOLD: state locks pin；
/ WP: write protection pin；
100,300: memory device；
110,120,310,320,330,340: memory dice；
111,200,311: match circuit；
113,313: core circuit；
210: detector；
220: identification circuit；
230: comparator；
CLK: clock pulse pin；
DI: data-out pin；
DO: data output pins；
GND: grounding pin；
IDcon: identification setting signal；
IDsel: identification selection signal；
IO0: the first output input pin；
IO1: the second output input pin；
IO2: third exports input pin；
IO3: the 4th output input pin；
SCE: core enable signal；
VCC: power pins.
Specific embodiment
Fig. 1 is the system schematic of the memory device of an embodiment according to the present invention.Fig. 1 is please referred to, in the present embodiment
In, memory device 100 includes multiple pins (it is assumed herein that by power pins VCC, grounding pin GND, clock pulse pin CLK, core
Piece selects pin/CS, the first output input pin IO0, second output input pin IO1, third export input pin IO2And the
Four output input pin IO3Constituted) and multiple memory dices (such as memory dice 110, memory dice 120), wherein
Memory dice (such as memory dice 110, memory dice 120) is, for example, vertical stacking.
In the present embodiment, each memory dice (such as memory dice 110, memory dice 120) can all couple
State pin, and each memory dice (such as memory dice 110, memory dice 120) all includes (or being configured with) one
Match circuit (such as match circuit 111) and a core circuit (such as core circuit 113).Core circuit (such as core circuit 113)
Such as with memory born of the same parents' array (not shown) and corresponding read/write circuit (not shown), but the embodiment of the present invention not as
Limit.
Match circuit (such as match circuit 111) couple above-mentioned pin and same memory dice (such as memory dice 110,
Memory dice 120) in core circuit (such as core circuit 113), and at least one of electricity according to above-mentioned pin
Voltage level provides core of the core enable signal SCE into same memory dice (such as core circuit 110, core circuit 120)
Circuit (such as core circuit 113), to determine whether core circuit (such as core circuit 113) starts.Furthermore, it is understood that when core causes
When energy signal SCE enable, core circuit (such as core circuit 113) just will start and be operated；When core enable signal SCE prohibits
When energy, core circuit (such as core circuit 113) will not be activated, i.e., can stop operating.
In the present embodiment, the core of only one memory dice (such as memory dice 110, memory dice 120)
Circuit (such as core circuit 113) can operate, i.e., when memory dice (such as memory dice 110, memory dice 120) wherein
One of core circuit when being operated, the core of remaining memory dice (such as memory dice 110, memory dice 120)
Electrocardio road is to stop operating.In other words, in all memory dices (such as memory dice 110, memory dice 120),
Only one match circuit (such as match circuit 111) can provide the core enable signal SCE of enable in the same time, and remaining
Match circuit (such as match circuit 111) can only provide the core enable signal SCE of forbidden energy.
In the present embodiment, match circuit (such as match circuit 111) can particular point in time (or time zone after the power-up
Between) voltage level detection is carried out, to set provided core enable signal SCE.For example, when power pins VCC rises to
When trigger voltage level (Trigger Voltage/Level) (such as 0.7 times supply voltage), match circuit is (as matched electricity
Road 111) voltage level of the above-mentioned pin of detection instantly, to provide core enable signal SCE；Alternatively, when power pins VCC rises
When after to trigger voltage level through a preset time, match circuit (such as 111) detects the voltage level of above-mentioned pin instantly, to mention
For core enable signal SCE.
Above-mentioned is to judge whether system powers on according to the voltage level of power pins VCC, but in other embodiments, can be according to
Judge whether system powers on according to the voltage foot position of resetting (reset) pin (not shown), depending on this can be according to circuit design, this
Inventive embodiments are not limited.
In general, two memory dices (such as memory dice 110, memory dice 120) can pass through a bit
It selects, i.e., memory dice 110, memory dice 120 can be selected by the voltage level of single pin.In other words,
When the quantity of memory dice (such as memory dice 110, memory dice 120) is 2, all memory dices are (as stored
Device tube core 110, memory dice 120) in match circuit (such as match circuit 111) jointly according to first export input pin
IO0, second output input pin IO1, third export input pin IO2And the 4th output input pin IO3One of electricity
Voltage level provides core enable signal SCE.Also, after core enable signal SCE is provided, match circuit (such as match circuit
111) it can voluntarily close, that is, stop detection, until next system electrification.
In an embodiment of the present invention, output input pin can have a control function in a particular mode, such as first defeated
Input pin IO out0It can be used as data-out pin DI use, the second output input pin IO1It can be used as data output to draw
Foot DO is used, and third exports input pin IO2It can be used as state locking pin/HOLD to use, the 4th output input pin IO3
It can be used as write protection pin/WP to use, this is according to depending on circuit design, and the embodiment of the present invention is not limited.
Fig. 2 is the system schematic of the match circuit of an embodiment according to the present invention.Please refer to Fig. 1 and Fig. 2, match circuit
200 be an example of match circuit 111, and the embodiment of the present invention is not limited.In the present embodiment, match circuit 200 includes
Detector 210, identification circuit 220 and comparator 230.
Detector 210 couples the pin on memory device (such as memory device 100), to detect the voltage of above-mentioned pin
Level, and identification selection signal IDsel is provided according to the voltage level of above-mentioned pin.Identification circuit 220 is default to provide
And changeless identification setting signal IDcon, wherein the bit number of identification setting signal IDcon can be identical to identification selection letter
The bit number of number IDsel.Comparator 230 couples detector 210 and identification circuit 220, to compare identification selection signal IDsel
With identification setting signal IDcon, and accordingly provide core enable signal SCE.
Furthermore, it is understood that comparator 230 provides when identification selection signal IDsel is identical as identification setting signal IDcon
The core enable signal SCE of enable；As identification selection signal IDsel and identification setting signal IDcon difference, comparator 230
The core enable signal SCE of forbidden energy is provided.
In the present embodiment running, the detection of different memory tube core (such as memory dice 110, memory dice 120)
Device (such as detector 210) can provide identical identification selection signal IDsel to comparator (such as comparator 230), and difference is deposited
It is pre-set if the identification circuit (such as identification circuit 220) of memory die (such as memory dice 110, memory dice 120)
Different identification setting signal IDcon, and comparator (such as 230) are provided to, so that all memory dices (such as memory pipe
Core 110, memory dice 120) in, the same time only has a comparator 230 and provides the core enable signal SCE of enable.
As shown in Figure 1, and memory dice 110, being deposited by taking two memory dices 110, memory dice 120 as an example
Memory die 120 can be selected by the voltage level of single pin, i.e. identification selection signal IDsel and identification setting signal
IDcon is the digital signal of a bit.Assuming that the identification setting signal IDcon of memory dice 110 is " 0 ", memory dice
120 identification setting signal IDcon is " 1 ".When identification selection signal IDsel is " 0 ", start the core of memory dice 110
The core circuit (such as core circuit 113) on electrocardio road (such as core circuit 113), memory dice 120 will not operate；When identification is selected
Select signal IDsel be " 1 " when, start memory dice 120 core circuit (such as core circuit 113), memory dice 110
Core circuit (such as core circuit 113) will not operate.
Fig. 3 is the system schematic of the memory device of another embodiment according to the present invention, wherein same or similar element
Use same or similar label.Fig. 1 and Fig. 3 is please referred to, memory device 300 is approximately identical to memory device 100, different
Place is that memory device 300 has 4 vertical stacking memory dices 310, memory dice 320, memory dice
330, memory dice 340, wherein match circuit 311 can refer to the explanation of match circuit 111, and core circuit 313 can refer to core
Electrocardio road 113, it will not be described in detail here.
In general, four memory dices (such as memory dice 310, memory dice 320, memory dice 330,
Memory dice 340) it can be selected by two bits, i.e. memory dice 310, memory dice 320, memory dice
330, memory dice 340 can be selected by the voltage level of two pins.In other words, when memory dice is (as stored
Device tube core 310, memory dice 320, memory dice 330, memory dice 340) quantity be 4 when, all memory pipes
Match circuit in core (such as memory dice 310, memory dice 320, memory dice 330, memory dice 340) is (such as
Match circuit 311) it is common according to the first output input pin IO0, second output input pin IO1, third export input pin
IO2And the 4th output input pin IO3Wherein any two voltage level provide core enable signal SCE.Also, it is providing
After core enable signal SCE, match circuit (such as match circuit 311) can be closed voluntarily, that is, stop detection, until on lower subsystem
Electricity.
Referring to figure 2. and Fig. 3, in four memory dices (such as memory dice 310, memory dice 320, memory
Tube core 330, memory dice 340) in the case where, memory dice (such as memory dice 310, memory dice 320, storage
Device tube core 330, memory dice 340) it can be selected by the voltage level of two pins, i.e. identification selection signal IDsel
And identification setting signal IDcon is the digital signal of two bits.
Such as assume that the identification setting signal IDcon of memory dice 310 is " 00 ", the identification of memory dice 320 is set
Determining signal IDcon is " 01 ", and the identification setting signal IDcon of memory dice 330 is " 10 ", the identification of memory dice 340
Setting signal IDcon is " 11 ".
Then when identification selection signal IDsel is " 00 ", start core circuit (such as core circuit of memory dice 310
313), the core circuit (such as core circuit 313) of memory dice 320, memory dice 330 and memory dice 340 will not
Running；When identification selection signal IDsel is " 01 ", start the core circuit (such as core circuit 313) of memory dice 320,
The core circuit (such as core circuit 313) of memory dice 310, memory dice 330 and memory dice 340 will not operate；
When identification selection signal IDsel is " 10 ", start the core circuit (such as core circuit 313) of memory dice 330, memory
The core circuit (such as core circuit 313) of tube core 310, memory dice 320 and memory dice 340 will not operate；Work as identification
When selection signal IDsel is " 11 ", start the core circuit (such as core circuit 313) of memory dice 340, memory dice
310, the core circuit (such as core circuit 313) of memory dice 320 and memory dice 330 will not operate.
It in the above-described embodiments, is that the logic level of a bit is determined with the voltage level of a pin, but at other
In embodiment, the voltage level of a pin can determine the logic level of two bits, this can be according to detector (detector 210)
Circuit design depending on.Also, the memory pipe stacked in memory device (such as memory device 100, memory device 300)
Core (memory dice 120, memory dice 310, memory dice 320, memory dice 330, deposit by such as memory dice 110
Memory die 340) quantity be to be preferred again with 2 power, to avoid there is no core circuit (such as core circuit after system electrification
113, core circuit 313) it is activated.
In conclusion the memory device of the embodiment of the present invention, match circuit provides core according to the voltage level of pin
Heart enable signal, with the core circuit in some memory dice of enable.Whereby, memory device is being increased without pin
In the case of, one of automatically starting multiple cores circuit.
Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention, any technical field
Middle those of ordinary skill, without departing from the spirit and scope of the present invention, when can make a little change and retouching, in the present invention
In range.
Claims (10)
1. a kind of memory device characterized by comprising
Multiple pins；And
Multiple memory dices, each the multiple memory dice couple the multiple pin, and each the multiple memory
Tube core includes:
Match circuit couples the multiple pin, and when the voltage level judgement according to power pins in the multiple pin
When the memory device powers on, core enable signal is provided, wherein the match circuit is automatic after providing core enable signal
It closes until the memory device powers on again；And
Core circuit couples the multiple pin and the match circuit, to receive the core enable signal, and when described
When core enable signal enable, the core circuit is operated, when the core enable signal forbidden energy, the core circuit
It stops operating；
Wherein when the core circuit of one of the multiple memory dice is operated, remaining is the multiple
The core circuit of memory dice is to stop operating.
2. memory device according to claim 1, which is characterized in that the match circuit includes:
Detector couples the multiple pin, to detect the voltage level of the multiple pin, and according to the multiple pin
At least one of voltage level provide identification selection signal；
Identification circuit, to provide identification setting signal；And
Comparator couples the detector and the identification circuit, sets to the identification selection signal and the identification
Determine signal, and the core enable signal is accordingly provided.
3. memory device according to claim 2, which is characterized in that in different memory dices, the identification
Circuit provides the different identification setting signals, and in different memory dices, and the detector provides identical
The identification selection signal.
4. memory device according to claim 1 or 2, which is characterized in that the multiple pin by the power pins,
Grounding pin, clock pulse pin, chip selection pin, the first output input pin, the second output input pin, third output input
Pin and the 4th output input pin are constituted.
5. memory device according to claim 4, which is characterized in that when the quantity of the multiple memory dice is 2
When, the match circuit is defeated according to the first output input pin, the second output input pin, third output input pin and the 4th
The voltage level of one of input pin provides the core enable signal out.
6. memory device according to claim 4, which is characterized in that when the quantity of the multiple memory dice is 4
When, the match circuit is defeated according to the first output input pin, the second output input pin, third output input pin and the 4th
Wherein any two the voltage level of input pin provides the core enable signal out.
7. memory device according to claim 4, which is characterized in that when the voltage level of the power pins rises to
When trigger voltage level, the match circuit detects the voltage level of the multiple pin, to provide the core enable signal.
8. memory device according to claim 4, which is characterized in that when the voltage level of the power pins rises to
When after trigger voltage level through a preset time, the match circuit detects the voltage level of the multiple pin, to provide
State core enable signal.
9. memory device according to claim 1, which is characterized in that the multiple memory dice is vertical stacking.
10. memory device according to claim 1, which is characterized in that the quantity of the multiple memory dice be 2
Power times.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710003711.8A CN107039058B (en) | 2017-01-04 | 2017-01-04 | Memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710003711.8A CN107039058B (en) | 2017-01-04 | 2017-01-04 | Memory device |
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| Publication Number | Publication Date |
|---|---|
| CN107039058A CN107039058A (en) | 2017-08-11 |
| CN107039058B true CN107039058B (en) | 2019-09-17 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710003711.8A Active CN107039058B (en) | 2017-01-04 | 2017-01-04 | Memory device |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111341367A (en) * | 2018-12-18 | 2020-06-26 | 深圳市江波龙电子股份有限公司 | Control method of storage device, storage device and electronic device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5646897A (en) * | 1994-04-27 | 1997-07-08 | Hitachi, Ltd. | Logic gate circuit and parallel bit test circuit for semiconductor memory devices, capable of operation at low power source levels |
| CN104813400A (en) * | 2012-11-30 | 2015-07-29 | 惠普发展公司，有限责任合伙企业 | Memory controllers to form symbols based on bursts |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4791924B2 (en) * | 2006-09-22 | 2011-10-12 | 株式会社東芝 | Semiconductor memory device |
-
2017
- 2017-01-04 CN CN201710003711.8A patent/CN107039058B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5646897A (en) * | 1994-04-27 | 1997-07-08 | Hitachi, Ltd. | Logic gate circuit and parallel bit test circuit for semiconductor memory devices, capable of operation at low power source levels |
| CN104813400A (en) * | 2012-11-30 | 2015-07-29 | 惠普发展公司，有限责任合伙企业 | Memory controllers to form symbols based on bursts |
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| Publication number | Publication date |
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| CN107039058A (en) | 2017-08-11 |
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