CN107025157A - A kind of algorithm self-checking circuit and method - Google Patents

A kind of algorithm self-checking circuit and method Download PDF

Info

Publication number
CN107025157A
CN107025157A CN201710267111.2A CN201710267111A CN107025157A CN 107025157 A CN107025157 A CN 107025157A CN 201710267111 A CN201710267111 A CN 201710267111A CN 107025157 A CN107025157 A CN 107025157A
Authority
CN
China
Prior art keywords
self
algorithm
parameter
inspection
module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710267111.2A
Other languages
Chinese (zh)
Other versions
CN107025157B (en
Inventor
王子彤
姜凯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shandong Inspur Science Research Institute Co Ltd
Original Assignee
Jinan Inspur Hi Tech Investment and Development Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jinan Inspur Hi Tech Investment and Development Co Ltd filed Critical Jinan Inspur Hi Tech Investment and Development Co Ltd
Priority to CN201710267111.2A priority Critical patent/CN107025157B/en
Publication of CN107025157A publication Critical patent/CN107025157A/en
Application granted granted Critical
Publication of CN107025157B publication Critical patent/CN107025157B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273Test methods

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The present invention is more particularly directed to a kind of algorithm self-checking circuit and method.The algorithm self-checking circuit and method, including random parameter generation module, parameter memory module, self-inspection data memory module, self-inspection process control module and interface module, the interface module is connected with external microcontroller, and parameter memory module and the self-inspection data memory module is all connected to interface module and algorithm unit;The random parameter generation module, parameter memory module, self-inspection data memory module and interface module are all connected to the self-inspection process control module, and the random parameter generation module is also connected with parameter memory module.

Description

A kind of algorithm self-checking circuit and method
Technical field
The present invention relates to technical field of data processing, more particularly to a kind of algorithm self-checking circuit and method.
Background technology
Algorithm represents the policy mechanism for describing to solve the problems, such as with the method for system, is a series of clear fingers solved the problems, such as Order, input that can be to certain specification obtains required output in finite time.With constantly carrying to performance requirement Rise, the complexity of algorithm and diversification are also in rising situation.Therefore, need to carry out self-inspection to detect conditions present before algorithm adaptation Correctness, integrality, security, matching of lower algorithm etc..
Due to various algorithm patterns it is different, it is necessary to parameter it is different, being transplanted to after new environment needs to redeploy, calculate Method self-inspection may also need to redesign because of the change of condition.This adds resistance to the transplanting of algorithm, can reduce development efficiency, It is also possible to algorithm is fallen flat.When polyalgorithm is both needed to carry out self-inspection, it need to respectively be identified and self-inspection, increase System extra resource.
Based on above-mentioned situation, the present invention proposes a kind of algorithm self-checking circuit and method.
The content of the invention
There is provided a kind of simple efficient algorithm self-checking circuit and method for defect of the invention in order to make up prior art.
The present invention is achieved through the following technical solutions:
A kind of algorithm self-checking circuit, it is characterised in that:Including random parameter generation module, parameter memory module, self-inspection data is deposited Module, self-inspection process control module and interface module are stored up, the interface module is connected with external microcontroller, the parameter storage Module and self-inspection data memory module are all connected to interface module and algorithm unit;The random parameter generation module, parameter is deposited Module is stored up, self-inspection data memory module and interface module are all connected to the self-inspection process control module, the random parameter life Also it is connected into module with parameter memory module.
The random parameter generation module, for the random parameter needed for generating algorithm unit self-inspection, and by generation with Machine parameter feeding parameter memory module is stored;
The parameter memory module, outside microcontroller is sent into for storing random parameter, and by random parameter by interface module Device carries out random parameter verification;The preset parameter sent by external microcontroller is stored simultaneously, and calculation is sent into together with random parameter Method unit;
The self-inspection data memory module, the self-detection result data after self-inspection is calculated and self-inspection are completed for storing through algorithm unit Complement mark, and be read out by external microcontroller by interface unit;
The self-inspection process control module is used to realize algorithm self-inspection Row control;The algorithm self-inspection Row control includes random The control of generation with the storage of parameter, notice external microcontroller carry out random parameter reading and start to receive the control of preset parameter System, algorithm unit read random parameter and preset parameter, proceed by control, the arithmetic result returning to external micro-control of algorithm self-inspection The control and the selection encoded control of multiple algorithm units for treating self-inspection of device processed.
The interface module is used to connect external microcontroller, realizes the selection decoding of polyalgorithm unit, and provides ginseng Number memory module read write command and address information;
The external microcontroller is used to provide algorithm self-inspection initial signal, and random parameter is verified, and to algorithm self-inspection Result data is judged;
The algorithm unit is some or certain the several algoritic modules for treating self-inspection.
The self checking method of the algorithm self-checking circuit, it is characterised in that comprise the following steps:
(1)Receive after external microcontroller initial signal, the random parameter needed for random parameter generation module generating algorithm is deposited Enter parameter memory module;
(2)Random parameter reads in external microcontroller through interface module and carries out random parameter verification;
(3)External microcontroller sends preset parameter to parameter memory module;
(4)Each algorithm unit reads corresponding preset parameter and algorithm is configured, and calculating is obtained into algorithm self-detection result data Self-inspection data memory module is stored in algorithm self-inspection complement mark;
(5)External microcontroller reads algorithm self-detection result data and carries out self-detection result judgement, completes algorithm process of self-test.
The beneficial effects of the invention are as follows:The algorithm self-checking circuit and method, can be to algorithm parameter and algorithm self-inspection data Enter line access, facilitate external equipment to read self-detection result and verified, reduce the time in algorithm migration process and resource Expense, improves development efficiency;, can be to polyalgorithm using selection decoding architecture by using interface module output result Unit carries out self-inspection in order, with certain versatility.
Brief description of the drawings
Accompanying drawing 1 is inventive algorithm self-checking circuit structural representation.
Embodiment
In order that technical problems, technical solutions and advantages to be solved are more clearly understood, tie below Drawings and examples are closed, the present invention will be described in detail.It should be noted that specific embodiment described herein is only used To explain the present invention, it is not intended to limit the present invention.
The algorithm self-checking circuit, including random parameter generation module, parameter memory module, self-inspection data memory module, from Examine process control module and interface module, the interface module is connected with external microcontroller, the parameter memory module and from Inspection data memory module is all connected to interface module and algorithm unit;The random parameter generation module, parameter memory module, from Inspection data memory module and interface module are all connected to the self-inspection process control module, the random parameter generation module also with Parameter memory module is connected.
The random parameter generation module, for the random parameter needed for generating algorithm unit self-inspection, and by generation with Machine parameter feeding parameter memory module is stored;
The parameter memory module, outside microcontroller is sent into for storing random parameter, and by random parameter by interface module Device carries out random parameter verification;The preset parameter sent by external microcontroller is stored simultaneously, and calculation is sent into together with random parameter Method unit;
The self-inspection data memory module, the self-detection result data after self-inspection is calculated and self-inspection are completed for storing through algorithm unit Complement mark, and be read out by external microcontroller by interface unit;
The self-inspection process control module is used to realize algorithm self-inspection Row control;The algorithm self-inspection Row control includes random The control of generation with the storage of parameter, notice external microcontroller carry out random parameter reading and start to receive the control of preset parameter System, algorithm unit read random parameter and preset parameter, proceed by control, the arithmetic result returning to external micro-control of algorithm self-inspection The control and the selection encoded control of multiple algorithm units for treating self-inspection of device processed.
The interface module is used to connect external microcontroller, realizes the selection decoding of polyalgorithm unit, and provides ginseng Number memory module read write command and address information;
The external microcontroller is used to provide algorithm self-inspection initial signal, and random parameter is verified, and to algorithm self-inspection Result data is judged;
The algorithm unit is some or certain the several algoritic modules for treating self-inspection.
The self checking method of the algorithm self-checking circuit, it is characterised in that comprise the following steps:
(1)Receive after external microcontroller initial signal, the random parameter needed for random parameter generation module generating algorithm is deposited Enter parameter memory module;
(2)Random parameter reads in external microcontroller through interface module and carries out random parameter verification;
(3)External microcontroller sends preset parameter to parameter memory module;
(4)Each algorithm unit reads corresponding preset parameter and algorithm is configured, and calculating is obtained into algorithm self-detection result data Self-inspection data memory module is stored in algorithm self-inspection complement mark;
(5)External microcontroller reads algorithm self-detection result data and carries out self-detection result judgement, completes algorithm process of self-test.

Claims (4)

1. a kind of algorithm self-checking circuit, it is characterised in that:Including random parameter generation module, parameter memory module, self-inspection data Memory module, self-inspection process control module and interface module, the interface module are connected with external microcontroller, and the parameter is deposited Storage module and self-inspection data memory module are all connected to interface module and algorithm unit;The random parameter generation module, parameter Memory module, self-inspection data memory module and interface module are all connected to the self-inspection process control module, the random parameter Generation module is also connected with parameter memory module.
2. algorithm self-checking circuit according to claim 1, it is characterised in that:The random parameter generation module, for giving birth to Random parameter into needed for algorithm unit self-inspection, and the random parameter feeding parameter memory module of generation is stored;
The parameter memory module, outside microcontroller is sent into for storing random parameter, and by random parameter by interface module Device carries out random parameter verification;The preset parameter sent by external microcontroller is stored simultaneously, and calculation is sent into together with random parameter Method unit;
The self-inspection data memory module, the self-detection result data after self-inspection is calculated and self-inspection are completed for storing through algorithm unit Complement mark, and be read out by external microcontroller by interface unit;
The self-inspection process control module is used to realize algorithm self-inspection Row control;
The interface module is used to connect external microcontroller, realizes that the selection of polyalgorithm unit is decoded, and provides parameter and deposits Store up module read write command and address information;
The external microcontroller is used to provide algorithm self-inspection initial signal, and random parameter is verified, and to algorithm self-inspection Result data is judged;
The algorithm unit is some or certain the several algoritic modules for treating self-inspection.
3. algorithm self-checking circuit according to claim 2, it is characterised in that:The algorithm self-inspection Row control includes random The control of generation with the storage of parameter, notice external microcontroller carry out random parameter reading and start to receive the control of preset parameter System, algorithm unit read random parameter and preset parameter, proceed by control, the arithmetic result returning to external micro-control of algorithm self-inspection The control and the selection encoded control of multiple algorithm units for treating self-inspection of device processed.
4. the self checking method of the algorithm self-checking circuit according to claim 1-3 any one, it is characterised in that including following Step:
(1)Receive after external microcontroller initial signal, the random parameter needed for random parameter generation module generating algorithm is deposited Enter parameter memory module;
(2)Random parameter reads in external microcontroller through interface module and carries out random parameter verification;
(3)External microcontroller sends preset parameter to parameter memory module;
(4)Each algorithm unit reads corresponding preset parameter and algorithm is configured, and calculating is obtained into algorithm self-detection result data Self-inspection data memory module is stored in algorithm self-inspection complement mark;
(5)External microcontroller reads algorithm self-detection result data and carries out self-detection result judgement, completes algorithm process of self-test.
CN201710267111.2A 2017-04-21 2017-04-21 A kind of algorithm self-checking circuit and method Active CN107025157B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710267111.2A CN107025157B (en) 2017-04-21 2017-04-21 A kind of algorithm self-checking circuit and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710267111.2A CN107025157B (en) 2017-04-21 2017-04-21 A kind of algorithm self-checking circuit and method

Publications (2)

Publication Number Publication Date
CN107025157A true CN107025157A (en) 2017-08-08
CN107025157B CN107025157B (en) 2019-08-02

Family

ID=59527593

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710267111.2A Active CN107025157B (en) 2017-04-21 2017-04-21 A kind of algorithm self-checking circuit and method

Country Status (1)

Country Link
CN (1) CN107025157B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11625820B2 (en) * 2020-05-28 2023-04-11 Applied Materials Israel Ltd. Evaluating an inspection algorithm for inspecting a semiconductor specimen

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102110053A (en) * 2011-03-18 2011-06-29 广东欧珀移动通信有限公司 Random testing method based on Android
JP2016208309A (en) * 2015-04-23 2016-12-08 三菱電機株式会社 Error correction decoding device, reception device and error correction decoding method
CN106385343A (en) * 2016-09-05 2017-02-08 Tcl集团股份有限公司 Method and device for monitoring client in distributed system, and distributed system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102110053A (en) * 2011-03-18 2011-06-29 广东欧珀移动通信有限公司 Random testing method based on Android
CN102110053B (en) * 2011-03-18 2013-09-18 广东欧珀移动通信有限公司 Random testing method based on Android
JP2016208309A (en) * 2015-04-23 2016-12-08 三菱電機株式会社 Error correction decoding device, reception device and error correction decoding method
CN106385343A (en) * 2016-09-05 2017-02-08 Tcl集团股份有限公司 Method and device for monitoring client in distributed system, and distributed system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11625820B2 (en) * 2020-05-28 2023-04-11 Applied Materials Israel Ltd. Evaluating an inspection algorithm for inspecting a semiconductor specimen

Also Published As

Publication number Publication date
CN107025157B (en) 2019-08-02

Similar Documents

Publication Publication Date Title
CN111553473B (en) Data redundancy method and neural network processor for executing the same
CN107943609B (en) Memory module, memory controller and system and corresponding operating method thereof
KR101969008B1 (en) Techniques for handling errors in persistent memory
KR101767018B1 (en) Error correction in non_volatile memory
CN106663472A (en) Recovery algorithm in non-volatile memory
CN103761988B (en) Solid state hard disc and data movement method
US8862953B2 (en) Memory testing with selective use of an error correction code decoder
US10698765B2 (en) Techniques to recover data in a network storage system
CN106445843A (en) Correlating physical page addresses for soft decision decoding
CN103077095B (en) Error correction method and device for stored data and computer system
CN111427794A (en) Method, system and medium for accelerating simulation of storage component netlist
CN106910528A (en) A kind of optimization method and device of solid state hard disc data routing inspection
US20160117221A1 (en) Error detection and correction utilizing locally stored parity information
CN104658609B (en) The method and system that error correcting code for storage system is distributed
CN115552422A (en) Memory fail mapping for accelerated neural networks
CN114546510B (en) Verification method and device for suspend function, electronic equipment and storage medium
CN106024066A (en) SRAM detection method and system
US20110004817A1 (en) Crc management method performed in sata interface and data storage device using crc management method
CN107025157A (en) A kind of algorithm self-checking circuit and method
CN103838638B (en) Calibration method and device for FPGA plug-in storage
CN101853198B (en) Detection method, equipment and system of address bus
CN105095011B (en) Data processing method, memorizer control circuit unit and memory storage apparatus
CN104461798A (en) Random number validation method for processor arithmetic logic unit instruction
CN106815153A (en) A kind of method for secure storing, device and system
CN105354107A (en) Data transmission method and system for NOR Flash

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right

Effective date of registration: 20190708

Address after: No. 1036, Shandong high tech Zone wave road, Ji'nan, Shandong

Applicant after: INSPUR GROUP Co.,Ltd.

Address before: 250100 First Floor of R&D Building 2877 Kehang Road, Sun Village Town, Jinan High-tech Zone, Shandong Province

Applicant before: JINAN INSPUR HIGH-TECH TECHNOLOGY DEVELOPMENT Co.,Ltd.

TA01 Transfer of patent application right
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20230414

Address after: 250000 building S02, No. 1036, Langchao Road, high tech Zone, Jinan City, Shandong Province

Patentee after: Shandong Inspur Scientific Research Institute Co.,Ltd.

Address before: No. 1036, Shandong high tech Zone wave road, Ji'nan, Shandong

Patentee before: INSPUR GROUP Co.,Ltd.

TR01 Transfer of patent right