CN107017016A - A kind of memory refresh control method and device of anti-sequential wing passage attack - Google Patents
A kind of memory refresh control method and device of anti-sequential wing passage attack Download PDFInfo
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- CN107017016A CN107017016A CN201710202202.8A CN201710202202A CN107017016A CN 107017016 A CN107017016 A CN 107017016A CN 201710202202 A CN201710202202 A CN 201710202202A CN 107017016 A CN107017016 A CN 107017016A
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- Prior art keywords
- refresh
- random
- memory
- sequential
- refresh address
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/55—Detecting local intrusion or implementing counter-measures
- G06F21/556—Detecting local intrusion or implementing counter-measures involving covert channels, i.e. data leakage between processes
Abstract
The present invention proposes a kind of memory refresh control method and device of anti-sequential wing passage attack, it is related to computer storage security technology area, this method, which includes setting, refreshes interference mechanism, is provided with interference range for M milliseconds, and the refreshing interference mechanism will be in moment tnWhen the DRAM in initial refresh operation RFnRandomly shift to an earlier date or retardation time m0, so that the initial refresh operation RFnDelivery time be tn±m0,m0≤M.The present invention simply carries out original refresh operation random; total refreshing number is not reduced; hardly have an impact to performance of memory system, while the request deadline sequence similarity after interference can be reduced into less than 2%, be effectively protected the sequential channel of shared drive controller.
Description
Technical field
The present invention relates to computer storage security technology area, more particularly to a kind of internal memory of anti-sequential wing passage attack
Refresh control method and device.
Background technology
In computer safety field, private communication channel refers to create the interprocess communication not allowed by computer security strategy
Computer security attack, the concept of private communication channel is initially to be proposed by Lampson in 1973, its hidden letter provided
Road is defined as：It is not to be designed or be not intended to the communication channel for transmitting information.Follow-up research by private communication channel again
It is divided into two types：Private communication channel and sequential private communication channel are stored, is referred to as private communication channel, wherein sequential private communication channel corresponds to
" private communication channel " signified Lampson.Disclosed in channel, significant information has acted only as the carrier of secret information, secret
Confidential information is transmitted by it, is potential private communication channel problem in shared drive system as described in Figure 1.Two safety
Domain (SD, Security Domain) SD 0 and SD 1 is separately operable on Core 0 and Core 1, shared drive resource.SD 0
Want information 10010110 snugly is sent into SD 1, it is that transmission is believed that SD0, which arranges oneself to send a large amount of intensive access requests,
Breath 1, is otherwise 0, at the same time, SD1 constantly counts the access request quantity oneself completed in different time sections, is inferred with this
SD0 access request closeness, so as to infer the information that other side is sending.
In cryptography, bypass attack refers to analyzing by the physics analysis to system and implementation, Er Feimi
Code credit analysis or Brute Force, to attempt the behavior of decryption system.The power consumption of cryptographic system, electromagnetic wave are let out
The information such as dew, time difference are likely to provide to cracking the helpful information of system.There are some bypass attacks to need completely
The internal implementation of understanding system, and some other means are also likely to be effective, such as power analysis to a black box.
Most of bypass attack is all based on statistical attack.
In April, 2005, D.J.Bernstein discloses a kind of caching timing attacks method, and he has cracked a loading with this
The client server of OpenSSL AES encryption systems, in order that all timing informations of the server publishes, attack algorithm is used
200,000,000 a plurality of garbled plain codes.For needing the internet of multiple route jump, such attack method is obvious not
Practicality, this attack of Bruce Schneier is called " good timing attacks method ", and 2010, Eran Tromer were ground with two other
The person of studying carefully has delivered a paper, illustrates several caching timing attacks methods for AES, in shown in Fig. 2 being shared drive system
Bypass channel problems that may be present, the program run on Core 0 can be influenceed by operation program on Core 1, bypass
Attack, i.e. program in Core 0 by analysis and is inferred by the timing information of self-operating, so as to obtain other side such as
The key messages such as key.
As modem computer systems are continued to develop towards the trend of resource-sharing, its sequential channel (Timing being subjected to
Channel) threaten also increasing,, can be between the different user of shared drive resource or service in the service such as cloud computing
Sequential channel (private communication channel, the Covert Channel) information produced using the characteristic of resource-sharing is gone to guess, sounds out, extracts
The private information of other users, equally, if running malicious application under unknown situation, may suffer from bypass attack
(Side Channel Attack) is so that information leakage.
Prior art basic thought is all by bandwidth partition, timesharing memory access, so as to ensure under different application scene, journey
The certainty of sequence memory access latency, eliminates the interference between resource-sharing program as far as possible.Prior art scheme mainly has bandwidth at present
Divide (Temporal Partitioning, TP) and RSVP (Bandwidth Reservation, BR).
It is several prior arts below, it is as follows：
TP technologies：Original memory sharing mechanism is broken, establishes a kind of set time response and execution is trusted each other
Thread request mechanism, as shown in figure 3, the program in identical SD (security domain) is trusted each other, each SD journey
Sequence can only be performed in the timeslice for distributing to oneself, and the time distribution between difference SD is impartial, but existed simultaneously and lacked
Point：1) due to ensure not influence each other between different SD, at each SD timeslice end, it is required for reserved a period of time
(dead time) completes the request in being carrying out and prevents to send new memory request to ensure not interfering with the next time
The program of fragment is performed, and Turn recommendation is 96ns, and corresponding dead time are then 65ns, it is seen then that dead time when
Between expense be sizable；2) each SD process needs the time waited to be (N-1) * Tturn, as number of processes increases, etc.
Treat the time also can linear increase, this can undoubtedly be impacted to program feature, to the performance impact of memory system 300% with
On.
BR technologies：As shown in figure 4, memory bandwidth is divided into N number of thread provides service, within the period in Q cycle,
The time of each thread distribution is impartial., it is necessary to count the time loss of its respective thread in actual moving process, if reached
To apportioning cost Q/N, then the next period is waited, if because request infrequently causes not reaching Q/N, insertion dummy operations are mixed
Confuse interference sequential channel, but there is shortcoming simultaneously：1) ensure bandwidth equalization by coarseness to protect the side of sequential channel
Case, security is relatively low with respect to TP technologies, under extreme case, is due to frequently that can not insert dummy operations not having protection in request
Effect；2) to the performance impact of memory system more than more than 150%.
For the guard method of main storage sequential covert channel or bypass attack, achievement in research both domestic and external is less.It is existing
Some achievements in research are primarily present problems with：First, protection expense is huge, and wherein most method to chip user by entering
The limitation of line storage space distribution, isolates potential danger user, therefore cause very big chip and processor resource to waste；The
Two, the method for not using strict physical to isolate can also carry out the strict distribution of use time to the user program of shared memory,
Substantial amounts of bandwidth of memory is caused to waste, the service quality that reduction computer is provided user.2 points of the above directly results in existing
Achievement need by putting into substantial amounts of hardware resource to while ensureing user security and performance requirement.
The content of the invention
In view of the shortcomings of the prior art, the present invention propose a kind of anti-sequential wing passage attack memory refresh control method and
Device.
A kind of memory refresh control method of anti-sequential wing passage attack of present invention proposition, the sequential channel based on DRAM,
Including：
Set and refresh interference mechanism, be provided with interference range for M milliseconds, the refreshing interference mechanism will be in moment tnWhen
The DRAM in initial refresh operation RFnRandomly shift to an earlier date or retardation time m0, so that the initial refresh operation RFnHair
Send is t constantlyn±m0,m0≤M。
Random refresh address and refresh operation order are produced by pseudo random number generative circuit.
The pseudo random number generative circuit is random refresh address maker.
The random refresh address maker is after the Bin addresses of generation N-bit, and Memory Controller Hub is to correspondence memory list
Member carries out refresh operation, meanwhile, the random refresh address maker waits tRFC by counter and prevents to generate new brush
New address, after the tRFC times terminate, the random refresh address maker generates random refresh command and sends interval H,
After the transmission interval H terminates, the random refresh address maker restarts and generates new refresh address.
The present invention also proposes a kind of memory refresh control device of anti-sequential wing passage attack, the sequential letter based on DRAM
Road, including：
Random refresh control circuit, interference mechanism is refreshed for setting, and it is M milliseconds, the brush to be provided with interference range
New interference mechanism will be in moment tnWhen the DRAM in initial refresh operation RFnRandomly shift to an earlier date or retardation time m0, so that institute
State initial refresh operation RFnDelivery time be tn±m0,m0≤M。
Random refresh address and refresh operation order are produced by pseudo random number generative circuit.
The pseudo random number generative circuit is random refresh address maker.
The random refresh address maker is after the Bin addresses of generation N-bit, and Memory Controller Hub is to correspondence memory list
Member carries out refresh operation, meanwhile, the random refresh address maker waits tRFC by counter and prevents to generate new brush
New address, after the tRFC times terminate, the random refresh address maker generates random refresh command and sends interval H,
After the transmission interval H terminates, the random refresh address maker restarts and generates new refresh address.
From above scheme, the advantage of the invention is that：
The present invention simply carries out original refresh operation at random, total refreshing number not being reduced, to memory system
Can hardly have an impact, while the request deadline sequence similarity after interference can be reduced into less than 2%, effectively
Protect the sequential channel of shared drive controller.
Brief description of the drawings
Fig. 1 is the private communication channel figure in shared drive；
Fig. 2 is the bypass channel mapping in shared drive；
Fig. 3 is Temporal Partitioning (time division) figure；
Fig. 4 is Bandwidth Reservation (RSVP) figure；
Fig. 5 is random refreshing interference method schematic diagram；
Fig. 6 is internal memory Bin address generator figures；
Fig. 7 is random flush mechanism generator figure.
Embodiment
Inventor has found performance of the prior art to memory system when carrying out the research of dram controller sequential channel safety
Influence can reach more than 150%, and this defect is due to draw to ensure the uniformity of different application memory access timing information
Caused by the extra time fragment entered (spurious requests in dead time and BR in such as TP), inventor passes through to be protected to DRAM
The research for holding Annual distribution characteristic finds that more than 99.9% DRAM internal storage location retention times can reach more than 10s, and
The refresh interval 64ms standards for the fixation that JEDEC is provided are to be formulated based on worst retention time distribution unit, in DRAM
Inevitable refresh operation is a kind of natural noise source, and in the implementation procedure of refresh operation, Memory Controller Hub can block
All memory requests, so as to produce sequential interference, therefore propose effectively and almost not appoint using DRAM refresh operation generation
The sequential noise of what expense protects internal memory sequential channel.
Current most of DRAM flush mechanisms are to fix to refresh once every 64ms, and fine granularity is researched and proposed in the recent period
Refresh (FGR, Fine-Grained Refresh) to reduce refresh overhead, FGR passes through the row unit for the different retention times
The different refresh interval times are set, rather than using the 64ms under worst condition, such scheme has also been used as part
JEDEC DDR4 standards and HMC specifications.
In FGR internal memories, Memory Controller Hub can't carry out all Bank the refresh operation of fixed frequency, but can be with
Different internal memory Bin (partial memory row row set) are pre-defined, each Bin can use its corresponding refreshing frequency
Each refreshed, therefore according to DRAM protocol specifications, refresh interval parameter tREFI (Refresh Interval), refreshing grain
Degree and refresh address have been owned by the characteristic that can be configured.
To sum up, by redesigning flush mechanism, the fixed refresh command sent is subjected to " randomization ", sequential is introduced and makes an uproar
Sound, internal memory sequential channel can be protected in the case where almost no expense does not influence systematic function, as shown in figure 5, right
There is the memory chip of 512K rows in one, to ensure internal memory refresh all one in 64ms in the case where refreshing a line every time
It is secondary, then to be accomplished by sending a refresh command every 64/512K ms, altogether the refresh command of 512K fixation, if we
The refreshing of original fixation is upset into random transmission in certain limit (it is assumed that the range size is M, M=32ms in Fig. 5), will
Form a natural random noise source, such as under original flush mechanism, refresh operation RFnCan be in moment tnSend, and refresh dry
Disturbing mechanism then randomly can shift to an earlier date this refresh operation or postpone a period of time m0, now RFnDelivery time be tn±m0,m0
≤ M, so the refresh operation time continuous twice in worst case to same memory line is (64+2*M) ms, and DRAM guarantor
Holding Annual distribution characteristic can ensure in the case of M chooses suitably, and any shadow is hardly had to the data stored in DRAM
Ring.
It is below the embodiment of the present invention, it is as follows：
In order to which by refresh operation randomization, Memory Controller Hub needs to introduce stochastic source generation logic.There are various ways can be with
Using the random number generator on piece, the Intel processors of such as big absolutely logarithm have the digital random numeral hair for encryption
Raw device (Digital Random Number Generator, DRNG), and built-in self-test (Built in Self Test,
BIST) made in circuit by using linear feedback shift register (Linear Feedback Shift Register, LFSR)
The life in circuit testing procedures for automatic test vector generator (Automatic Test Pattern Generator, ATPG)
Into test vector.Because the ATPG in Memory Controller Hub is only used in off-line test circuit, therefore its circuit structure can be by
Random flush mechanism is completed for being multiplexed.
The random refresh control circuit can be used to produce random brush using the pseudo random number generative circuit of any low overhead
New address and refresh command, are illustrated in figure 6 the random refresh address maker example based on Tausworthe, for an appearance
Measure as 4GB, comprising 1K refreshing Bin, and the random address that each Bin is included in the DRAM of 1K memory line unit, Fig. 6 is sent out
Raw device within (32+M) ms periods by 1K memory line Bin address of refreshing in need generate and refresh at random, it is ensured that
The brush machine row of refresh command.
It is Bin of the address generator in the random refresh address maker structure chart 7 of N-bit in generation N-bit shown in Fig. 7
After address, Memory Controller Hub carries out refresh operation to correspondence memory unit, meanwhile, in order to ensure that current refresh operation has been performed
Into the random refresh address maker can wait tRFC (required for a refresh operation by a simple counter
Time) and prevent to generate new refresh address, after the tRFC times terminate, the random refresh address maker can generate one
Individual random refresh command sends interval H, and (i.e. tREFI, scope is 0~2n*Q main memory cycle, and Q is the minimum of a non-zero
TREFI values), after transmission interval H terminates, the random refresh address maker can just restart and generate new refreshing
Address.
By random number generation circuit on piece, the refresh controller in the present invention will give memory cell refresh interval
Under constraint (such as JEDEC refreshes standard 64ms), using the fixation at random refresh command interval, rather than conventional dynamic memory
Time refresh interval, launches refresh command so that dynamic memory is not violating number to random memory block address space
It is the random parameter that daily refresh operation introduces two, so as to the memory access sequential of user on the premise of being constrained according to the retention time
Random disturbances that are lasting, can not being cracked in the short time are produced, main storage sequential channel, covert channel or side is embodied in
Path channels introduce ambient noise signal so that attacker can not observe from the sequential channel, recover equally to share the memory
User's memory access information of passage, also causes multidigit attacker from being that sequential covert channel is mutually transmitted correctly by memory access interference
Signal, so as to block memory covert channel with potential safety hazard and sequential bypass (Timing side-channel), protect
Card shares the information security of the computer user of the storage channel.
Claims (8)
1. a kind of memory refresh control method of anti-sequential wing passage attack, the sequential channel based on DRAM, it is characterised in that bag
Include：
Set and refresh interference mechanism, be provided with interference range for M milliseconds, the refreshing interference mechanism will be in moment tnWhen institute
State initial refresh operation RF in DRAMnRandomly shift to an earlier date or retardation time m0, so that the initial refresh operation RFnTransmission when
Carve as tn±m0,m0≤M。
2. the memory refresh control method of anti-sequential wing passage attack as claimed in claim 1, it is characterised in that by puppet with
Machine number generative circuit produces random refresh address and refresh operation order.
3. the memory refresh control method of anti-sequential wing passage attack as claimed in claim 2, it is characterised in that it is described it is pseudo- with
Machine number generative circuit is random refresh address maker.
4. the memory refresh control method of anti-sequential wing passage attack as claimed in claim 3, it is characterised in that described random
Refresh address maker is after the Bin addresses of generation N-bit, and Memory Controller Hub carries out refresh operation to correspondence memory unit,
Meanwhile, the random refresh address maker waits tRFC by counter and prevents to generate new refresh address, as tRFC
Between terminate after, the random refresh address maker generates random refresh command and sends interval H, and interval H is sent when described
After end, the random refresh address maker restarts and generates new refresh address.
5. a kind of memory refresh control device of anti-sequential wing passage attack, the sequential channel based on DRAM, it is characterised in that bag
Include：
Random refresh control circuit, interference mechanism is refreshed for setting, and is provided with interference range for M milliseconds, described to refresh dry
The mechanism of disturbing will be in moment tnWhen the DRAM in initial refresh operation RFnRandomly shift to an earlier date or retardation time m0, so that described first
Beginning refresh operation RFnDelivery time be tn±m0,m0≤M。
6. the memory refresh control device of anti-sequential wing passage attack as claimed in claim 5, it is characterised in that by puppet with
Machine number generative circuit produces random refresh address and refresh operation order.
7. the memory refresh control device of anti-sequential wing passage attack as claimed in claim 6, it is characterised in that it is described it is pseudo- with
Machine number generative circuit is random refresh address maker.
8. the memory refresh control device of anti-sequential wing passage attack as claimed in claim 7, it is characterised in that described random
Refresh address maker is after the Bin addresses of generation N-bit, and Memory Controller Hub carries out refresh operation to correspondence memory unit,
Meanwhile, the random refresh address maker waits tRFC by counter and prevents to generate new refresh address, as tRFC
Between terminate after, the random refresh address maker generates random refresh command and sends interval H, and interval H is sent when described
After end, the random refresh address maker restarts and generates new refresh address.
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| CN201710202202.8A CN107017016A (en) | 2017-03-30 | 2017-03-30 | A kind of memory refresh control method and device of anti-sequential wing passage attack |
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| CN201710202202.8A CN107017016A (en) | 2017-03-30 | 2017-03-30 | A kind of memory refresh control method and device of anti-sequential wing passage attack |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108650075A (en) * | 2018-05-11 | 2018-10-12 | 中国科学院信息工程研究所 | A kind of quick encryption implementation methods of soft or hard combination AES and system of preventing side-channel attack |
| CN111158585A (en) * | 2019-11-27 | 2020-05-15 | 核芯互联科技(青岛)有限公司 | Memory controller refreshing optimization method, device, equipment and storage medium |
| US10776079B2 (en) | 2018-05-31 | 2020-09-15 | Winbond Electronics Corp. | True random number generation device and generation method thereof |
| WO2022077971A1 (en) * | 2020-10-16 | 2022-04-21 | 长鑫存储技术有限公司 | Memory test method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108650075A (en) * | 2018-05-11 | 2018-10-12 | 中国科学院信息工程研究所 | A kind of quick encryption implementation methods of soft or hard combination AES and system of preventing side-channel attack |
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| US11599646B2 (en) | 2020-10-16 | 2023-03-07 | Changxin Memory Technologies, Inc. | Memory test method |
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Application publication date: 20170804 |