CN107015840B - Quick execution method and quick execution system of resolver - Google Patents
Quick execution method and quick execution system of resolver Download PDFInfo
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- CN107015840B CN107015840B CN201710161150.4A CN201710161150A CN107015840B CN 107015840 B CN107015840 B CN 107015840B CN 201710161150 A CN201710161150 A CN 201710161150A CN 107015840 B CN107015840 B CN 107015840B
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F8/40—Transformation of program code
- G06F8/41—Compilation
- G06F8/42—Syntactic analysis
- G06F8/427—Parsing
Abstract
The invention discloses a quick execution method of an analyzer, which comprises the steps of firstly obtaining an instruction file, then constructing an instruction array, reading the instruction file, coding according to an instruction type, associating with a precompiled instruction execution function, and dynamically creating the instruction array according to the instruction number; and scheduling the execution instruction array in the operation process, starting from 0 to execute according to the sequence of increasing the array subscript, modifying the currently executed array subscript into the JUMP destination index recorded by the JUMP and BREAK instruction when the JUMP and BREAK instruction is executed, and then sequentially executing the corresponding instruction starting from the new subscript. The invention also discloses a quick execution system of the resolver, which comprises an instruction acquisition module, an instruction function module, an instruction construction module and an instruction scheduling module. The technical scheme can improve the execution efficiency of the parser, simultaneously support the flow jump statements of the ST statements and the variable argument instructions, and ensure the functional integrity of the ST language supported by the parser.
Description
Technical Field
The invention belongs to the field of computer language compiling and analyzing processing, and particularly relates to a method and a system for quickly executing an analytic instruction.
Background
The IEC61131 standard can improve the openness, the standard and the uniformity of an industrial control system and has already gained acceptance in the development of the industrial control system. The structured text realizes the logic of the program by a code of a plain text, can realize a complex control algorithm, and is widely applied.
The method comprises the steps of converting ST codes into intermediate instructions, having the advantages of high flexibility, good cross-platform support, strong portability and the like, but the conventional analysis execution mode is to make switch-case branch judgment according to instruction types and often cannot meet requirements on occasions with high real-time requirements, and also has the defects of insufficient flexibility, incomplete support of ST functions and the like, for example, in order to solve the problem of inconsistent operand numbers of different instructions, UMA is generally simplified, operands are uniformly divided according to global regions, each region has a fixed region size, an actual language has the defects of insufficient flexibility, incomplete support of ST functions and the like, for example, in order to solve the problem of inconsistent operand numbers of different instructions, the operations are uniformly divided into different operand types, the operations of a standard language ST 19, data types are different, and the operation of a standard language is not required to be input into a target file, the execution mode is changed into a target machine code, the execution mode is not good in portability, when a hardware model is changed, a rear-end module of a compiler is required to be newly developed.
Disclosure of Invention
The invention aims to provide a quick execution method and a quick execution system of a parser, which can improve the execution efficiency of the parser, support the flow jump statement of an ST statement and support a variable argument instruction, and ensure the functional integrity of an ST language supported by the parser.
In order to achieve the above purpose, the solution of the invention is:
a quick execution method of a resolver comprises the following steps:
and 3, scheduling the execution instruction array in the operation process, starting from 0 to execute according to the sequence of increasing the array subscript, modifying the currently executed array subscript into the JUMP destination index recorded by the JUMP and BREAK instruction when the JUMP and BREAK instruction is executed, and then sequentially executing the corresponding instruction starting from the new subscript.
In the step 1, the instruction file is composed of a data area, an instruction area and an optional debugging information area, wherein the data area is subdivided into a global data area, a constant data area, a variable holding area and a local variable area, and variable name character strings and associated data area addresses are recorded in the debugging information area.
In step 1, the instruction includes an instruction type with a fixed argument format and argument types with a variable number.
In step 2, the members of the instruction array are a composite structure, and include an instruction execution function pointer, an instruction label, the number of the parameters, the addresses of the parameters in the data area, and the next instruction label to be executed.
The instruction comprises an instruction label, an instruction type code, a parameter number, a parameter address and parameter type information.
In the step 2, the instruction file is transmitted from the client software to the device side through a network or serial port communication transmission mode.
A fast execution system of a parser comprising:
the instruction acquisition module is used for providing a communication transmission function and transmitting an instruction file of the client to a device to be executed;
the instruction function module is a precompiled function library, each instruction corresponds to a function, a function table is formed, a search interface is provided for the instruction construction module to call, and an execution function pointer corresponding to the instruction is obtained;
the instruction construction module is used for reading an instruction file, executing association according to the instruction type code and a function instruction compiled in advance, and dynamically creating an instruction array according to the number of the instructions; and the number of the first and second groups,
and the instruction scheduling module is used for executing the function pointers in the instruction array, dynamically adjusting the currently executed data subscript according to the instruction type and realizing the execution of the jump instruction.
After the scheme is adopted, the analyzer reads the instruction file in the initialization process, and acquires information such as the instruction type, the shape parameter address, the instruction label and the like. Each type of instruction corresponds to 1 compiled task function, and a dynamically distributed instruction array is formed according to information such as an actual instruction type, a form parameter number, an address of a form parameter in a data area and the like. The instruction data comprises corresponding task function pointers, actual form parameter information, instruction labels and the like. And in the periodic operation process, transmitting actual form parameters, executing a function pointer in instruction data, and modifying the currently executed array subscript according to the instruction labels for jump and return instructions. On one hand, the invention improves the execution efficiency, simultaneously supports the execution of the variable parameter instruction and the flow control instruction, and solves the problem that the jump cannot be supported when the linear instruction list structure is executed in sequence. The invention is applied in the application development of industrial control, can obviously improve the execution speed of ST language of 61131 standard, supports jump and flow control instructions, and improves the flexibility and application range of the system.
Drawings
FIG. 1 is a flow chart of the present invention;
FIG. 2 is a diagram of an instruction array architecture of the present invention;
FIG. 3 is a system configuration diagram of the resolver of the present invention.
Detailed Description
The technical scheme of the invention is explained in detail in the following with the accompanying drawings.
As shown in fig. 1, the present invention provides a fast execution method of a parser, including the following steps:
the instruction file comprises a data area, an instruction area and a debugging information area (optional), wherein the data area is subdivided into a global data area, a constant data area, a variable holding area and a local variable area, and variable name character strings and associated data area addresses are recorded in the debugging information area.
And 2, constructing an instruction array. Reading the instruction file, coding according to the instruction type, associating with a precompiled instruction execution function, and dynamically creating an instruction array according to the instruction number. The member of the instruction array is a composite structure body and comprises information such as an instruction execution function pointer, an instruction label, the number of the shape parameters, the address of the shape parameters in the data area, the next instruction label to be executed and the like;
and 3, scheduling and executing the instruction array in the running process. And executing according to the sequence of increasing the array subscripts from 0, modifying the currently executed array subscript into the JUMP destination label recorded by the JUMP and BREAK instruction when the JUMP and BREAK instruction is executed, and then sequentially executing the corresponding instruction starting from the new subscript.
The following describes specific contents of the fast execution method according to the present invention with reference to specific embodiments.
1) Defining instruction format, writing C/C + + implementation function corresponding to each instruction, forming lib library and other modules of the parser to be linked together into executable program. And filling in and forming a corresponding function pointer array according to the instruction type coding sequence number, providing a search interface, and returning a corresponding realization function pointer according to the instruction type.
The fixed-parameter-format instruction type takes a three-address code as a prototype and comprises instructions of binary operation, assignment, JUMP JUMP, BREAK and the like, and the variable-parameter-number instruction comprises a CA LL function call instruction, a logical AND, a logical OR and the like.
2) And acquiring an instruction file, wherein the instruction file consists of a data area, an instruction area and a debugging information area (optional). The data area is subdivided into a global data area, a constant data area, a variable holding area and a local variable area, and variable name character strings and associated data area addresses are recorded in the debugging information area. Each instruction comprises an instruction label, an instruction type code, a parameter number, a parameter address and parameter variable type information. Preferably, the instruction file is transmitted from the client software to the device side through a network or serial port communication transmission mode.
3) An instruction array is constructed. Reading the instruction file, coding according to the instruction type, associating with a precompiled instruction execution function, and dynamically creating an instruction array according to the instruction number. The member of the instruction array is a composite structure body and comprises information such as an instruction execution function pointer, an instruction label, the number of the shape parameters, the address of the shape parameters in the data area, the next instruction label to be executed and the like. Preferably, the instruction data member structure is defined as follows:
dynamically creating an instruction array according to the number of instructions:
StOpCode*OpCode＝new StOpCode[opnum]；
FIG. 2 is an example of an instruction array being built.
4) And scheduling and executing the instruction array in the operation process. Setting the currently executed instruction subscript current _ oplabel equal to 0, starting from 0, executing in the order of increasing array subscript (current _ oplabel + +), when executing the JUMP and BREAK instructions, modifying the currently executed array subscript into the JUMP destination index recorded by the JUMP and BREAK instructions (current _ oplabel equal to next _ label), and then sequentially executing the corresponding instructions starting from the new subscript.
In combination with the above fast execution method, the present invention further provides a fast execution system of the parser, as shown in fig. 3, the system includes an instruction obtaining module, an instruction function module, an instruction constructing module, and an instruction scheduling execution module, which are respectively described below.
The instruction obtaining module is configured to provide a communication transmission function, and transmit an instruction file of the client to a device to be executed, which is an instruction constructing module in this embodiment.
The instruction function module is a function library compiled in advance, each instruction corresponds to a function, a function table is formed, a search interface is provided for the instruction construction module to call, and an execution function pointer corresponding to the instruction is obtained.
The instruction construction module is used for reading the instruction file, executing association according to the instruction type code and the function instruction compiled in advance, and dynamically creating an instruction array according to the instruction number.
And the instruction scheduling module is used for executing the function pointers in the instruction array, dynamically adjusting the currently executed data subscript according to the instruction type and realizing the execution of the jump instruction.
The above embodiments are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modifications made on the basis of the technical scheme according to the technical idea of the present invention fall within the protection scope of the present invention.
Claims (6)
1. A quick execution method of a parser is used for supporting a process jump statement of an ST statement and supporting a variable argument instruction, and ensuring the functional integrity of an ST language supported by the parser; the method is characterized by comprising the following steps:
step 1, acquiring an instruction file;
in the step 1, the instruction file is composed of a data area, an instruction area and an optional debugging information area, wherein the data area is subdivided into a global data area, a constant data area, a variable holding area and a local variable area, and variable name character strings and associated data area addresses are recorded in the debugging information area;
step 2, constructing an instruction array, reading an instruction file, coding according to the instruction type, associating with a pre-compiled instruction execution function, and dynamically creating the instruction array according to the instruction number;
and 3, scheduling the execution instruction array in the operation process, starting from 0 to execute according to the sequence of increasing the array subscript, modifying the currently executed array subscript into the JUMP destination index recorded by the JUMP and BREAK instruction when the JUMP and BREAK instruction is executed, and then sequentially executing the corresponding instruction starting from the new subscript.
2. A method for fast execution of a parser according to claim 1, characterized by: in the step 1, the instruction comprises an instruction type with a fixed parameter format and a variable number of parameter types.
3. A method for fast execution of a parser according to claim 1, characterized by: in step 2, the members of the instruction array are a composite structure, and include an instruction execution function pointer, an instruction label, the number of the parameters, the addresses of the parameters in the data area, and the next instruction label to be executed.
4. A method for fast execution of a parser according to claim 1, characterized by: the instruction comprises an instruction label, an instruction type code, a parameter number, a parameter address and parameter type information.
5. A method for fast execution of a parser according to claim 1, characterized by: in the step 2, the instruction file is transmitted from the client software to the device side through a network or serial port communication transmission mode.
6. A quick execution system of a parser is used for supporting a process jump statement of an ST statement and supporting a variable argument instruction, and ensuring the functional integrity of an ST language supported by the parser; it is characterized by comprising:
the instruction acquisition module is used for providing a communication transmission function and transmitting an instruction file of the client to a device to be executed; the instruction file consists of a data area, an instruction area and an optional debugging information area, wherein the data area is divided into a global data area, a constant data area, a variable holding area and a local variable area, and variable name character strings and associated data area addresses are recorded in the debugging information area;
the instruction function module is a precompiled function library, each instruction corresponds to a function, a function table is formed, a search interface is provided for the instruction construction module to call, and an execution function pointer corresponding to the instruction is obtained;
the instruction construction module is used for reading an instruction file, executing association according to the instruction type code and a function instruction compiled in advance, and dynamically creating an instruction array according to the number of the instructions; and the number of the first and second groups,
and the instruction scheduling module is used for executing the function pointers in the instruction array, dynamically adjusting the currently executed data subscript according to the instruction type and realizing the execution of the jump instruction.
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| CN108804105B (en) * | 2018-04-13 | 2022-02-18 | 南京南瑞继保电气有限公司 | Program organization unit compiling processing method |
| CN108733410B (en) * | 2018-04-13 | 2021-10-01 | 南京南瑞继保电气有限公司 | Instruction optimization method |
| CN109446096B (en) * | 2018-11-06 | 2021-08-24 | 北京知道创宇信息技术股份有限公司 | Intelligent contract debugging method and device and storage medium thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101706734A (en) * | 2009-11-10 | 2010-05-12 | 中国科学院计算技术研究所 | Method and system thereof for translating indirect jump instruction in binary translation |
| CN103761071A (en) * | 2014-01-08 | 2014-04-30 | 东南大学 | PLC instruction coding and identifying system |
| CN104267999A (en) * | 2014-09-26 | 2015-01-07 | 浙江中控技术股份有限公司 | Method and device for compiling control program |
| US9348569B1 (en) * | 2012-09-11 | 2016-05-24 | Emc Corporation | Method and system for a configurable automation framework |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101706734A (en) * | 2009-11-10 | 2010-05-12 | 中国科学院计算技术研究所 | Method and system thereof for translating indirect jump instruction in binary translation |
| US9348569B1 (en) * | 2012-09-11 | 2016-05-24 | Emc Corporation | Method and system for a configurable automation framework |
| CN103761071A (en) * | 2014-01-08 | 2014-04-30 | 东南大学 | PLC instruction coding and identifying system |
| CN104267999A (en) * | 2014-09-26 | 2015-01-07 | 浙江中控技术股份有限公司 | Method and device for compiling control program |
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