CN107014489B - Light multi-parameter sensing CMOS monolithic integrated circuit - Google Patents
Light multi-parameter sensing CMOS monolithic integrated circuit Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J1/00—Photometry, e.g. photographic exposure meter
- G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
- G01J1/44—Electric circuits
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J9/00—Measuring optical phase difference; Determining degree of coherence; Measuring optical wavelength
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J1/00—Photometry, e.g. photographic exposure meter
- G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
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- G01J2001/4446—Type of detector
- G01J2001/446—Photodiode
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Abstract
A light multi-parameter sensing CMOS monolithic integrated circuit comprises a BDJ photoelectric sensing selection unit, a current-voltage linear conversion circuit, a related secondary sampling circuit, a differential amplification output circuit and a mode time sequence control circuit. The optical multi-parameter sensing integrated circuit provided by the invention is integrated with a buried CMOS double PN junction photodiode single chip, can realize real-time monitoring of optical wavelength and light intensity parameters, has the advantages of small error, high precision, wide detection range, small circuit size, low power consumption and the like, and can be widely applied to optical multi-parameter monitoring occasions.
Description
Technical field
The present invention relates to light multi-parameter sensing CMOS monolithic integrated optical circuits.
Background technology
The double PN junction photodiodes of CMOS are buried, are made of the diode of the different depth of two vertical stackings.This device
When the stacked structure of part is caused using silicon materials as optical filter, transmission depth of the light in silicon crystal and wavelength have it is strong according to
When the relation of relying, incident optical power and wavelength are different, the photoelectric current that PN junction is measured also differs.The photoelectric current ratio of two PN junctions with
Wavelength can be used for monochromatic wavelength measurement into good monotonic increase relation, and output current size and incident optical power
It is directly proportional, it can be used for the measurement of intensity of illumination.
At present, the application of photodiode discrete component is ripe, its coherent signal process circuit, which often uses, to be divided
Vertical element is built, the drawback is that circuit is complicated, volume is big, optical parameter to be detected is single, precision is low；Two pole of photoelectricity of parallel-connection structure
Pipe, by setting switch, it can be achieved that parallel-connection structure provides possibility to the conversion of cascaded structure to realize that many reference amounts detect；It is based on
The light multi-parameter sensing circuit of microelectric technique, while circuit volume is substantially reduced, can improve the accuracy of detection of weak signal,
Light multi-parameter sensing system is set to be miniaturizated to possibility.
The content of the invention
The present invention will overcome the disadvantages mentioned above of the prior art, there is provided a kind of smooth multi-parameter sensing CMOS monolithic integrated optical circuits.
Light multi-parameter sensing technology is combined by the present invention with microelectric technique, devises a kind of smooth multi-parameter sensing CMOS
Monolithic integrated optical circuit, the circuit will bury double PN junction photodiode sensing units and signal processing circuit list using CMOS technology
Piece integrates, and by pattern switching, can detect intensity of illumination and optical wavelength at the same time, realizes the miniature of light many reference amounts detecting system
Change, automation.Wherein bury CMOS photodiodes and realize conversion of the optical signal to electric signal, and with burying two pole of CMOS photoelectricity
The integrated each circuit module of pipe exports the voltage signal that the weak current that photodiode responds is converted into easily measuring.
A kind of smooth multi-parameter sensing CMOS monolithic integrated optical circuits of the present invention, by BDJ photoelectric sensings selecting unit 1, electric current
Voltage linear conversion circuit 2, correlation secondary sampling circuit 3, differential amplification output circuit 4, pattern sequential control circuit 5, totally 5
Circuit module forms.
In the BDJ photoelectric sensings selecting unit 1, first input end 11a, the second input terminal 12a respectively with pattern sequential
The first output terminal 51b, the second output terminal 52b of control circuit 5 are connected, output terminal 1b and Current Voltage linear transform circuit 2
Second input terminal 22a is connected；
BDJ photoelectric sensings selecting unit 1 is by shallow PN junction photodiode D1, deep PN junction photodiode D2, NMOS tube N1
And PMOS tube P1 compositions；The shallow PN junction photodiode D1 is connected with the deep PN junction photodiode D2 common cathodes, and
It is and described as the output terminal 1b of the BDJ photoelectric sensings selecting unit 1, the depth PN junction photodiode D2 plus earths
NMOS tube N1 drain electrodes connect the shallow PN junction photodiode D1 anodes, and source electrode is grounded, described in the PMOS tube P1 source electrodes connection
Shallow PN junction photodiode D1 anodes, grounded drain, the NMOS tube N1 grids and the PMOS tube P1 grids are respectively the BDJ
The first input end 11a of photoelectric sensing selecting unit 1 and the second input terminal 12a；
In the Current Voltage linear transform circuit 2, it is the 3rd defeated to connect pattern sequential control circuit 5 by first input end 21a
Outlet 53b, the second input terminal 22a meet the output terminal 1b of BDJ photoelectric sensings selecting unit 1, and output terminal 2b connects correlation secondary sampling
The first input end 31a of circuit 3 and the second input terminal 32a；
Current Voltage linear transform circuit 2 is by NMOS tube N2, N3, N4, N5, N6 and PMOS tube P2, P3, P4, P5 and electricity
Hold C1 compositions；The PMOS tube P2 source electrodes meet power vd D, and grid connects the PMOS tube P3 grids, and drain electrode meets the PMOS tube P4
Source electrode, the PMOS tube P4 grids connect the PMOS tube P5 grids, and drain electrode is connected with NMOS tube N3 drain electrodes, and is used as the electricity
The output terminal 2b of voltage linear conversion circuit 2 is flowed, the NMOS tube N3 grids connect the NMOS tube N4 grids, and source electrode connects described
NMOS tube N5 drains, the NMOS tube N5 source electrodes ground connection, second input of the grid as the Current Voltage linear transform circuit (2)
22a is held, the PMOS tube P3 source electrodes meet power vd D, grid leak short circuit, and drain electrode meets the PMOS tube P5 source electrodes, the PMOS tube P5
Grid leak short circuit, drain electrode connect the NMOS tube N4 drain electrodes, the NMOS tube N4 grid leak short circuits, and source electrode connects the NMOS tube N6 drain electrodes,
The NMOS tube N6 grid leak short circuits, source electrode ground connection, the NMOS tube N2 drain electrodes terminate the Current Voltage line with the capacitance C1 mono-
Property conversion circuit 2 output terminal 2b, NMOS tube N2 drain electrode with the capacitance C1 is another terminates the Current Voltage linear transformation
The input terminal 22a of circuit 2, first input end 21a of the NMOS tube N2 grids as the Current Voltage linear transform circuit 2；
In the correlation secondary sampling circuit 3, first input end 31a and the second input terminal 32a linearly turn with Current Voltage
The output terminal 2b for changing circuit 2 is connected, and the 3rd input terminal 33a is connected with the 3rd output terminal 53b of pattern sequential control circuit 5, the
One output terminal 31b, the second output terminal 32b respectively with 4 first input end 41a of differential amplification output circuit, the second input terminal 42a phases
Even；
Correlation secondary sampling circuit 3 is made of PMOS tube P6, P7, P8 and NMOS tube N7, N8, N9 and capacitance C2, C3；Institute
State PMOS tube P6 source electrodes and meet power vd D, grid is connected with the NMOS tube N7 grids, and draws port as the correlation is secondary and adopt
3rd input terminal 33a of sample circuit 3, NMOS tube N7 source electrodes ground connection, drain electrode connect the PMOS tube P6 drain electrodes, and with it is described
PMOS tube P7 grids are connected with the NMOS tube N9 grids, and the PMOS tube P7 source electrodes connect the NMOS tube N8 drain electrodes, and draw
First input end 31a of the port as the correlation secondary sampling circuit 3, the PMOS tube P7 drain electrodes connect the NMOS tube N8 sources
Pole, and draw first output terminal 31b, the NMOS tube N8 and the PMOS tube of the port as the correlation secondary sampling circuit 3
P8 grids are connected with each other, and are commonly connected to the 3rd input terminal 33a of the correlation secondary sampling circuit 3, the PMOS tube P8 sources
Pole is connected with NMOS tube N9 drain electrodes, and draws second input terminal 32a of the port as the correlation secondary sampling circuit 3, institute
State PMOS tube P8 drain electrodes with the NMOS tube N9 source electrodes to be connected, and draw second of port as the correlation secondary sampling circuit 3
Output terminal 32b, described capacitance C2, C3 one end connect the first output terminal 31b of the correlation secondary sampling circuit 3, the second output respectively
32b is held, capacitance C2, C3 other end is all grounded；
In the differential amplification output circuit 4, first input end 41a, the second input terminal 42a connect correlation secondary sampling respectively
3 first output terminal 31b of circuit, the output terminal that the second output terminal 32b, output terminal OUTPUT are the differential amplification output circuit 4, together
When be also light multi-parameter sensing integrated circuit of the present invention output terminal；
Differential amplification output circuit 4 by NMOS tube N10, N11, N12, N13, N14, N15, N16 and PMOS tube P9, P10,
P11, P12, P13, P14, P15 are formed；The PMOS tube P9 source electrodes meet power vd D, and grid meets the PMOS tube P12 grids, institute
PMOS tube P10 source electrodes are stated to connect the PMOS tube P11 source electrodes and be connected to the PMOS tube P9 drain electrodes, the PMOS tube P10 grids
The NMOS tube N10 grids are connect, the PMOS tube P11 grids connect the NMOS tube N11 grids, and the NMOS tube N10 grids are made
For the first input end 41a of the differential amplification output circuit 4, source electrode connects the NMOS tube N11 source electrodes and is connected to the NMOS
Pipe N12 drains, second input terminal 42a of the NMOS tube N11 grids as the differential amplification output circuit 4, the NMOS tube
N12 source electrodes are grounded, and grid connects the NMOS tube N15 grids, and the PMOS tube P12 source electrodes connect power vd D, grid leak short circuit, grid
The PMOS tube P13 grids are connect, drain electrode connects the PMOS tube P14 source electrodes, and draws port and meet the NMOS tube N10 drain electrodes, institute
State PMOS tube P14 grids and connect the PMOS tube P15 grids, grid leak short circuit, drain electrode meets the NMOS tube N13 drain electrodes, the NMOS
Pipe N13 grid leak short circuits, grid connect the NMOS tube N14 grids, and source electrode connects the NMOS tube N15 drain electrodes, and draws port and meet institute
PMOS tube P10 drain electrodes, the NMOS tube N15 grid leak short circuits are stated, grid connects the NMOS tube N16 grids, and source electrode ground connection is described
PMOS tube P13 source electrodes meet power vd D, and drain electrode connects the PMOS tube P15 source electrodes, and draw port and connect the NMOS tube N11 drain electrodes,
The PMOS tube P15 drain electrodes connect the NMOS tube N14 drain electrodes, and draw output terminal OUTPUT of the port as whole circuit, institute
State NMOS tube N14 source electrodes and connect the NMOS tube N16 drain electrodes, and draw port and connect the PMOS tube P11 drain electrodes, the NMOS tube
N16 source electrodes are grounded；
The first input end Sel of the pattern sequential control circuit 5 is test pattern selection port, the second input terminal CLK
Input clock signal, the first output terminal 51b, the second output terminal 52b connect the first input end of BDJ photoelectric sensings selecting unit 1
11a, the second input terminal 12a, the 3rd output terminal 53b meet the first input end 21a and correlation two of Current Voltage linear transform circuit 2
3rd input terminal 33a of secondary sample circuit 3；
Pattern timing control electricity 5 by PMOS tube P16, P17, P18, P19, P20, P21, P22, P23, P24, P25, P26,
P27 and NMOS tube N17, N18, N19, N20, N21, N22, N23, N24, N25, N26, N27, N28 and capacitance C4, C5, C6, C7
Composition；The PMOS tube P16 source electrodes meet power vd D, and grid connects the NMOS tube N17 grids, and is connected with first input end Sel
And drain as the second output terminal 52b of the pattern sequential control circuit 5, the PMOS tube P16 drain electrodes with the NMOS tube N17
It is connected, and draws first output terminal 51b of the port as the pattern sequential control circuit 5, the NMOS tube N17 source electrodes connects
Ground, the PMOS tube P17 source electrodes meet power vd D, and grid connects the NMOS tube N18 grids, and draws port and connect the second input terminal
CLK, the PMOS tube P17 drain electrode connect the NMOS tube N18 drain electrodes, and draw port and connect PMOS tube P21 grids and described
NMOS tube N19 grids, the NMOS tube N18 source electrodes ground connection, the PMOS tube P18 source electrodes meet power vd D, and grid meets the NMOS
Pipe N20 grids, and connected with PMOS tube P22 drain electrodes and NMOS tube N23 drain electrodes, the PMOS tube P18 drain electrodes meet institute
PMOS tube P19 source electrodes are stated, the PMOS tube P19 grids meet the second input terminal CLK, and drain electrode connects the NMOS tube N19 drain electrodes, and draws
Exit port meets described capacitance C4 one end and the PMOS tube P20 grids and the NMOS tube N22 grids, the NMOS tube N19
Source electrode connects the NMOS tube N20 drain electrodes, the NMOS tube N20 source electrodes ground connection, the capacitance C4 other ends ground connection, the PMOS tube
P20 source electrodes meet power vd D, and grid connects the NMOS tube N22 grids, and drain electrode connects the PMOS tube P21 source electrodes, the PMOS tube
P21 drain electrodes connect NMOS tube N21 drain electrode, and are connected to described capacitance C5 one end and the PMOS tube P22 grids and described
NMOS tube N23 grids, the NMOS tube N21 grids meet the second input terminal CLK, and source electrode connects the NMOS tube N22 drain electrodes, described
NMOS tube N22 source electrodes are grounded, and the capacitance C5 other ends ground connection, the PMOS tube P22 source electrodes meet power vd D, and grid connects described
NMOS tube N23 grids, and the PMOS tube P24 grids and the NMOS tube N26 grids are connected to, the PMOS tube P22 drain electrodes
The NMOS tube N23 drain electrodes are connect, and connect the PMOS tube P26 grids and the NMOS tube N24 grids, the NMOS tube N23
Source electrode is grounded, and the PMOS tube P23 source electrodes meet power vd D, and grid connects the NMOS tube N25 grids, and is connected to the PMOS tube
P27 drains and NMOS tube N28 drain electrodes, and the PMOS tube P23 drain electrodes meet the PMOS tube P24 source electrodes, the PMOS tube P24
Drain electrode connects the NMOS tube N24 drain electrodes, and is connected to described capacitance C6 one end and the PMOS tube P25 grids and the NMOS tube
N27 grids, the NMOS tube N24 source electrodes meet the NMOS tube N25 drain electrodes, the NMOS tube N25 source electrodes ground connection, the capacitance C6
The other end is grounded, and the PMOS tube P25 source electrodes meet power vd D, and grid connects the NMOS tube N27 grids, and drain electrode meets the PMOS
Pipe P26 source electrodes, PMOS tube P26 drain electrode connect the NMOS tube N26 drain electrodes, and draw port be connected to described capacitance C7 one end with
And the PMOS tube P27 grids and the NMOS tube N28 grids, the port is at the same time as the pattern sequential control circuit (5)
3rd output terminal 53b, the NMOS tube N26 source electrodes connect the NMOS tube N27 drain electrodes, and the NMOS tube N27 source electrodes ground connection is described
The capacitance C7 other ends are grounded, and the PMOS tube P27 source electrodes meet power vd D, and grid and drain electrode connect the NMOS tube N28 grids respectively
And drain electrode, the NMOS tube N28 source electrodes ground connection.
It is an advantage of the invention that：Smooth multi-parameter sensing integrated circuit proposed by the present invention, with burying the double PN junction photoelectricity of CMOS
Diode single-chip integration has error small, precision is high, detection range, it can be achieved that the real-time monitoring of optical wavelength and luminous intensity parameter
Width, the advantages such as circuit is small, power consumption is low, can be widely applied to the occasion of light many reference amounts monitoring.
Brief description of the drawings
Fig. 1 is the unit block diagram of structure of the present invention
Fig. 2 is the schematic diagram that the present invention designs
Fig. 3 is the partial enlarged view in the S1 portions of Fig. 2
Fig. 4 is the partial enlarged view in the S2 portions of Fig. 2
Fig. 5 is the partial enlarged view in the S3 portions of Fig. 2
Embodiment
The present invention is further illustrated below in conjunction with the accompanying drawings.
A kind of smooth multi-parameter sensing CMOS monolithic integrated optical circuits of the present invention, including BDJ photoelectric sensings selecting unit 1, electricity
Flow voltage linear conversion circuit 2, correlation secondary sampling circuit 3, differential amplification output circuit 4, pattern sequential control circuit 5 totally 5
A circuit module.
Optical signal, electric signal, BDJ are converted into using diode photoelectric effect by the BDJ photoelectric sensings selecting unit (1)
Operating mode can be selected by control signal, realize photodiode series connection and the mutual conversion of parallel-connection structure；The photoelectricity
Diode D1 and D2 are used to convert optical signals to electric signal, intensity of illumination and output current into strong dependence, light wave
Length is linear with D1, D2 current ratio, and the NMOS tube N1 and PMOS tube P1 form transmission gate, as input terminal 11a, 12a
Respectively high and low level when, transmission gate conducting, the photodiode D1 and D2 is worked at the same time, and BDJ photoelectric sensings selection is single
The output terminal 1b output currents of member 1 the sum of for D1 and D2 electric currents, when input terminal 11a, 12a are respectively low, high level when, transmission gate
Cut-off, only photodiode D2 work, the output terminal 1b of the BDJ photoelectric sensings selecting unit 1 only export the photoelectric current on D2；
2 high sensitivity of Current Voltage linear transform circuit, strong interference immunity, by faint to the second input terminal 22a
The reading of electric current, voltage signal is converted to by current signal；When first input end 21a input high levels, the NMOS tube N2
Conducting, circuit is in reset state, and when first input end 21a input low levels, the NMOS tube N2 cut-offs, circuit passes through institute
Capacitance C1 Integral Transformations are stated into voltage output, wherein, the common source of described PMOS tube P2, P4 and NMOS tube N3, N5 composition is total to
Grid amplifying circuit is as the amplifier in Current Voltage linear transform circuit 5, described PMOS tube P3, P5 and NMOS tube N4, N6
Biasing is provided for cascade amplifying circuit, the Current Voltage linear transform circuit 5 is photoelectricity two by amplifier feedback control loop
Pole pipe provides very low reversed bias voltage to reduce dark current, while the voltage in integration phase photodiode parasitic capacitance is protected
Hold it is constant, ensure that output terminal 2b output integral voltage there is the more preferable linearity；
The correlation secondary sampling circuit 3 is used for the fixed pattern noise for eliminating circuit；The NMOS tube N8 and PMOS tube
P7 forms the first transmission gate, and the NMOS tube N9 and PMOS tube P8 form the second transmission gate, when the 3rd input terminal 33a input signals
For high level when, the first transmission gate conducting, the cut-off of the second transmission gate, the output signal of Current Voltage linear transform circuit 2 is from the
One input terminal 31a is inputted, and is charged to the capacitance C2, and the capacitance C2 both end voltages are reference model voltage, when the 3rd defeated
When to enter to hold 33a input signals be low level, the cut-off of the first transmission gate, the second transmission gate conducting, Current Voltage linear transform circuit 2
Output signal inputted from the second input terminal 32a, and to the capacitance C3 charge, the capacitance C3 both end voltages are photoelectric sensing
Voltage；
It is poor that the differential amplification output circuit 4 is used to two output end voltage signals of correlation secondary sampling circuit 3 make, most
Output eliminates the photoelectric sensing voltage of fixed pattern noise eventually；The differential amplification output circuit 4 uses rail-to-rail structure, when defeated
Enter to hold the input voltage of 41a, 42a 0 to mains voltage variations when, difference can be made, final signal is from output terminal OUTPUT ends
Mouth output；
Two input terminal 11as and 12a, electric current electricity of the pattern sequential control circuit 5 for BDJ photoelectric sensings selecting unit 1
The first input end 21a of linear transform circuit 2 and the 3rd input terminal 33a of correlation secondary sampling circuit 3 is pressed to provide control respectively
Signal processed；The phase inverter that the PMOS tube P16 and NMOS tube N17 is formed is anti-phase by the input signal of first input end Sel
Afterwards to provide voltage to the first output port 51b, and the output voltage of the second output terminal 52b is directly carried by first input end Sel
For described NMOS tube N19, N20, N21, N22 and described PMOS tube P18, P19, P20, P21 and described capacitance C4, C5 are common
The first clock control CMOS registers are formed, the PMOS tube P17 and NMOS tube N18 forms phase inverter, by input clock
After signal inversion signal, the PMOS tube P22 and institute are provided for the first clock control CMOS registers together with original clock signal
The phase inverter for stating NMOS tube N23 compositions is used for the voltage inversion for exporting the first clock control CMOS registers at capacitance C5,
And feed back to the PMOS tube P18 grids and NMOS tube N20 grids and subsequent conditioning circuit in the first clock control CMOS registers, institute
Phase inverter where stating PMOS tube P17 and PMOS tube P22 place phase inverters and the first clock control CMOS registers are common
Form the first T ' triggers, described PMOS tube P23, P24, P25, P26 and described NMOS tube N24, N25, N26, N27 and capacitance
C6, C7 collectively form second clock control CMOS registers, in-phase clock signal and the inverting clock signal difference of the register
It is output voltage signal at the first clock control CMOS register capacitances C5 and the voltage through inverter where PMOS tube P22
The phase inverter that output voltage signal afterwards, the PMOS tube P27 and the NMOS tube N28 are formed is used to control second clock
The voltage inversion that CMOS registers export at capacitance C7, and feed back to the PMOS tube in second clock control CMOS registers
P23 grids and NMOS tube N25 grids, phase inverter and the first clock control CMOS registers are common where the PMOS tube P27
The 2nd T ' triggers are formed, first and second T ' triggers collectively form four-divider, and fractional frequency signal exports at capacitance C7, at the same time
The output terminal is as the 3rd output terminal 53b of the pattern sequential control circuit 5.
Content described in this specification embodiment is only enumerating to the way of realization of inventive concept, protection of the invention
Scope should not be construed as limited to only the concrete form that embodiment is stated, protection scope of the present invention is also and in people in the art
The thinkable equivalent technologies mean of member's design according to the present invention institute.
Claims (1)
1. a kind of smooth multi-parameter sensing CMOS monolithic integrated optical circuits, linear by BDJ photoelectric sensings selecting unit (1), Current Voltage
Conversion circuit (2), correlation secondary sampling circuit (3), differential amplification output circuit (4), pattern sequential control circuit (5)；
In the BDJ photoelectric sensings selecting unit (1), first input end 11a, the second input terminal 12a respectively with pattern sequential control
The first output terminal 51b, the second output terminal 52b of circuit (5) processed are connected, output terminal 1b and Current Voltage linear transform circuit (2)
The second input terminal 22a be connected；
BDJ photoelectric sensings selecting unit (1) by shallow PN junction photodiode D1, deep PN junction photodiode D2, NMOS tube N1 with
And PMOS tube P1 compositions；The shallow PN junction photodiode D1 is connected with the deep PN junction photodiode D2 common cathodes, and
It is described as the output terminal 1b of the BDJ photoelectric sensings selecting unit (1), the depth PN junction photodiode D2 plus earths
NMOS tube N1 drain electrodes connect the shallow PN junction photodiode D1 anodes, and source electrode is grounded, described in the PMOS tube P1 source electrodes connection
Shallow PN junction photodiode D1 anodes, grounded drain, the NMOS tube N1 grids and the PMOS tube P1 grids are respectively the BDJ
The first input end 11a of photoelectric sensing selecting unit (1) and the second input terminal 12a；
In the Current Voltage linear transform circuit (2), it is the 3rd defeated to connect pattern sequential control circuit (5) by first input end 21a
Outlet 53b, the second input terminal 22a meet the output terminal 1b of BDJ photoelectric sensings selecting unit (1), and output terminal 2b connects related secondary adopt
The first input end 31a of sample circuit (3) and the second input terminal 32a；
Current Voltage linear transform circuit (2) is by NMOS tube N2, N3, N4, N5, N6 and PMOS tube P2, P3, P4, P5 and capacitance
C1 is formed；The PMOS tube P2 source electrodes meet power vd D, and grid connects the PMOS tube P3 grids, and drain electrode connects the PMOS tube P4 sources
Pole, the PMOS tube P4 grids connect the PMOS tube P5 grids, and drain electrode is connected with NMOS tube N3 drain electrodes, and is used as the electric current
The output terminal 2b of voltage linear conversion circuit (2), the NMOS tube N3 grids connect the NMOS tube N4 grids, and source electrode connects described
NMOS tube N5 drains, the NMOS tube N5 source electrodes ground connection, second input of the grid as the Current Voltage linear transform circuit (2)
22a is held, the PMOS tube P3 source electrodes meet power vd D, grid leak short circuit, and drain electrode meets the PMOS tube P5 source electrodes, the PMOS tube P5
Grid leak short circuit, drain electrode connect the NMOS tube N4 drain electrodes, the NMOS tube N4 grid leak short circuits, and source electrode connects the NMOS tube N6 drain electrodes,
The NMOS tube N6 grid leak short circuits, source electrode ground connection, the NMOS tube N2 drain electrodes terminate the Current Voltage line with the capacitance C1 mono-
Property conversion circuit (2) output terminal 2b, NMOS tube N2 drain electrode linearly turns with another termination Current Voltages of the capacitance C1
Change the input terminal 22a of circuit (2), first input of the NMOS tube N2 grids as the Current Voltage linear transform circuit (2)
Hold 21a；
In the correlation secondary sampling circuit (3), first input end 31a and the second input terminal 32a and Current Voltage linear transformation
The output terminal 2b of circuit (2) is connected, and the 3rd input terminal 33a is connected with the 3rd output terminal 53b of pattern sequential control circuit (5),
First output terminal 31b, the second output terminal 32b respectively with differential amplification output circuit (4) first input end 41a, the second input terminal
42a is connected；
Correlation secondary sampling circuit (3) is made of PMOS tube P6, P7, P8 and NMOS tube N7, N8, N9 and capacitance C2, C3；It is described
PMOS tube P6 source electrodes meet power vd D, and grid is connected with the NMOS tube N7 grids, and draws port as the correlation secondary sampling
3rd input terminal 33a of circuit (3), NMOS tube N7 source electrodes ground connection, drain electrode connect the PMOS tube P6 drain electrodes, and with it is described
PMOS tube P7 grids are connected with the NMOS tube N9 grids, and the PMOS tube P7 source electrodes connect the NMOS tube N8 drain electrodes, and draw
First input end 31a of the port as the correlation secondary sampling circuit (3), the PMOS tube P7 drain electrodes connect the NMOS tube N8 sources
Pole, and draw first output terminal 31b, the NMOS tube N8 and the PMOS of the port as the correlation secondary sampling circuit (3)
Pipe P8 grids are connected with each other, and are commonly connected to the 3rd input terminal 33a of the correlation secondary sampling circuit (3), the PMOS tube
P8 source electrodes are connected with NMOS tube N9 drain electrodes, and draw second input terminal of the port as the correlation secondary sampling circuit (3)
32a, the PMOS tube P8 drain electrodes are connected with the NMOS tube N9 source electrodes, and draw port as the correlation secondary sampling circuit
(3) the one of the second output terminal 32b, the capacitance C2 terminates the first output terminal 31b of the correlation secondary sampling circuit (3), institute
The one of capacitance C3 the second output terminal 32b for terminating the correlation secondary sampling circuit (3) is stated, capacitance C2, C3 other end all connects
Ground；
In the differential amplification output circuit (4), first input end 41a, the second input terminal 42a connect correlation secondary sampling electricity respectively
(3) first output terminal 31b of road, the output terminal that the second output terminal 32b, output terminal OUTPUT are the differential amplification output circuit (4),
It is also the output terminal of light multi-parameter sensing integrated circuit of the present invention at the same time；
Differential amplification output circuit (4) by NMOS tube N10, N11, N12, N13, N14, N15, N16 and PMOS tube P9, P10, P11,
P12, P13, P14, P15 are formed；The PMOS tube P9 source electrodes meet power vd D, and grid connects the PMOS tube P12 grids, described
PMOS tube P10 source electrodes connect the PMOS tube P11 source electrodes and are connected to the PMOS tube P9 drain electrodes, and the PMOS tube P10 grids connect
The NMOS tube N10 grids, the PMOS tube P11 grids connect the NMOS tube N11 grids, the NMOS tube N10 grid conducts
The first input end 41a of the differential amplification output circuit (4), source electrode connect the NMOS tube N11 source electrodes and are connected to the NMOS
Pipe N12 drains, second input terminal 42a, the NMOS of the NMOS tube N11 grids as the differential amplification output circuit (4)
Pipe N12 source electrodes are grounded, and grid connects the NMOS tube N15 grids, and the PMOS tube P12 source electrodes connect power vd D, grid leak short circuit, grid
Pole connects the PMOS tube P13 grids, and drain electrode connects the PMOS tube P14 source electrodes, and draws port and connect the NMOS tube N10 drain electrodes,
The PMOS tube P14 grids connect the PMOS tube P15 grids, grid leak short circuit, and drain electrode connects the NMOS tube N13 drain electrodes, described
NMOS tube N13 grid leak short circuits, grid connect the NMOS tube N14 grids, and source electrode connects the NMOS tube N15 drain electrodes, and draws port
The PMOS tube P10 drain electrodes, the NMOS tube N15 grid leak short circuits are connect, grid meets the NMOS tube N16 grids, source electrode ground connection, institute
State PMOS tube P13 source electrodes and meet power vd D, drain electrode connects the PMOS tube P15 source electrodes, and draws port and connect the NMOS tube N11 leakages
Pole, the PMOS tube P15 drain electrodes connect the NMOS tube N14 drain electrodes, and draw output terminal OUTPUT of the port as whole circuit,
The NMOS tube N14 source electrodes connect the NMOS tube N16 drain electrodes, and draw port and connect the PMOS tube P11 drain electrodes, the NMOS tube
N16 source electrodes are grounded；
The first input end Sel of the pattern sequential control circuit (5) is test pattern selection port, and the second input terminal CLK is defeated
Enter clock signal, the first output terminal 51b, the second output terminal 52b connect the first input end of BDJ photoelectric sensings selecting unit (1)
11a, the second input terminal 12a, the 3rd output terminal 53b meet the first input end 21a and correlation of Current Voltage linear transform circuit (2)
3rd input terminal 33a of double sampling circuit (3)；
Pattern sequential control circuit (5) by PMOS tube P16, P17, P18, P19, P20, P21, P22, P23, P24, P25, P26,
P27 and NMOS tube N17, N18, N19, N20, N21, N22, N23, N24, N25, N26, N27, N28 and capacitance C4, C5, C6, C7
Composition；The PMOS tube P16 source electrodes meet power vd D, and grid connects the NMOS tube N17 grids, and is connected with first input end Sel
And leaked as the second output terminal 52b of the pattern sequential control circuit (5), the PMOS tube P16 drain electrodes with the NMOS tube N17
Extremely it is connected, and draws first output terminal 51b of the port as the pattern sequential control circuit (5), the NMOS tube N17 source electrodes
Ground connection, the PMOS tube P17 source electrodes meet power vd D, and grid connects the NMOS tube N18 grids, and draws port and connect the second input
CLK is held, the PMOS tube P17 drain electrodes connect the NMOS tube N18 drain electrodes, and draw port and meet the PMOS tube P21 grids and institute
NMOS tube N19 grids, the NMOS tube N18 source electrodes ground connection are stated, the PMOS tube P18 source electrodes meet power vd D, and grid connects described
NMOS tube N20 grids, and connected with PMOS tube P22 drain electrodes and NMOS tube N23 drain electrodes, the PMOS tube P18 drain electrodes
The PMOS tube P19 source electrodes are connect, the PMOS tube P19 grids meet the second input terminal CLK, and drain electrode connects the NMOS tube N19 drain electrodes,
And draw port and connect described capacitance C4 one end and the PMOS tube P20 grids and the NMOS tube N22 grids, the NMOS tube
N19 source electrodes connect the NMOS tube N20 drain electrodes, and the NMOS tube N20 source electrodes ground connection, the capacitance C4 other ends are grounded, described
PMOS tube P20 source electrodes meet power vd D, and grid connects the NMOS tube N22 grids, and drain electrode connects the PMOS tube P21 source electrodes, described
PMOS tube P21 drain electrodes connect NMOS tube N21 drain electrode, and be connected to described capacitance C5 one end and the PMOS tube P22 grids and
The NMOS tube N23 grids, the NMOS tube N21 grids meet the second input terminal CLK, and source electrode meets the NMOS tube N22 drain electrodes, institute
NMOS tube N22 source electrodes ground connection, the capacitance C5 other ends ground connection are stated, the PMOS tube P22 source electrodes meet power vd D, and grid meets institute
NMOS tube N23 grids are stated, and are connected to the PMOS tube P24 grids and the NMOS tube N26 grids, the PMOS tube P22 leakages
Pole connects the NMOS tube N23 drain electrodes, and connects the PMOS tube P26 grids and the NMOS tube N24 grids, the NMOS tube
N23 source electrodes are grounded, and the PMOS tube P23 source electrodes meet power vd D, and grid connects the NMOS tube N25 grids, and is connected to the PMOS
Pipe P27 drains and NMOS tube N28 drain electrodes, and the PMOS tube P23 drain electrodes connect the PMOS tube P24 source electrodes, the PMOS tube
P24 drain electrodes connect NMOS tube N24 drain electrode, and are connected to described capacitance C6 one end and the PMOS tube P25 grids and described
NMOS tube N27 grids, the NMOS tube N24 source electrodes connect the NMOS tube N25 drain electrodes, and the NMOS tube N25 source electrodes ground connection is described
The capacitance C6 other ends are grounded, and the PMOS tube P25 source electrodes meet power vd D, and grid connects the NMOS tube N27 grids, and drain electrode meets institute
PMOS tube P26 source electrodes are stated, the PMOS tube P26 drain electrodes connect the NMOS tube N26 drain electrodes, and draw port and be connected to the capacitance C7
One end and the PMOS tube P27 grids and the NMOS tube N28 grids, the port are used as the pattern sequential control circuit at the same time
(5) the 3rd output terminal 53b, the NMOS tube N26 source electrodes connect the NMOS tube N27 drain electrodes, and the NMOS tube N27 source electrodes connect
Ground, the capacitance C7 other ends ground connection, the PMOS tube P27 source electrodes meet power vd D, and grid and drain electrode connect the NMOS tube respectively
N28 grids and drain electrode, the NMOS tube N28 source electrodes ground connection.
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| CN203629681U (en) * | 2013-12-12 | 2014-06-04 | 杭州电子科技大学 | An LED lamp illumination detection circuit |
| CN105226059A (en) * | 2014-06-30 | 2016-01-06 | 万国半导体股份有限公司 | Compact cmos device insulation system |
| CN106104232A (en) * | 2014-04-04 | 2016-11-09 | 夏普株式会社 | Light-receiving device and portable electronic device |
| CN106352977A (en) * | 2016-09-09 | 2017-01-25 | 四川中惯科技股份有限公司 | Four-quadrant sensor circuit |
| CN206740241U (en) * | 2017-04-27 | 2017-12-12 | 浙江工业大学 | A kind of smooth multi-parameter sensing CMOS monolithic integrated optical circuits |
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| EP1302986B1 (en) * | 2001-10-16 | 2008-05-21 | CSEM Centre Suisse d'Electronique et de Microtechnique SA | Photodetector with high dynamic range and increased operating temperature |
| JP4227152B2 (en) * | 2005-08-02 | 2009-02-18 | 三星電機株式会社 | Active pixel array of CMOS image sensor |
| US9627424B2 (en) * | 2014-11-19 | 2017-04-18 | Silicon Laboratories Inc. | Photodiodes for ambient light sensing and proximity sensing |
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|---|---|---|---|---|
| CN203629681U (en) * | 2013-12-12 | 2014-06-04 | 杭州电子科技大学 | An LED lamp illumination detection circuit |
| CN106104232A (en) * | 2014-04-04 | 2016-11-09 | 夏普株式会社 | Light-receiving device and portable electronic device |
| CN105226059A (en) * | 2014-06-30 | 2016-01-06 | 万国半导体股份有限公司 | Compact cmos device insulation system |
| CN106352977A (en) * | 2016-09-09 | 2017-01-25 | 四川中惯科技股份有限公司 | Four-quadrant sensor circuit |
| CN206740241U (en) * | 2017-04-27 | 2017-12-12 | 浙江工业大学 | A kind of smooth multi-parameter sensing CMOS monolithic integrated optical circuits |
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