CN107014382A - A kind of NEXT series of products OMAP and FPGA computing system - Google Patents

Abstract

The invention discloses a kind of NEXT series of products OMAP and FPGA computing system, the system is made up of FPGA system, dsp system, bionical polarized light sensor, A/D change-over circuits, odometer, MEMS, the Big Dipper/GPS, altimeter, PC；FPGA system is connected by extended serial port with odometer, MEMS, the Big Dipper/GPS, altimeter, PC, integration and pretreatment for system data, the EMIFA interfaces that dsp system and FPGA system are carried by dsp system are bi-directionally connected, navigation operations for realizing system, bionical polarized light sensor is used to gather polarized light signal, the height above sea level that altimeter is used for carrier is positioned, and PC is used to export attitude angle, speed, positional information, realizes the function of integrated navigation；The present invention has the characteristics of simple in construction, integrated level is high, low in energy consumption, arithmetic speed is fast.

Description

It is a kind of NEXT Series of products OMAP With FPGA Computing system

Technical field

The invention belongs to the concrete application of field of navigation systems, more particularly to a kind of NEXT series of products OMAP and FPGA computing system.

Background technology

With the development of modern science and technology, bionical polarized light sensor becomes the focus of research due to its unique advantage, and has obtained in navigation being increasingly widely applied.And now device just tend to miniaturization, it is integrated, micro inertial measurement unit become inertial navigation circle research emphasis.Micro-inertia measuring list is aided in using bionical polarized light sensor.Member completes navigation task, and not only application is unrestricted, and can suppress the error accumulation of inertia device, the navigation accuracy of Mierotubule-associated proteins is further enhanced.

Foreign countries are early in the sixties in last century, and the Wehner professors of animal institute of Univ Zurich Switzerland are in the husky ant biology of research, while have studied the polarotactic navigation mechanism of husky ant.Starting point is husky ant behaviouristics, by carrying out electrophysiologicalexperiment experiment and the navigation mechanism of husky ant being explored using biotomy, and the source of husky ant navigation information is found and have studied its polarization vision function, it is proposed that its photoelectricity model：The single ommatidium of husky ant perceives polarised light.And successful design bionic navigation robot, the navigation behavior of husky ant can be imitated, by means of vision sensor, realize the navigation feature of husky ant on the ground.Wherein Sahabot Series machines people, most representative, and its bionical polarotactic navigation compass is the photoelectricity modelling for perceiving polarised light using the Wehner single ommatidiums proposed by Lambrinos.

Relative to foreign countries, the domestic research for bionical polarotactic navigation, starting also achieves certain achievement in research than later.Especially in recent years, the correlative study to polarotactic navigation extend to increasing research institution.The doctor Lu Hongqian of Harbin Institute of Technology confirms a kind of effective integrated navigation system by emulation：Polarotactic navigation is got up with celestial navigation, INS；Professor Chu Jinkui leads the Team Member of his Dalian University of Technology to combine imitative husky ant polarotactic navigation with MEMS technology, the polarizer based on metal grating was have devised before this, further according to Point-source measuring methods, successfully polarotactic navigation sensor design is come out；2009, Peking University also began to study polarotactic navigation, and it is Yan Lei professors that it, which is represented, and he analyzes the polarization theory under the conditions of sky polarization mode patterns dynamic change and scattering,single；The Yang Fuxing of Beijing University of Post ＆ Telecommunication teaches a kind of photoelectric test system of polarotactic navigation of research and design, and experimental data is handled using the concurrent type frog model of polarotactic navigation, realizes the validity of result verification system design.

At present, the U.S., Russia, Australia, Switzerland, the scholar of Sweden study to bionical polarotactic navigation.As a kind of novel airmanship, bionical polarotactic navigation causes the extensive concern of domestic and international scientific research personnel.Bionical polarotactic navigation is a kind of new autonomous air navigation aid, and it is based on the natural light polarization of the earth, as long as so there is the place of natural light, it is possible to carry out polarotactic navigation.The especially sensitive polarization vision that it has using such as husky ant is perceived with navigation feature as biological basis, its theoretical foundation is the natural polarization characteristic of sunshine, pass through the detection and processing to atmospheric polarization type, extract corresponding information, by the resolving of brain and neuron, the course of carrier is judged.Satellite navigation signals are weaker or foreign environment of nothing in, this independent navigation mode is especially suitable for.

The precision of the long-term navigation of micro- inertia system is low, and error diverging is fast, it is impossible to which complete independently navigates, and the shortcoming of micro- inertia system is error accumulation over time and accumulated rapidly.The present invention combines bionical polarized light sensor and micro- inertia system, is improved a lot when the navigation system performance after combination can be made to be used than any one independent navigation system.Bionical polarised light/micro- inertia system integrated navigation, takes respective length, and benefit is each short, overcomes respective shortcoming, the navigation accuracy after integrating is higher than the precision that two systems work independently.

The content of the invention

In order to design a kind of navigation system based on DSP ﹢ FPGA architectures, the powerful data-handling capacity advantages of DSP are played, the powerful logic control abilities of FPGA and abundant I/O resources advantages is played：DSP is set to be absorbed in navigation calculation, FPGA extension multi-channel serial ports, to receive the various data needed for navigating.It is an object of the invention to provide a kind of NEXT series of products OMAP and FPGA computing system, the invention has the characteristics of simple in construction, integrated level is high, low in energy consumption, arithmetic speed is fast.

In order to realize said system, the present invention is adopted the technical scheme that：

A kind of NEXT series of products OMAP and FPGA computing system, it is characterised in that the system is made up of FPGA system, dsp system, bionical polarized light sensor, A/D change-over circuits, odometer, MEMS, the Big Dipper/GPS, altimeter, PC；Specifically, the polarized light signal that A/D change-over circuits first collect bionical polarized light sensor is converted into digital quantity, FPGA system is together inputted with MEMS data, FPGA system is integrated and pre-processed to data and inputs dsp system by EMIFA interfaces, dsp system carries out navigation calculation to the data of reception, just the speed needed for being navigated, positional information, altimeter information input dsp system can be obtained into altitude info ination through resolving, mileage is also counted into importing dsp system simultaneously, navigation calculation is calibrated, make the result of resolving more accurate, finally, navigation information can be shown by PC, PC is additionally operable to the hardware debugging of system simultaneously, because of weather conditions and orographic factor, in some moment and region, the collection of polarised light can be potentially encountered obstacle, high accuracy and real-time based on satellite navigation, therefore in particular cases system can use satellite navigation, so, the system just realizes area navigation desired position, speed, altitude information.

In OMAP the and FPGA computing systems, the FPGA system selects Spartan-3 series of X C3S200, and it has 173 I/O mouthfuls of users, distributed RAM capacity 30Kbit, BlockRAM capacity 216Kbit, and capacity is used enough, and dependable performance, and cost is low；The present invention is that the I/O and OMAP and other each devices for making FPGA have preferably electrically compatible, and each Bank I/O mouthfuls of voltage VCCO are configured into+3.3V；The present invention is using two kinds of loading modes：One is main string loading mode, its M [2:0] it is 000, FPGA initialization program is loaded using a Platform Flash；Two be JTAG MODE, its M [2:0] it is 101, thus, M [1] is set to 0, M [2] and M [0] with toggle switch always its one end is introduced into high level, one end introducing low level；Jtag interface uses double 14 pin contact pin, to connect emulator, several small resistors has been added between JTAG interfaces and FPGA, metering function is played.

In OMAP the and FPGA computing systems, the dsp system selects the OMAP-L138 chips of TI companies, a C6000 series DSPs processor and an ARM9 processor are integrated with OMAP-L138 chips, not only data-handling capacity is powerful for OMAP family chips, and also support operation operating system.Extraordinary performance can be provided by terminals equipment of very low power consumption, can realize up to 456-MHz unit core frequency for the bandwidth and function needed for data, voice, multimedia application are provided, the chip, support 32bit/16bit instructions；In the dsp system, power circuit selects the power supply chip TPS650531 of TI companies, and the chip is powered using outside 5V, the different magnitude of voltage in 5 tunnels can be produced, wherein preceding four tunnel：L1, L2, VLDO1, VLDO2 are that output voltage size can configure, and the 5th tunnel output VLDO3 output voltage values are fixed 1.2V；In the dsp system, OMAP emulator is connected by the 14 pin interfaces and board JTAG interfaces of a standard, and JATG interfaces use double 14 pin contact pin, and emulator is connected by usb bus with PC, and CCS is run on PC（Code Composer Studio）Software in the loop simulation debugs goal systems；In the dsp system, from Samsung DDR2 SDRAM K4T51163 as memory, from Fei Suo semiconductor companies of the U.S.（Spansion）NOR FLASH S29GL01GP are as the FLASH of system, and NOR FLASH are connected by OMAP-L138 EMIFA interfaces with system；, it is necessary to use two kinds of BOOT MODE in the dsp system：NOR FLASH MODE and Emulation Debug（JTAG debugging modes）, corresponding BOOT [7:0]：Respectively 0,000 0010 and 0,001 1110, so, by BOOT [7:6] with BOOT [1:0] low level, BOOT [4 are all accessed:2] toggle switch control, one end access high level, one end access ground are used.

In OMAP the and FPGA computing systems, the A/D change-over circuits select the modulus conversion chip ADS8556 of TI companies, ADS8556 is 16 high-precision As/D conversion chips, signal to noise ratio is up to 91.5dB, ADS8556 has 3 groups of analog input channels, and every group includes A, B two paths, and ADS8556 had both supported unipolarity or supported bipolar input signal, input reference signal can be configured to ± 2Vref or ± 4Vref, the reachable ± 12V of maximum input voltage scope；Present invention configuration STBY is high level, normal mode of operation；PAR/SER is low level, parallel interface pattern；REFen/WR is high level, and internal reference voltage source is enabled；RANG/XCLK is low level, and AD conversion analog channel input voltage range is ± 4 times of internal reference voltage value, and WORD/BYTE is low level, and data transfer digit is 16；In the present invention, HW/SW is connected to FPGA user's I/O port, high level is first configured to during work, ADS8556 control register CR is configured, CR [18]=0 under default conditions, 1 is write to CR [18], it is+3V to make ADS8556 internal reference voltages value, and it is ± 4 × 3V=± 12V that just can so make AD conversion analog channel input voltage range, meets polarized light analog signal ± 10V input voltage range, CR is configured, then HW/SW is configured to low level；In the A/D change-over circuits, three tunnel analog-to-digital conversion commencing signals are connected together, the synchronized sampling in LIULUTONG road is realized, the ADS8556 data bit of 16 is connected to FPGA, data transfer is carried out under FPGA SECO；Using preposition amplification of the OPA2141 and OPA4141 amplifiers as A/D change-over circuits in the present invention, wherein OPA2141 and OPA4141 is respectively 2 passages, 4 passages, and its internal principle is the same with OPA141；The present invention selects a voltage stabilizing chip LM7805, it is+5V by the+15V voltage conversions of outside input, powered for ADS8556 analog circuits, in order that ADS8556 I/O mouth electrical characteristics are preferably compatible with other devices, the present invention is using unified+3.3V digital voltages.

In OMAP the and FPGA computing systems, the work computing flow of the OMAP systems is as follows：

Step 1, beginning；

Step 2, initialization module；

Step 3, startup timer；

Step 4, interrupt latency judge, are then to carry out step 5, otherwise repeat step 4；

Step 5, reading data（MEMS, polarized light signal, GPS or the Big Dipper, altimeter, odometer）；

Step 6, navigation calculation；

Step 7, data output；

Step 8, startup timer, go to step 4.

The beneficial effects of the invention are as follows：

A kind of NEXT series of products OMAP and FPGA computing system, it is characterised in that system is made up of FPGA system, dsp system, bionical polarized light sensor, A/D change-over circuits, odometer, MEMS, the Big Dipper/GPS, altimeter, PC；Navigation system of the invention based on DSP ﹢ FPGA architectures, has played the powerful data-handling capacity advantages of DSP, has played the powerful logic control abilities of FPGA and abundant I/O resources advantages：DSP is set to be absorbed in navigation calculation, FPGA extends multi-channel serial port, to receive the various data needed for navigating, under FPGA SECO, by MEMS data and the polarised light information data after AD conversion input FPGA, also by odometer, altimeter, satellite data input FPGA, FPGA complete to inputting DSP after the integration and pretreatment of these data, DSP completes the navigation calculation to receiving data, and posture, position, velocity information are exported finally by host computer.The present invention has the characteristics of simple in construction, integrated level is high, low in energy consumption, arithmetic speed is fast.

Brief description of the drawings

The present invention is further explained below in conjunction with the drawings and specific embodiments.

Fig. 1 is NEXT series of products OMAP and FPGA computing system overall framework figures；

Fig. 2 is OMAP-L138 system block diagrams；

Fig. 3 is system power supply circuit diagram；

Fig. 4 is JTAG artificial debugging circuit diagrams；

Fig. 5 is BOOT MODE selection circuit figures；

Fig. 6 is FPGA configurations and jtag circuit figure；

Fig. 7 is the pre-amplification circuit figure of AD conversion；

Fig. 8 is the work operational flowchart of OMAP systems.

Embodiment

The present invention embodiment be：A kind of described NEXT series of products OMAP and FPGA computing system, first, the polarized light signal that bionical polarized light sensor is collected is converted into digital quantity by A/D change-over circuits, FPGA system is together inputted with MEMS data, FPGA system is integrated and pre-processed to data and inputs dsp system by EMIFA interfaces, dsp system carries out navigation calculation to the data of reception, just the speed needed for being navigated, positional information, altimeter information input dsp system can be obtained into altitude info ination through resolving, mileage is also counted into importing dsp system simultaneously, navigation calculation is calibrated, make the result of resolving more accurate, finally, navigation information can be shown by PC, PC is additionally operable to the hardware debugging of system simultaneously, because of weather conditions and orographic factor, in some moment and region, the collection of polarised light can be potentially encountered obstacle, high accuracy and real-time based on satellite navigation, therefore in particular cases system can use satellite navigation, so, the system just realizes area navigation desired position, speed, altitude information.

Fig. 1 is NEXT series of products OMAP and FPGA computing system overall framework figures, and the system is made up of FPGA system, dsp system, bionical polarized light sensor, A/D change-over circuits, odometer, MEMS, the Big Dipper/GPS, altimeter, PC；FPGA system passes through extended serial port and odometer, MEMS, the Big Dipper/GPS, altimeter, PC is connected, integration and pretreatment for system data, the EMIFA interfaces that dsp system and FPGA system are carried by dsp system are bi-directionally connected, navigation operations for realizing system, bionical polarized light sensor is used to gather polarized light signal, A/D change-over circuits are used to the polarized light analog signal collected being converted to data signal, odometer is used to calibrate bearer rate information, MEMS is used to provide horizontal angle information for system, the height above sea level that altimeter is used for carrier is positioned, PC is used to export attitude angle, speed, positional information, realize the function of integrated navigation.

Fig. 2 is OMAP-L138 system block diagrams, the dsp system selects the OMAP-L138 chips of TI companies, a C6000 series DSPs processor and an ARM9 processor are integrated with OMAP-L138 chips, not only data-handling capacity is powerful for OMAP family chips, and also support operation operating system.Extraordinary performance can be provided by terminals equipment of very low power consumption, can realize up to 456-MHz unit core frequency for the bandwidth and function needed for data, voice, multimedia application are provided, the chip, support 32bit/16bit instructions；In the dsp system, from Samsung DDR2 SDRAM K4T51163 as memory, from Fei Suo semiconductor companies of the U.S.（Spansion）NOR FLASH S29GL01GP are as the FLASH of system, and NOR FLASH are connected by OMAP-L138 EMIFA interfaces with system.

Fig. 3 is system power supply circuit diagram, in the dsp system, and power circuit selects the power supply chip TPS650531 of TI companies, and the chip is powered using outside 5V, the different magnitude of voltage in 5 tunnels can be produced, wherein preceding four tunnel：L1, L2, VLDO1, VLDO2 are that output voltage size can configure, and the 5th tunnel output VLDO3 output voltage values are fixed 1.2V；Preceding four tunnels output is respectively configured as+1.2V ,+3.3V.+ 1.8V, F_+2.5V.Wherein+1.2V supplies OMAP-L138 kernels, and+3.3V supplies OMAP, FPGA I/O mouths and NOR FLASHA, + 1.8V supplies OMAP I/O mouths and DDR2SDRAM, F_+2.5V supplies FPGA accessory power supply VCCAUX, finally F_+1.2V supplies FPGA core voltage all the way, and the output of the tunnels of TPS650531 five L1, L2, VLDO1, VLDO2, VLDO3 current driving ability are respectively 1000mA, 1000mA, 400mA, 200mA, 200mA, device each enough are used.Only correct electric order just can guarantee that the normal startup and work of device, if upper electric order is wrong, not only device cisco unity malfunction, it is also possible to which device is caused damage.OMAP-L138 upper electric order is successively：+ 1.2V core voltages ,+1.8VI/O mouthfuls of voltages, as illustrated, it is respectively ENDCDC1, ENDCDC2, ENLDO1, ENLDO2, ENLDO3 that five, which enable passage,.

Fig. 4 is JTAG artificial debugging circuit diagrams, and OMAP emulator is connected by the 14 pin interfaces and board jtag interface of a standard, and JATG interfaces use double 14 pin contact pin, and emulator is connected by usb bus with PC, and CCS is run on PC（Code Composer Studio）Software in the loop simulation debugs goal systems.

Fig. 5 is BOOT MODE selection circuit figures, and BOOT pins are sampled, and Boot Loader loading modes is determined with the BOOT values sampled, it is necessary to use two kinds of BOOT MODE in the dsp system：NOR FLASH MODE and Emulation Debug（JTAG debugging modes）, corresponding BOOT [7:0]：Respectively 0,000 0010 and 0,001 1110, so, by BOOT [7:6] with BOOT [1:0] low level, BOOT [4 are all accessed:2] toggle switch control, one end access high level, one end access ground are used.

Fig. 6 is FPGA configurations and jtag circuit figure, and the present invention is using two kinds of loading modes：One is main string loading mode, its M [2:0] it is 000, FPGA initialization program is loaded using a Platform Flash；Two be JTAG MODE, its M [2:0] it is 101, thus, M [1] is set to 0, M [2] and M [0] with toggle switch always its one end is introduced into high level, one end introducing low level.Jtag interface uses double 14 pin contact pin, to connect emulator.Because the power supply VREF of jtag port is+3.3V, and FPGA several JTAG pins TDI, TDO, TMS, TCK are powered by+2.5V VCCAUX, so having added several small resistors between jtag interface and FPGA, play metering function.

Fig. 7 is the pre-amplification circuit figure of AD conversion, and in order to ensure the correct and stable regulation of chip energy in acquisition time, ADS8556 input is generally required plus an operational amplifier is to drive.For driving force, noise and offset behavior, TI OPA141, which can reach, ensures many preposition amplifications for requiring, making A/D in the present invention using OPA2141 and OPA4141 amplifiers necessary to high input signal quality.Wherein OPA2141 and OPA4141 is respectively 2 passages, 4 passages, and OPA2141 is a with low noise level, low-power consumption, low bias voltage drift, wide power voltage scope（Single-ended 4.5V ~ 36V, or both-end ± 2.25~± 18V）Accurate ambipolar two-way operational amplifier, its noise density only has 6.5 nV/ Hz, and voltage drift is 10uV/ DEG C to the maximum.OPA2141 can be amplified to two paths of signals, and circuit is connected for channel C H_C0 and C H_C1 preposition amplification shown in figure.The present invention is powered using bipolar voltage to it.According to databook, its signal input range is（V-）-0.5V~ （V+）+ 0.5V, so, make its generating positive and negative voltage identical with HVSS generating positive and negative voltage with ADS8556 HVDD.That is V+ is+15V, and V- is -15V.Channel C H_A [1:0] and CH_B [1:0] preposition amplification connection circuit is provided by OPA4141.

Fig. 8 is the work operational flowchart of OMAP systems, and the work computing flow of the OMAP systems is as follows：

Step 1, beginning；

Step 2, initialization module；

Step 3, startup timer；

Step 4, interrupt latency judge, are then to carry out step 5, otherwise repeat step 4；

Step 5, reading data（MEMS, polarized light signal, GPS or the Big Dipper, altimeter, odometer）；

Step 6, navigation calculation；

Step 7, data output；

Step 8, startup timer, go to step 4.

General technical staff of the technical field of the invention also will readily appreciate that in addition to the foregoing, and the specific embodiment for illustrating herein and illustrating can further change combination.Although the present invention gives diagram with regard to its preferred embodiment and illustrated, person skilled in the art to the present invention, it is recognized that in the spirit and scope of the present invention limited in the attached claims, can also make a variety of changes and variation.

Claims (5)

1. a kind of NEXT series of products OMAP and FPGA computing system, it is characterised in that the system is made up of FPGA system, dsp system, bionical polarized light sensor, A/D change-over circuits, odometer, MEMS, the Big Dipper/GPS, altimeter, PC；The present invention uses DSP+FPGA processor architecture form, and FPGA system is connected by extended serial port with odometer, MEMS, the Big Dipper/GPS, altimeter, PC, and the EMIFA interfaces that dsp system and FPGA system are carried by dsp system are bi-directionally connected；Specifically, the polarized light signal that A/D change-over circuits first collect bionical polarized light sensor is converted into digital quantity, FPGA system is together inputted with MEMS data, FPGA system is integrated and pre-processed to data and inputs dsp system by EMIFA interfaces, dsp system carries out navigation calculation to the data of reception, just the speed needed for being navigated, positional information, altimeter information input dsp system can be obtained into altitude info ination through resolving, mileage is also counted into importing dsp system simultaneously, navigation calculation is calibrated, make the result of resolving more accurate, finally, navigation information can be shown by PC, PC is additionally operable to the hardware debugging of system simultaneously, because of weather conditions and orographic factor, in some moment and region, the collection of polarised light can be potentially encountered obstacle, high accuracy and real-time based on satellite navigation, therefore in particular cases system can use satellite navigation, so, the system just realizes area navigation desired position, speed, altitude information.

2. NEXT series of products OMAP and FPGA computing system as claimed in claim 1, it, which is levied, is, the FPGA system selects Spartan-3 series of X C3S200, it has 173 I/O mouthfuls of users, distributed RAM capacity 30Kbit, BlockRAM capacity 216Kbit, capacity is used enough, and dependable performance, cost is low；The present invention is that the I/O and OMAP and other each devices for making FPGA have preferably electrically compatible, and each Bank I/O mouthfuls of voltage VCCO are configured into+3.3V；The present invention is using two kinds of loading modes：One is main string loading mode, its M [2:0] it is 000, utilizes a Platform Flash loads FPGA initialization program；Two be JTAG MODE, its M [2:0] it is 101, thus, M [1] is set to 0, M [2] and M [0] with toggle switch always its one end is introduced into high level, one end introducing low level；Jtag interface uses double 14 pin contact pin, to connect emulator, several small resistors has been added between JTAG interfaces and FPGA, metering function is played.

3. NEXT series of products OMAP and FPGA computing system as claimed in claim 1, it, which is levied, is, the dsp system selects the OMAP-L138 chips of TI companies, a C6000 series DSPs processor and an ARM9 processor are integrated with OMAP-L138 chips, not only data-handling capacity is powerful for OMAP family chips, and also support operation operating system, extraordinary performance can be provided by terminals equipment of very low power consumption, can be data, voice, multimedia application provides required bandwidth and function, the chip can realize up to 456-MHz unit core frequency, support 32bit/16bit instructions；In the dsp system, power circuit selects the power supply chip TPS650531 of TI companies, and the chip is powered using outside 5V, the different magnitude of voltage in 5 tunnels can be produced, wherein preceding four tunnel：L1, L2, VLDO1, VLDO2 are that output voltage size can configure, and the 5th tunnel output VLDO3 output voltage values are fixed 1.2V；In the dsp system, OMAP emulator is connected by the 14 pin interfaces and board JTAG interfaces of a standard, and JATG interfaces use double 14 pin contact pin, and emulator is connected by usb bus with PC, and CCS is run on PC（Code Composer Studio）Software in the loop simulation debugs goal systems；In the dsp system, from the DDR2 SDRAM of Samsung K4T51163 is as memory, from Fei Suo semiconductor companies of the U.S.（Spansion）NOR FLASH S29GL01GP be used as the FLASH of system, NOR FLASH is connected by OMAP-L138 EMIFA interfaces with system；, it is necessary to use two kinds of BOOT MODE in the dsp system：NOR FLASH MODE and Emulation Debug（JTAG debugging modes）, corresponding BOOT [7:0]：Respectively 0,000 0010 and 0,001 1110, so, by BOOT [7:6] with BOOT [1:0] low level, BOOT [4 are all accessed:2] toggle switch control, one end access high level, one end access ground are used.

4. NEXT series of products OMAP and FPGA computing system as claimed in claim 1, it, which is levied, is, the A/D change-over circuits select the modulus conversion chip ADS8556 of TI companies, ADS8556 is 16 high-precision As/D conversion chips, signal to noise ratio is up to 91.5dB, ADS8556 has 3 groups of analog input channels, every group includes A, B two paths, ADS8556 had both supported unipolarity or had supported bipolar input signal, input reference signal can be configured to ± 2Vref or ± 4Vref, the reachable ± 12V of maximum input voltage scope；Present invention configuration STBY is high level, normal mode of operation；PAR/SER is low level, parallel interface pattern；REFen/WR is high level, and internal reference voltage source is enabled；RANG/XCLK is low level, and AD conversion analog channel input voltage range is ± 4 times of internal reference voltage value, and WORD/BYTE is low level, and data transfer digit is 16；In the present invention, HW/SW is connected to FPGA user's I/O port, high level is first configured to during work, ADS8556 control register CR is configured, CR [18]=0 under default conditions, 1 is write to CR [18], it is+3V to make ADS8556 internal reference voltages value, and it is ± 4 × 3V=± 12V that just can so make AD conversion analog channel input voltage range, meets polarized light analog signal ± 10V input voltage range, CR is configured, then HW/SW is configured to low level；In the A/D change-over circuits, three tunnel analog-to-digital conversion commencing signals are connected together, the synchronized sampling in LIULUTONG road is realized, the ADS8556 data bit of 16 is connected to FPGA, data transfer is carried out under FPGA SECO；Using preposition amplification of the OPA2141 and OPA4141 amplifiers as A/D change-over circuits in the present invention, wherein OPA2141 and OPA4141 is respectively 2 passages, 4 passages, and its internal principle is the same with OPA141；The present invention selects a voltage stabilizing chip LM7805, is+5V by the+15V voltage conversions of outside input, is that ADS8556 analog circuits are powered, in order that ADS8556 I/O mouth electrical characteristics are preferably compatible with other devices, the present invention is using unified+3.3V digital voltages.

5. NEXT series of products OMAP and FPGA computing system as claimed in claim 1, it, which is levied, is, the work computing flow of the OMAP systems is as follows：

Step 1, beginning；

Step 2, initialization module；

Step 3, startup timer；

Step 4, interrupt latency judge, are then to carry out step 5, otherwise repeat step 4；

Step 5, reading data（MEMS, polarized light signal, GPS or the Big Dipper, altimeter, odometer）；

Step 6, navigation calculation；

Step 7, data output；

Step 8, startup timer, go to step 4.