CN106997011A - A kind of test device for MMC valve current unit - Google Patents
A kind of test device for MMC valve current unit Download PDFInfo
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- CN106997011A CN106997011A CN201610050045.9A CN201610050045A CN106997011A CN 106997011 A CN106997011 A CN 106997011A CN 201610050045 A CN201610050045 A CN 201610050045A CN 106997011 A CN106997011 A CN 106997011A
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- mathematical model
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
Abstract
The present invention designs a kind of test device for MMC valve current unit, and the test device is based on layer architecture, including：Interface layer：It is the tie between physical signalling and logical signal for connecting current unit and mathematical model；Model layer：Mathematical model needed for building, analog current unit and its working characteristics；Key-course：By each model of command operating, it is set to cooperate, the working environment of analog current unit；Read each model working condition and generate sequence of events recording SOE and report operation layer；Operation layer：Mathematical model is mapped using visualization model；SOE is recorded, later stage enquiry of historical data is analyzed.The technical scheme that the present invention is provided is using current unit as test object；Working characteristics according to collection unit, OCT and PCP sets up corresponding mathematical model；Mathematical model can be observed, be controlled by host computer；With the peripheral environment of mathematical model analog current unit；And then deploy comprehensive, deep test.
Description
Technical field
The present invention relates to a kind of test device of flexible direct-current transmission field, and in particular to a kind of for MMC valve current unit
Test device.
Background technology
In flexible DC power transmission engineering, current unit is responsible for control bridge arm output voltage and electric current, is most important composition in VBC
One of part, must have continuous, stable service ability.The current method of testing to current unit is mainly group in the lab
Build low-voltage, the flexible direct current converter station dynamic model platform of low current simulates the working condition of current conversion station in Practical Project, by right
Current unit hardware reliability, control strategy, Preservation tactics etc. are verified by VBC integrated testability.
However, VBC is the secondary device of cooperation between a huge structure, multi-functional unit；Each current unit need with
Multiple collection units, photocurrent sensor (abbreviation OCT) and pole control protection system (abbreviation PCP) coordinate lower work.Currently
Dynamic model platform have the limitations such as complex operation, very flexible, assessment can only be made to VBC overall performances, is but difficult to electric current list
Member does more deep test for object.Accordingly, it would be desirable to which a kind of good device of more flexible, easy to operate, versatility is to electric current list
Member carries out comprehensive, deep test.But do not find to carry out VBC current units the device design side of depth test both at home and abroad at present
Case.
The content of the invention
To solve above-mentioned deficiency of the prior art, it is an object of the invention to provide a kind of test for MMC valve current unit
Device, the device is using current unit as test object；Working characteristics according to collection unit, OCT and PCP sets up corresponding number
Word model；Mathematical model can be observed, be controlled by host computer；With the peripheral environment of mathematical model analog current unit；
And then deploy comprehensive, deep test.
The purpose of the present invention is realized using following technical proposals：
The present invention relates to a kind of test device for MMC valve current unit, it is theed improvement is that, the test device base
In layer architecture, including：
(1) interface layer：It is the tie between physical signalling and logical signal for connecting current unit and mathematical model；
(2) model layer：The mathematical model of current unit ancillary equipment is built in FPGA by hardware language (HDL), is wrapped
Include collection unit, optic current transformer (OCT) and pole control protection (PCP) mathematical model, simulation collection unit, photoelectricity
Current transformer (OCT) and pole control protection (PCP) mathematical model working characteristics, peripheral working environment is provided for current unit；
(3) key-course：Command operating mathematical model, makes it cooperate, the working environment of analog current unit；Read each mould
Type working condition simultaneously generates sequence of events recording SOE and reports operation layer；
(4) operation layer：Mathematical model is mapped using visualization model in host computer interface, by operating visualization model, set
The working method of mathematical model, and read the working condition of mathematical model；The SOE that mathematical model is produced is recorded simultaneously, for experiment
Post analysis provides historical data.
Further, the interface layer is made up of at least one piece interface board；The interface board will receive the fiber-optic signal of current unit
It is converted into LVDS signals and is transferred to model layer, and the LVDS signals for being received from model layer is converted into signal transmission through fiber to electricity
Flow unit.
Further, the model layer is made up of FPGA；The FPGA includes collection unit, optic current transformer (OCT)
With pole control protection (PCP) mathematical model.
Further, the key-course is made up of DSP and Ethernet driver；The each controlling cycle of key-course accesses numeral
Model one time；When checking state change, generate corresponding event journal SOE and sent by Ethernet to operation layer；Surely
Determine under running status, key-course does not change the running status of mathematical model；When receiving the instruction code that operation layer is sent, control
Preparative layer is operated according to instruction code to model layer, while generating sequence of events recording SOE is uploaded to operation layer；The control
Cycle is 100us.
Further, the operation layer is made up of drive module, main operation module, database and user interface, in user interface
Visualization model including collection unit, OCT and PCP mathematical models, the visualization model maps to whole numbers of model layer
Word model；
During the operation layer operation, main operation module receives the sequence of events recording SOE data parsed from drive module, according to
Its content change visualization model shows result, then stores sequence of events recording SOE to database；Need to change experiment shape
During state, operation layer sends instruction code to key-course, and the SECO of mathematical model is completed by key-course；Tester by using
Family interface accesses database, reappears whole process of the test, and analysis result according to historical data.
Further, the interface layer, model layer and key-course constitute the slave computer of current unit test device；The operation layer
Constitute the host computer of current unit test device.
Compared with immediate prior art, the excellent effect that the technical scheme that the present invention is provided has is：
(1) test device (VTS) is easy to operate：The mathematical model of each collection unit, OCT and PCP is in host computer screen
On have corresponding visualization model；Tester can configure experimental enviroment by visualization model, understand Test condition；Greatly
Big reduction operation difficulty.
(2) test device (VTS) has automation：Part test needs to reach 0.1 between collection unit, OCT and PCP
Ms grades of cooperations, existing test device is difficult to；VTS key-course can be carried out under operation layer control instruction to each model
Unified scheduling, control, carry out a series of automation, the operation of sequential tightly.
(3) test device (VTS) record is complete：SOE is stored in database by operation layer；According to historical data, it can recover
Complete process of the test.
Therefore, VTS is adapted to carry out depth survey to current unit and the similar functional unit worked in huge, complicated electrical secondary system
Examination.
Brief description of the drawings
Fig. 1 is the test device VTS hardware structure diagrams provided by the present invention for MMC valve current unit；
Fig. 2 is that interface layer, model layer and the key-course that the present invention is provided describe schematic diagram；
Fig. 3 is that the operation layer that the present invention is provided describes schematic diagram；
Fig. 4 is the test device VTS structural representations provided by the present invention for MMC valve current unit.
Embodiment
The embodiment to the present invention is described in further detail below in conjunction with the accompanying drawings.
The following description and drawings fully show specific embodiments of the present invention, to enable those skilled in the art to put into practice it
.Other embodiments can include structure, logic, electric, process and other changes.Embodiment only generation
The possible change of table.Unless explicitly requested, otherwise single component and function are optional, and the order operated can change.
The part of some embodiments and feature can be included in or replace part and the feature of other embodiments.The implementation of the present invention
The scope of scheme includes the gamut of claims, and claims all obtainable equivalents.Herein,
These embodiments of the present invention can individually or generally be represented that it is convenient that this is used for the purpose of with term " invention ", and
And if in fact disclosing the invention more than one, the scope for being not meant to automatically limit the application is any single invention or hair
Bright design.
The invention provides a kind of test device suitable for current unit, abbreviation VTS, based on hierarchical architecture design thinking, divides
For interface layer, model layer, key-course and operation layer：
(1) interface layer：Current unit and mathematical model are connected, is the tie between physical signalling and logical signal；
(2) model layer：The mathematical model of current unit ancillary equipment is built in FPGA by hardware language (HDL), is wrapped
Include collection unit, optic current transformer (OCT) and pole control protection (PCP) mathematical model, simulation collection unit, photoelectricity
Current transformer (OCT) and pole control protection (PCP) mathematical model working characteristics, peripheral working environment is provided for current unit；
(3) key-course：Command operating mathematical model, makes it cooperate, the working environment of analog current unit；Read each mould
Type working condition simultaneously generates sequence of events recording SOE and reports operation layer (0.1ms resolution ratio)；
(4) operation layer：Mathematical model is mapped using visualization model in host computer interface, by operating visualization model, set
The working method of mathematical model, and read the working condition of mathematical model；The SOE that mathematical model is produced is recorded simultaneously, for experiment
Post analysis provides historical data.It is described in detail below：
As shown in figure 1, VTS is made up of host computer slave computer two parts, functionally it is divided into interface layer, model layer, key-course
And operation layer.
As shown in Fig. 2 interface layer is made up of 10 pieces of interface boards.The fiber-optic signal for being received from current unit is converted into by interface board
LVDS signals are transferred to model layer, and the LVDS signals for being received from model layer are converted into signal transmission through fiber to current unit.
As shown in Fig. 2 model layer is made up of FPGA.Mathematical model will be capable of the primary operating characteristics of analog machine, even in
In the case that key-course is not involved in, current unit continuous service can be also driven.Hardware description language (Hardware Description
Language, abbreviation HDL) there is the characteristics of running parallel.The mathematical model write in FPGA with HDL may insure
Separate operation between different models, more really simulates the situation of multiple ancillary equipment Collaboration, it might even be possible to which simulation is not
With clock drift phenomenon between equipment.
As shown in Fig. 2 key-course is made up of DSP and Ethernet driver.The each controlling cycle of key-course (100us) is accessed
Mathematical model one time；When checking state change, generate corresponding SOE and sent by Ethernet to operation layer；Stable operation shape
Under state, key-course does not change the running status of mathematical model；When receiving the instruction code that operation layer is sent, key-course according to
The instruction carries out a series of, orderly operation to model layer, while generating SOE is uploaded to operation layer.
As shown in figure 3, operation layer is made up of driver, main program, database and user interface, being included in user interface can
Depending on changing module, the latter maps to whole mathematical models of model layer.During operation, main program receives the SOE parsed from driver
Data, change visualization model according to its content and show result, then store SOE to database；Need to change trystate
When, operation layer sends corresponding instruction code to key-course, and the SECO of mathematical model is completed by the latter.Tester can be with
Database is accessed by user interface, whole process of the test, analysis result are reappeared according to historical data.
It is VTS schematic diagrames shown in Fig. 4.Current unit cooperates with multiple collection units, OCT and PCP in systems.
VTS configurations are as follows：(1) current unit is connected by optical fiber with VTS slave computers；(2) collection unit, OCT are included in FPGA
With PCP mathematical model；(3) corresponding control, communication program are included in controller；(4) host computer comprising collection unit,
The visualization model of OCT and PCP mathematical models.In experiment, tester is held by upper computer selecting content of the test, slave computer
Row operates and returns to test data；Tester passes through data analysis result of the test.
The present invention provides the test device suitable for current unit, and the device is using current unit as test object；Foundation collection unit,
OCT and PCP working characteristics sets up corresponding mathematical model；Mathematical model can be observed, be controlled by host computer；With
The peripheral environment of mathematical model analog current unit；And then deploy comprehensive, deep test.
The above embodiments are merely illustrative of the technical scheme of the present invention and are not intended to be limiting thereof, although with reference to above-described embodiment to the present invention
Be described in detail, those of ordinary skill in the art still can to the present invention embodiment modify or
Person's equivalent substitution, these any modifications or equivalent substitution without departing from spirit and scope of the invention are applying for this pending hair
Within bright claims.
Claims (6)
1. a kind of test device for MMC valve current unit, it is characterised in that the test device is based on layer architecture,
Including：
(1) interface layer：It is the tie between physical signalling and logical signal for connecting current unit and mathematical model；
(2) model layer：The mathematical model of current unit ancillary equipment is built in FPGA by hardware language (HDL), is wrapped
Include collection unit, optic current transformer (OCT) and pole control protection (PCP) mathematical model, simulation collection unit, photoelectricity
Current transformer (OCT) and pole control protection (PCP) mathematical model working characteristics, peripheral working environment is provided for current unit；
(3) key-course：By command operating mathematical model, it is set to cooperate, the working environment of analog current unit；Read each
Model working condition simultaneously generates sequence of events recording SOE and reports operation layer；
(4) operation layer：Mathematical model is mapped using visualization model in host computer interface, by operating visualization model, set
The working method of mathematical model, and read the working condition of mathematical model；The SOE that mathematical model is produced is recorded simultaneously, for experiment
Post analysis provides historical data.
2. test device as claimed in claim 1, it is characterised in that the interface layer is made up of at least one piece interface board；Institute
State interface board to be converted into LVDS signals and be transferred to model layer the fiber-optic signal for receiving current unit, and model layer will be received from
LVDS signals are converted into signal transmission through fiber to current unit.
3. test device as claimed in claim 1, it is characterised in that the model layer is made up of FPGA；The FPGA
Include collection unit, optic current transformer (OCT) and pole control protection (PCP) mathematical model.
4. test device as claimed in claim 1, it is characterised in that the key-course is by DSP and Ethernet driver group
Into；The each controlling cycle of key-course accesses mathematical model one time；When checking state change, generation corresponding event order is remembered
Record SOE is simultaneously sent to operation layer by Ethernet；Under steady operational status, key-course does not change the running status of mathematical model；
When receiving the instruction code that operation layer is sent, key-course is operated according to instruction code to model layer, while the event of generation
Journal SOE is uploaded to operation layer；The controlling cycle is 100us.
5. test device as claimed in claim 1, it is characterised in that the operation layer by drive module, main operation module,
Include collection unit, the visualization model of OCT and PCP mathematical models, institute in database and user interface composition, user interface
State whole mathematical models that visualization model maps to model layer；
During the operation layer operation, main operation module receives the sequence of events recording SOE data parsed from drive module, according to
Its content change visualization model shows result, then stores sequence of events recording SOE to database；Need to change experiment shape
During state, operation layer sends instruction code to key-course, and the SECO of mathematical model is completed by key-course；Tester by using
Family interface accesses database, reappears whole process of the test, and analysis result according to historical data.
6. test device as claimed in claim 1, it is characterised in that the interface layer, model layer and key-course composition electric current
The slave computer of unit testing device；The operation layer constitutes the host computer of current unit test device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610050045.9A CN106997011A (en) | 2016-01-26 | 2016-01-26 | A kind of test device for MMC valve current unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610050045.9A CN106997011A (en) | 2016-01-26 | 2016-01-26 | A kind of test device for MMC valve current unit |
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| Publication Number | Publication Date |
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| CN106997011A true CN106997011A (en) | 2017-08-01 |
Family
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| Application Number | Title | Priority Date | Filing Date |
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| CN201610050045.9A Pending CN106997011A (en) | 2016-01-26 | 2016-01-26 | A kind of test device for MMC valve current unit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109240157A (en) * | 2018-09-13 | 2019-01-18 | 华北电力科学研究院有限责任公司 | SOE signal generation apparatus and SOE signal output method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102313850A (en) * | 2011-06-24 | 2012-01-11 | 中国电力科学研究院 | Physical real-time dynamic simulation device for flexible direct current transmission system |
| CN103631235A (en) * | 2013-12-05 | 2014-03-12 | 国家电网公司 | Valve monitor system applicable to high-capacity MMC flexible high-voltage direct-current transmission |
| CN103713214A (en) * | 2013-12-24 | 2014-04-09 | 国家电网公司 | Intelligent transformer station relay protection closed loop test system |
-
2016
- 2016-01-26 CN CN201610050045.9A patent/CN106997011A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102313850A (en) * | 2011-06-24 | 2012-01-11 | 中国电力科学研究院 | Physical real-time dynamic simulation device for flexible direct current transmission system |
| CN103631235A (en) * | 2013-12-05 | 2014-03-12 | 国家电网公司 | Valve monitor system applicable to high-capacity MMC flexible high-voltage direct-current transmission |
| CN103713214A (en) * | 2013-12-24 | 2014-04-09 | 国家电网公司 | Intelligent transformer station relay protection closed loop test system |
Non-Patent Citations (4)
| Title |
|---|
| 刘栋 等: "模块化多电平柔性直流输电数字-模拟混合实时仿真技术", 《电力自动化设备》 * |
| 季子孟 等: "柔性直流输电工程二次保护系统的实现", 《电力安全技术》 * |
| 赵成勇 等: "MMC-HVDC物理模拟系统的控制器架构设计", 《电力系统自动化》 * |
| 陈晓捷 等: "柔性直流换流站IGBT换流阀控制、监视及保护系统设计", 《能源与环境》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109240157A (en) * | 2018-09-13 | 2019-01-18 | 华北电力科学研究院有限责任公司 | SOE signal generation apparatus and SOE signal output method |
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