CN106993306B - FPGA-based wireless network MAC layer distributed coordination system and construction method thereof - Google Patents
FPGA-based wireless network MAC layer distributed coordination system and construction method thereof Download PDFInfo
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Abstract
The invention provides a wireless network MAC layer distributed coordination system based on FPGA and a construction method thereof, comprising a data storage module, a time slot control module, an information grouping processing module and a throughput detection module; the data storage module, the time slot control module, the information packet processing module, the signal flow direction between the throughput detection modules is: the invention also provides a construction method of the system, wherein Poisson data generated in Matlab software is connected with a time slot control module through a data storage module and a primary station, signals from the time slot control module enter an information processing module through an information station, and then enter a throughput detection module. The invention can generate Poisson data flow and adjust the time slot length according to different channel states, thus realizing the information source meeting the requirement of the protocol algorithm; the control module controls and feeds back the information of different states of the channel and realizes a protocol algorithm control mechanism in a skip reading mode; the system expansibility realizes a multi-node competition system.
Description
Technical Field
The invention relates to the technical field of communication systems, in particular to a wireless network MAC layer distributed coordination system based on FPGA and a construction method thereof.
Background
With the continuous development of communication technology, we are moving to deeper communication system fields. Wireless local area networks are widely used due to their reliability and flexibility. However, the channel of the wlan is in an external sharing state, and the link state is unstable, so it is very important to reasonably allocate limited resources. The communication network system is composed of a large number of stations, communication services of the stations work intermittently, channel resources are used irregularly, and utilization rate of the channel resources is reduced. In the 802.11 protocol, a distributed coordination function (distributeddoordinationfunction) mechanism is a basic access mode for data transmission of a node sharing wireless channel, and a CSMA/ca (carrier sense multiple access with connectivity access) technology is applied, and a station monitors a channel state before transmitting data and determines whether to send information according to the channel state, so that the number of collision states in an information transmission process is greatly reduced, and the utilization rate of channel resources is improved. The channel under distributed coordination control can be continuously monitored when being in a busy state, the communication state of the channel can be detected at the first time, and information packets can be immediately sent when the idle state of the channel is detected, so that the idle time of the channel is fully utilized, and the utilization rate of the channel is effectively improved.
The Field Programmable Gate Array (FPGA) has the advantages of rich internal logic resources, strong processing capability of NIOSII soft cores, strong simulation capability, repeatable programming, field modifiable design, complete corresponding EDA (electronic design automation) software functions, rich IP core (interactive performance) resources and the like, and has more advantages compared with the traditional system development method combining a microprocessor and a digital logic unit. The algorithm for realizing the communication protocol by using the FPGA can restore the real data transmission process and show the advantages and the disadvantages of the communication protocol. The FPGA is used as a design main body of a protocol chip by virtue of the characteristics of low operating frequency, low power consumption and the like, and is rapidly developed in the field of communication.
The existing protocol design of the related MAC layer based on FPGA design has the following problems:
1. the signal source part is generated by pseudo random numbers in hardware and does not meet the mathematical distribution of signal source arrival in the protocol algorithm principle;
2. the time slot lengths of different channel states are not controllable, and the implementation process is not accurate;
3. the information packet processing module cannot be controlled according to a protocol control principle, and the error of a design simulation result is larger than a theoretical value.
Disclosure of Invention
The invention aims to provide a wireless network MAC layer distributed coordination system based on FPGA and a construction method thereof, so as to achieve the purpose of improving the utilization rate of channel resources.
The invention provides a wireless network MAC layer distributed coordination system based on FPGA, which is characterized by comprising a data storage module, a time slot control module, an information grouping processing module and a throughput detection module; the data storage module, the time slot control module, the information packet processing module, the signal flow direction between the throughput detection modules is: the poisson data generated in Matlab software is connected with the time slot control module through the data storage module and the initial station, the signal from the time slot control module enters the information processing module through the information station, and then enters the throughput detection module, wherein,
the data storage module is used for storing a poisson data stream generated in Matlab software through a ROM core module in QuartusII and introducing the poisson data into FPGA software;
the time slot control module is used for controlling the time slot length according to two different events in a channel, including an idle event and a busy event, and specifically comprises a feedback signal module written by asynchronous FIFO and Verilog;
the information packet processing module divides two different states in a channel, one information station is regarded as a busy station and an idle station, and the information packet processing module performs skip reading between the two stations according to the different states of the channel, namely the busy state reads data at the busy station and the idle state reads data at the idle station, so that a control mechanism in a protocol algorithm is realized;
and the throughput detection module carries out data statistics by using three counters respectively according to three signals of channel idle, data transmission success and information conflict fed back by the information packet processing module, so as to calculate and obtain a simulated value of the throughput.
Furthermore, the time slot control module comprises an asynchronous FIFO and a counter, when data needing time slot increasing is read, the asynchronous FIFO is stopped from being read and enabled, the counter is triggered to count down, and when the counter counts down to a specified value, the asynchronous FIFO is restored to be read and enabled.
Further, the information grouping processing module designs system stations according to different states in the channel, one station is used as a busy station or an idle station, and the system skips between the busy station and the idle station according to the read real-time state of the channel in the operation process.
Furthermore, the throughput detection module comprises a counter, and according to the data output by the information packet, the data value detected to be successfully sent is added by itself, so that the throughput statistic value of the system is counted.
The invention provides a method for constructing a wireless network MAC layer distributed coordination system based on FPGA, which is characterized by comprising the following steps:
the method comprises the following steps: generating a poisson data stream; generating a poisson data stream by using a poisson function in Matlab, and generating a file which can be read by a ROM module in a Quartus II kernel, so that the poisson data stream is introduced into the Quartus II, and a hardware circuit design system has a data source;
step two: constructing a circuit; according to the requirement of a system output protocol under distributed coordination control, the design is divided into various functional modules, and the functional modules mainly comprise: the system comprises a data storage module, a time slot control module, an information grouping processing module and a throughput detection module, wherein after Poisson data are introduced into Quartus II, a hardware description language Verilog HDL is adopted to compile codes to construct hardcores to realize functions;
step three: simulating a circuit system; according to the arrival rate of information in the system under distributed coordination control and the value of an idle time slot a, the arrival rate G of a Poisson function in Matlab software and the counter value in a time slot control module are adjusted, and the number of successful data transmission, namely the throughput statistic value, is counted through comprehensive simulation.
Step four: circuit system verification; and adjusting the values of G and a, carrying out statistics and sequence diagram analysis on multiple groups of data, and verifying whether the whole system is successfully designed or not according to the comparison between the throughput statistic value and the protocol theoretical value.
The wireless network MAC layer distributed coordination system based on the FPGA and the construction method thereof can generate a Poisson data stream, adjust the time slot length thereof according to different channel states and realize an information source meeting the requirements of a protocol algorithm; the control module controls and feeds back the information of different states of the channel and realizes a protocol algorithm control mechanism in a skip reading mode; the system expansibility realizes a multi-node competition system. In summary, the invention has the following advantages:
the method comprises the following steps of (I) generating a data stream satisfying a Poisson distribution;
(II) the time slot length can be adjusted according to different channel states;
thirdly, a protocol control mechanism can be realized by using a 'skip' module;
the expansibility of the system can be utilized to realize a multi-node competition system;
the information processing module can accurately control according to a protocol algorithm mechanism, a simulation result is basically consistent with a theoretical value, and the transmission process of a protocol system can be accurately realized;
and (VI) the FPGA hardware realizes a communication algorithm protocol, and the invention has the positive effects of being popularized and applied to the fields of wireless networks and the like and improving the utilization rate of channel resources.
Drawings
FIG. 1 is a diagram of a protocol model of the present invention;
FIG. 2 is a schematic structural view of the present invention;
FIG. 3 is a schematic illustration of Poisson data generation according to the present invention;
FIG. 4 is a schematic diagram of the timeslot control module according to the present invention.
Detailed Description
As shown in fig. 1 to 4, the FPGA-based wireless network MAC layer distributed coordination system provided by the present invention includes a data storage module, a timeslot control module, an information packet processing module, and a throughput detection module; the system comprises a data storage module, a time slot length control module, an information grouping processing module and a throughput detection module, wherein the signal flow direction among the throughput detection modules is as follows: poisson data generated in Matlab software is connected with the time slot control module through the data storage module and the initial station, and signals coming out of the time slot control module enter the information processing module through the information station and then enter the throughput detection module.
The data storage module is used for storing the Poisson data stream generated in Matlab software through a ROM core module in QuartusII and introducing the Poisson data into FPGA software.
The time slot control module controls the time slot length according to two different events in the channel, including an idle event and a busy event, and as shown in fig. 4, the time slot control module is specifically composed of a feedback signal module written by an asynchronous FIFO and a Verilog.
The information packet processing module divides two different states in a channel, one information station is regarded as a busy station and an idle station, and the two stations are subjected to skip reading according to the different states of the channel, namely the busy state reads data at the busy station and the idle state reads data at the idle station, so that a control mechanism in a CSMA protocol algorithm is realized.
And the throughput detection module carries out data statistics by using three counters respectively according to three signals of channel idle, data transmission success and information conflict fed back by the information packet processing module, so as to calculate and obtain a simulated value of the throughput.
The invention combines two kinds of software of Matlab and Quartus II, and is characterized in that: the design fully utilizes the design idea of FPGA from top to bottom, and the FPGA-based data processing system is composed of a data storage module, a time slot control module, an information grouping processing module, a throughput detection module and the like. The data storage module and the time slot control module mainly have the functions of storing and controlling the length of the Poisson data stream generated in Matlab software.
The data storage module is composed of a ROM module in Quartus II, and is mainly used for reading data streams generated in Matlab.
The time slot control module mainly comprises an asynchronous FIFO and a counter, when data needing time slot increasing is read, the asynchronous FIFO is stopped from being read and enabled, the counter is triggered to count down, and when the counter counts down to a specified value, the asynchronous FIFO is recovered to be enabled.
The information packet processing module processes according to different states in the channel. In the design of system sites, one site is regarded as a busy site or an idle site, and the system skips reading between the busy site and the idle site (busy or idle) according to the read real-time state of a channel in the operation process.
The throughput detection module consists of a counter; and according to the data output by the information packet, self-adding is carried out when the data value successfully transmitted is detected, so that the throughput statistic value of the system is counted.
The invention provides a method for constructing a wireless network MAC layer distributed coordination system based on FPGA, which comprises the following steps:
the method comprises the following steps: generating a poisson data stream; generating a poisson data stream by using a poisson function in Matlab, and generating a file which can be read by a ROM module in a Quartus II kernel, so that the poisson data stream is introduced into the Quartus II, and a hardware circuit design system has a data source;
step two: constructing a circuit; according to the control output protocol requirement of the system, the design is divided into various functional modules, and the functional modules mainly comprise: the system comprises a data storage module, a time slot control module, an information grouping processing module and a throughput detection module, wherein after Poisson data are introduced into Quartus II, a hardware description language Verilog HDL is adopted to compile codes to construct hardcores to realize functions;
step three: simulating a circuit system; according to the arrival rate of the information in the protocol and the value of the idle time slot a, the arrival rate G of the Poisson function in Matlab software and the counter value in the time slot control module are adjusted, and the number of successful data transmission, namely the throughput statistic value, is counted through comprehensive simulation.
Step four: circuit system verification; and adjusting the values of G and a, carrying out statistics and sequence diagram analysis on multiple groups of data, and verifying whether the whole system is successfully designed or not according to the comparison between the throughput statistic value and the protocol theoretical value.
Claims (5)
1. A wireless network MAC layer distributed coordination system based on FPGA is characterized by comprising a data storage module, a time slot control module, an information grouping processing module and a throughput detection module; the data storage module, the time slot control module, the information packet processing module, the signal flow direction between the throughput detection modules is: the poisson data generated in Matlab software is connected with the time slot control module through the data storage module and the initial station, the signal from the time slot control module enters the information grouping processing module through the information station, and then enters the throughput detection module, wherein,
the data storage module is used for storing a poisson data stream generated in Matlab software through a ROM core module in QuartusII and introducing the poisson data into FPGA software;
the time slot control module is used for controlling the time slot length according to two different events in a channel, including an idle event and a busy event, and specifically comprises a feedback signal module written by asynchronous FIFO and Verilog;
the information packet processing module divides two different states in a channel, one information station is regarded as a busy station and an idle station, and the information packet processing module performs skip reading between the two stations according to the different states of the channel, namely the busy state reads data at the busy station and the idle state reads data at the idle station, so that a control mechanism in a protocol algorithm is realized;
and the throughput detection module carries out data statistics by using three counters respectively according to three signals of channel idle, data transmission success and information conflict fed back by the information packet processing module, so as to calculate and obtain a simulated value of the throughput.
2. The FPGA-based wireless network MAC layer distributed coordination system of claim 1, wherein the time slot control module comprises an asynchronous FIFO and a counter, when reading the data requiring the time slot to become larger, the asynchronous FIFO is stopped from being read and the counter is triggered to count down, and when the counter counts down to a specified value, the asynchronous FIFO is restored to be read.
3. The FPGA-based wireless network MAC layer distributed coordination system as claimed in claim 1, wherein the information packet processing module performs system site design according to different states in a channel, and takes one site as a busy site or an idle site, and the system skips between the busy site and the idle site according to a read real-time state of the channel during operation.
4. The distributed coordination system according to claim 1, wherein said throughput detection module comprises a counter, and said counter performs self-addition when detecting a successfully transmitted data value according to the data outputted from the packet, so as to count the system throughput statistic value.
5. A method for constructing a wireless network MAC layer distributed coordination system based on FPGA is characterized by comprising the following steps:
the method comprises the following steps: generating a poisson data stream; generating a poisson data stream by using a poisson function in Matlab, and generating a file which can be read by a ROM module in a Quartus II kernel, so that the poisson data stream is introduced into the Quartus II, and a hardware circuit design system has a data source;
step two: constructing a circuit; according to the control output protocol requirement of the distributed coordination system, the design is divided into various functional modules, and the functional modules mainly comprise: the system comprises a data storage module, a time slot control module, an information grouping processing module and a throughput detection module, wherein after Poisson data are introduced into Quartus II, a hardware description language Verilog HDL is adopted to compile codes to construct hardcores to realize functions;
step three: simulating a circuit system; according to the arrival rate of the information in the protocol and the value of the idle time slot a, adjusting the arrival rate G of a Poisson function in Matlab software and the counter value in a time slot control module, and counting the number of successful data transmission, namely a throughput statistic value, through comprehensive simulation;
step four: circuit system verification; and adjusting the values of G and a, carrying out statistics and sequence diagram analysis on multiple groups of data, and verifying whether the whole system is successfully designed or not according to the comparison between the throughput statistic value and the protocol theoretical value.
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