CN106981417A - A kind of semiconductor devices and its manufacture method, electronic installation - Google Patents
A kind of semiconductor devices and its manufacture method, electronic installation Download PDFInfo
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- CN106981417A CN106981417A CN201610034509.7A CN201610034509A CN106981417A CN 106981417 A CN106981417 A CN 106981417A CN 201610034509 A CN201610034509 A CN 201610034509A CN 106981417 A CN106981417 A CN 106981417A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 238000000034 method Methods 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000009434 installation Methods 0.000 title claims abstract description 11
- 239000010410 layer Substances 0.000 claims abstract description 233
- 229910052751 metal Inorganic materials 0.000 claims abstract description 140
- 239000002184 metal Substances 0.000 claims abstract description 136
- 239000000463 material Substances 0.000 claims abstract description 86
- 239000011229 interlayer Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 150000004767 nitrides Chemical class 0.000 claims abstract description 31
- 229910052782 aluminium Inorganic materials 0.000 claims description 13
- 239000004411 aluminium Substances 0.000 claims description 13
- -1 dimethylethyl amine aluminium alkane Chemical class 0.000 claims description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- 230000008021 deposition Effects 0.000 claims description 10
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 238000003851 corona treatment Methods 0.000 claims description 4
- 238000011010 flushing procedure Methods 0.000 claims description 4
- 238000002791 soaking Methods 0.000 claims description 4
- 238000010790 dilution Methods 0.000 claims description 3
- 239000012895 dilution Substances 0.000 claims description 3
- 239000007788 liquid Substances 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- 239000002243 precursor Substances 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 238000011049 filling Methods 0.000 abstract description 16
- 229910052581 Si3N4 Inorganic materials 0.000 description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 20
- 239000011248 coating agent Substances 0.000 description 15
- 238000000576 coating method Methods 0.000 description 15
- 238000010276 construction Methods 0.000 description 13
- 238000005229 chemical vapour deposition Methods 0.000 description 10
- 239000000470 constituent Substances 0.000 description 10
- 238000000151 deposition Methods 0.000 description 10
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 238000002955 isolation Methods 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 7
- 238000005530 etching Methods 0.000 description 7
- 229910052719 titanium Inorganic materials 0.000 description 7
- 239000010936 titanium Substances 0.000 description 7
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 5
- 239000007769 metal material Substances 0.000 description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
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- 229910000765 intermetallic Inorganic materials 0.000 description 4
- IATRAKWUXMZMIY-UHFFFAOYSA-N strontium oxide Chemical compound [O-2].[Sr+2] IATRAKWUXMZMIY-UHFFFAOYSA-N 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 3
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- 229910052707 ruthenium Inorganic materials 0.000 description 3
- 229910018509 Al—N Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 2
- WUNIMIODOAGQAW-UHFFFAOYSA-N [O-2].[Ba+2].[Ti+4] Chemical compound [O-2].[Ba+2].[Ti+4] WUNIMIODOAGQAW-UHFFFAOYSA-N 0.000 description 2
- DBOSVWZVMLOAEU-UHFFFAOYSA-N [O-2].[Hf+4].[La+3] Chemical compound [O-2].[Hf+4].[La+3] DBOSVWZVMLOAEU-UHFFFAOYSA-N 0.000 description 2
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 description 2
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- INIGCWGJTZDVRY-UHFFFAOYSA-N hafnium zirconium Chemical compound [Zr].[Hf] INIGCWGJTZDVRY-UHFFFAOYSA-N 0.000 description 2
- ZQXQADNTSSMHJI-UHFFFAOYSA-N hafnium(4+) oxygen(2-) tantalum(5+) Chemical compound [O-2].[Ta+5].[Hf+4] ZQXQADNTSSMHJI-UHFFFAOYSA-N 0.000 description 2
- KQHQLIAOAVMAOW-UHFFFAOYSA-N hafnium(4+) oxygen(2-) zirconium(4+) Chemical compound [O--].[O--].[O--].[O--].[Zr+4].[Hf+4] KQHQLIAOAVMAOW-UHFFFAOYSA-N 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- OLBVUFHMDRJKTK-UHFFFAOYSA-N [N].[O] Chemical compound [N].[O] OLBVUFHMDRJKTK-UHFFFAOYSA-N 0.000 description 1
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- GPBUGPUPKAGMDK-UHFFFAOYSA-N azanylidynemolybdenum Chemical compound [Mo]#N GPBUGPUPKAGMDK-UHFFFAOYSA-N 0.000 description 1
- 239000004567 concrete Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 229910001195 gallium oxide Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910000476 molybdenum oxide Inorganic materials 0.000 description 1
- VIKNJXKGJWUCNN-XGXHKTLJSA-N norethisterone Chemical group O=C1CC[C@@H]2[C@H]3CC[C@](C)([C@](CC4)(O)C#C)[C@@H]4[C@@H]3CCC2=C1 VIKNJXKGJWUCNN-XGXHKTLJSA-N 0.000 description 1
- PQQKPALAQIIWST-UHFFFAOYSA-N oxomolybdenum Chemical compound [Mo]=O PQQKPALAQIIWST-UHFFFAOYSA-N 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000011513 prestressed concrete Substances 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention provides a kind of semiconductor devices and its manufacture method, electronic installation, and methods described includes：There is provided and be formed with interlayer dielectric layer and the groove in interlayer dielectric layer in Semiconductor substrate, the Semiconductor substrate, the groove exposes the Semiconductor substrate；High k dielectric layer and workfunction setting metal layer are sequentially formed in the side wall of groove and bottom；Metal gate material layer is formed, groove is filled up completely with；The high k dielectric layer of etch-back and workfunction setting metal layer；Etch-back metal gate material layer；Deposited metal nitride layer, wraps up the metal gate material layer exposed；Another interlayer dielectric layer is formed, and the contact hole for exposing source/drain region and metal nitride layer is formed in interlayer dielectric layer.According to the present invention it is possible to reduce the thickness that metal gate material layer is removed by etch-back, and then reduce the resistance of metal gates, realize good gap filling.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of semiconductor devices and its manufacture method, electronic installation.
Background technology
In the manufacturing process of next generation's integrated circuit, for the making of the grid of field-effect transistor, generally using high k- metal gate process.For the field-effect transistor with compared with fractional value process node, the high k- metal gate process is usually post tensioned unbonded prestressed concrete technique, and its implementation process is two kinds of metal gates after metal gates after first high k dielectric layer and rear high k dielectric layer.
First the implementation process of metal gate process includes after high k dielectric layer：Dummy gate structure is formed on a semiconductor substrate, and the dummy gate structure is made up of the boundary layer being laminated from bottom to top, high k dielectric layer, coating (capping layer) and sacrificial gate material layer；Side wall construction is formed in the both sides of dummy gate structure, remove afterwards in the sacrificial gate material layer in dummy gate structure, the groove left between side wall construction and be sequentially depositing barrier layer (barrier layer), workfunction layers (workfunction metal layer) and soakage layer (wetting layer)；Carry out the filling of metal gate material (being usually aluminium).
The implementation process of metal gate process includes after high k dielectric layer afterwards：Dummy gate structure is formed on a semiconductor substrate, and the dummy gate structure is made up of sacrificial gate dielectric layer and the sacrificial gate material layer being laminated from bottom to top；Side wall construction is formed in the both sides of dummy gate structure, remove afterwards in the sacrificial gate dielectric layer and sacrificial gate material layer in dummy gate structure, the groove left between side wall construction and be sequentially depositing boundary layer, high k dielectric layer, coating, barrier layer, workfunction layers and soakage layer；Carry out the filling of metal gate material.
, it is necessary to the coating at the top of covering metal gate material be formed, in favor of the making of follow-up self-aligned contacts after the filling of completion metal gate material.Prior art is using material of the silicon nitride as the coating at the top of covering metal gate material, but, because the material etch of silicon nitride and interlayer dielectric layer selects the limitation of ratio, need the metal gate material that etch-back is more, the thicker nitridation silicon covering layer of filling, thereby results in that metal gates resistance is too high and silicon nitride layer of filling be present.
It is, therefore, desirable to provide a kind of method, to solve the above problems.
The content of the invention
In view of the shortcomings of the prior art, the present invention provides a kind of manufacture method of semiconductor devices, including：
There is provided and be formed with interlayer dielectric layer and the groove in the interlayer dielectric layer in Semiconductor substrate, the Semiconductor substrate, the groove exposes the Semiconductor substrate；
High k dielectric layer and workfunction setting metal layer are sequentially formed in the side wall of the groove and bottom；
Metal gate material layer is formed, to be filled up completely with the groove；
High k dielectric layer described in etch-back and the workfunction setting metal layer reserve the gap of deposited metal nitride layer；
Metal gate material layer described in etch-back, makes the top of the metal gate material layer be less than the top of the interlayer dielectric layer；
Implement the deposition of the metal nitride layer, to wrap up the metal gate material exposed layer.
In one example, hydrofluoric acid and hydrogen peroxide of the corrosive liquid of etch-back for dilution are implemented to the high k dielectric layer and the workfunction setting metal layer.
In one example, the etch-back to metal gate material layer is reactive ion etching.
In one example, implement after the etch-back to metal gate material layer, the top of the metal gate material layer is higher than the high k dielectric layer and the top of the workfunction setting metal layer.
In one example, the metal nitride layer includes AlN layers.
In one example, the precursor for depositing described AlN layers is dimethylethyl amine aluminium alkane, and temperature is less than 350 degrees Celsius.
In one example, by circulating the dimethylethyl amine aluminium alkane soaking flushing implemented successively and NH3/N2Corona treatment, the making of described AlN layers of completion.
In one example, the step of after the deposition for implementing the metal nitride layer, in addition to forming another interlayer dielectric layer, and the contact hole for exposing source/drain region and the metal nitride layer formed in the interlayer dielectric layer.
In one embodiment, the present invention also provides a kind of semiconductor devices of use above method manufacture.
In one embodiment, the present invention also provides a kind of electronic installation, and the electronic installation includes the semiconductor devices.
According to the present invention it is possible to reduce the thickness that the metal gate material layer is removed by etch-back, and then reduce the resistance of metal gates, realize good gap filling.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of embodiments of the invention and its description, for explaining the principle of the present invention.
In accompanying drawing：
Figure 1A-Fig. 1 H are the schematic cross sectional view of the device obtained respectively the step of implementation successively according to the method for exemplary embodiment of the present one；
Fig. 2 is flow chart the step of implementation successively according to the method for exemplary embodiment of the present one.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.It is, however, obvious to a person skilled in the art that the present invention can be carried out without one or more of these details.In other examples, in order to avoid obscuring with the present invention, it is not described for some technical characteristics well known in the art.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to embodiments presented herein.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.Same reference numerals represent identical element from beginning to end.
It is understood that, be referred to as when element or layer " ... on ", " with ... it is adjacent ", " being connected to " or when " being coupled to " other elements or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or there may be element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other elements or layer, then in the absence of element or layer between two parties.Although it should be understood that term first, second, third, etc. can be used to describe various elements, part, area, floor and/or part, these elements, part, area, floor and/or part should not be limited by these terms.These terms are used merely to distinguish an element, part, area, floor or part and another element, part, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, part, area, floor or part be represented by the second element, part, area, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " below ", " ... under ", " ... on ", " above ", can describe for convenience herein and by using so as to the element or feature shown in description figure and other elements or the relation of feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term is intended to also including the use of the different orientation with the device in operation.If for example, the device upset in accompanying drawing, then, be described as " below other elements " or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary term " ... below " and " ... under " may include it is upper and lower two orientation.Device can be additionally orientated and (be rotated by 90 ° or other orientations) and spatial description language as used herein is correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Herein in use, " one " of singulative, " one " and " described/should " be also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that term " composition " and/or " comprising ", when using in this specification, the presence of the feature, integer, step, operation, element and/or part is determined, but is not excluded for the presence or addition of one or more other features, integer, step, operation, element, part and/or group.Herein in use, term "and/or" includes any and all combination of related Listed Items.
In the manufacturing process of next generation's integrated circuit, for the making of the grid of field-effect transistor, generally using high k- metal gate process., it is necessary to the coating at the top of covering metal gate material be formed, in favor of the making of follow-up self-aligned contacts after filling metal gate material in the groove that removal dummy gate structure leaves.Prior art is using material of the silicon nitride as the coating at the top of covering metal gate material, but, because the material etch of silicon nitride and interlayer dielectric layer selects the limitation of ratio, need the metal gate material that etch-back is more, the thicker nitridation silicon covering layer of filling, thereby results in that metal gates resistance is too high and silicon nitride layer of filling be present.
In order to solve the above problems, as shown in Fig. 2 the invention provides a kind of manufacture method of semiconductor devices, this method includes：
In step 201 there is provided Semiconductor substrate, dummy gate structure, including the sacrifice gate dielectric layer and sacrificial gate dielectric layer being laminated from bottom to top are formed with a semiconductor substrate；
In step 202., interlayer dielectric layer is formed on a semiconductor substrate, to fill the gap between dummy gate structure；
In step 203, dummy gate structure is removed, groove is formed；
In step 204, high k dielectric layer and workfunction setting metal layer are sequentially formed in the side wall of groove and bottom；
In step 205, metal gate material layer is formed, to be filled up completely with groove；
In step 206, the high k dielectric layer of etch-back and workfunction setting metal layer；
In step 207, etch-back metal gate material layer；
In a step 208, deposited metal nitride layer, to wrap up the metal gate material exposed layer.
Metal nitride selection is compared to silicon nitride with higher etching selection rate and more easily in the material of metal gates deposited atop, such as AlN.AlN is far longer than silicon nitride relative to the etching selection rate for the oxide for constituting interlayer dielectric layer, and it is easier to be deposited on the top of metal gates relative to silicon nitride, while it also has good space filling capacity, is adapted as the coating at the top of metal gates.
According to the manufacture method of semiconductor devices proposed by the present invention, implementation steps 206 are to reserve the gap of deposited metal nitride layer, implementation steps 207 are so that the top of metal gate material layer is less than the top of interlayer dielectric layer, because metal nitride layer is thinner relative to what silicon nitride can be formed, therefore the thickness that the metal gate material layer is removed by etch-back can be reduced in step 207, and then reduces the resistance of metal gates；Implementation steps 208, deposited metal nitride layer can realize good gap filling.
Also include after step 208 in step 209, form another interlayer dielectric layer, and the contact hole for exposing source/drain region and metal nitride layer is formed in interlayer dielectric layer.
In order to thoroughly understand the present invention, detailed structure and/or step will be proposed in following description, to explain technical scheme proposed by the present invention.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, the present invention can also have other embodiment.
[exemplary embodiment one]
Reference picture 1A- Fig. 1 H, the schematic cross sectional view for the device that the step of method that illustrated therein is according to an exemplary embodiment of the present one is implemented successively obtains respectively.
First, as shown in Figure 1A there is provided Semiconductor substrate 100, the constituent material of Semiconductor substrate 100 can use undoped with monocrystalline silicon, the monocrystalline silicon doped with impurity, silicon-on-insulator (SOI) etc..As an example, in the present embodiment, Semiconductor substrate 100 is constituted from single crystal silicon material.
Isolation structure is formed with Semiconductor substrate 100, as an example, isolation structure, which is shallow trench, isolates (STI) structure or selective oxidation silicon (LOCOS) isolation structure.100 points of Semiconductor substrate is different transistor areas by isolation structure, for example, isolation structure by Semiconductor substrate 100 points be PMOS areas and nmos area.Various traps (well) structure is also formed with Semiconductor substrate 100, to put it more simply, being omitted in diagram.
Dummy gate structure 102 is formed with a semiconductor substrate 100, and as an example, dummy gate structure 102 may include the sacrifice gate dielectric layer 102a being laminated from bottom to top and sacrificial gate dielectric layer 102b.
Sacrifice gate dielectric layer 102a material preferred oxides, such as silica.Sacrificial gate dielectric layer 102b material includes polysilicon or amorphous carbon, particularly preferably polysilicon.Sacrifice any prior art that gate dielectric layer 102a and sacrificial gate dielectric layer 102b forming method can be familiar with using those skilled in the art, it is preferred that chemical vapour deposition technique (CVD), such as low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD).
In addition, as an example, be formed with side wall construction 103 in the both sides of dummy gate structure 102, wherein, side wall construction 103 at least includes oxide skin(coating) and/or nitride layer.The method for forming side wall construction 103 is known to those skilled in the art, is not repeated here herein.
Source/drain region is formed with the Semiconductor substrate 100 of the both sides of side wall construction 103, embedded carbon silicon layer and embedded germanium silicon layer are respectively formed with the source/drain region positioned at nmos area and PMOS areas.As a rule, the U-shaped profile of embedded carbon silicon layer, the cross section of embedded germanium silicon layer is in ∑ shape, with the carrier mobility for the channel region for further enhancing nmos area and PMOS areas, to put it more simply, being omitted in diagram.The technical process for forming embedded carbon silicon layer and embedded germanium silicon layer is familiar with by those skilled in the art, is not repeated here herein.
Next, interlayer dielectric layer 105 is formed on a semiconductor substrate 100, covering dummy gate structure 102 and side wall construction 103.Then, cmp is performed, until exposing the top of dummy gate structure 102.
Before interlayer dielectric layer 105 is formed, contact etch stop layer 104, covering dummy gate structure 102 and side wall construction 103 can also be formed on a semiconductor substrate 100.The various suitable techniques being familiar with using those skilled in the art form contact etch stop layer 104 and interlayer dielectric layer 105 respectively, for example, using conformal deposition process formation contact etch stop layer 104, using chemical vapor deposition method formation interlayer dielectric layer 105, wherein, silicon nitride (SiN) may be selected in the material of contact etch stop layer 104, and oxide may be selected in the material of interlayer dielectric layer 105.
Then, as shown in Figure 1B, dummy gate structure 102 is removed, groove is formed.As an example, by implementing dry etching, sacrificial gate dielectric layer 102b being removed successively and gate dielectric layer 102a is sacrificed.The technological parameter of the dry etching includes：Etching gas HBr flow is 20-500sccm, and pressure is 2-40mTorr, and power is 100-2000W, and wherein mTorr represents milli millimetres of mercury, and sccm represents cc/min.
After the dry etching is implemented, etch residues and impurity that the dry etching is produced are removed using wet etching process.
Then, as shown in Figure 1 C, high k dielectric layer 107 is formed in the side wall of groove and bottom.The k values (dielectric constant) of high k dielectric layer 107 are usually more than 3.9, its constituent material includes hafnium oxide, hafnium silicon oxide, nitrogen oxidation hafnium silicon, hafnium oxide tantalum, hafnium oxide zirconium, nitrogen oxidation hafnium zirconium, hafnium oxide lanthanum, lanthana, lanthana silicon, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminum oxide, alumina silicon, the suitable material that silicon nitride, oxynitride etc. can be formed by chemical vapor deposition, ald or physical gas-phase deposition.
Next, forming workfunction setting metal layer 108 in high k dielectric layer 107.For the PMOS areas of device, workfunction setting metal layer 108 includes one or more layers metal or metallic compound, its constituent material is carbide, nitride of the metal material suitable for PMOS, including titanium, ruthenium, palladium, platinum, tungsten and its alloy, in addition to above-mentioned metallic element etc..For the nmos area of device, workfunction setting metal layer 108 includes one or more layers metal or metallic compound, its constituent material is carbide, nitride of the metal material suitable for NMOS, including titanium, tantalum, aluminium, zirconium, hafnium and its alloy, in addition to above-mentioned metallic element etc..
In addition, being formed before high k dielectric layer 107, boundary layer 106 is formed in the bottom of groove.The constituent material of boundary layer 106 includes the suitable material that thermal oxide, nitrogen oxides, chemical oxide etc. can be formed by handling process in chemical vapor deposition, ald or stove, and the effect for forming boundary layer 106 is to improve the interfacial characteristics between the high k dielectric layer 107 being subsequently formed and Semiconductor substrate 100.Then, annealing is implemented, to improve the surface characteristic of boundary layer 106, this helps to form the high k dielectric layer 107 with good conformability on boundary layer 106.
In addition, formed in high k dielectric layer 107 before workfunction setting metal layer 108, form coating, the constituent material of coating includes lanthana, aluminum oxide, gallium oxide, indium oxide, molybdenum oxide ramet, oxygen nitrogen ramet, tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride, platinum, ruthenium, iridium etc. can be by the suitable material of chemical vapor deposition, ald or physical gas-phase deposition formation, and the effect for forming coating is to prevent diffusion of the metal material in the metal gate material layer 109 that is subsequently formed to high k dielectric layer 107.
Then, as shown in figure iD, metal gate material layer 109 is formed, to be filled up completely with groove.The material of metal gate material layer includes the suitable material that tungsten, aluminium etc. can be formed by chemical vapor deposition, ald or physical gas-phase deposition.
In addition, formed before metal gate material layer 109, soakage layer is formed on workfunction setting metal layer 108, the material of soakage layer includes titanium or titanium-aluminium alloy, the effect for forming soakage layer is to improve the interfacial characteristics between workfunction setting metal layer 108 and metal gate material layer 109.
Then, as referring to figure 1E, the high k dielectric layer 107 of etch-back and workfunction setting metal layer 108.As an example, hydrofluoric acid and hydrogen peroxide of the corrosive liquid of the etch-back for dilution.Implement after the etch-back, not exclusively expose metal gate material layer 109, the soakage layer for during implementing the etch-back, be formed at the coating between high k dielectric layer 107 and workfunction setting metal layer 108, being formed at workfunction setting metal layer 108 between metal gate material layer 109 is also synchronously etched.
Then, as shown in fig. 1F, etch-back metal gate material layer 109.As an example, implementing the etch-back using reactive ion etching process.Implement after the etch-back, the top of metal gate material layer 109 is higher than the top of high k dielectric layer 107 and workfunction setting metal layer 108.
Then, as shown in Figure 1 G, deposited metal nitride layer 110, to wrap up the metal gate material exposed layer 109.
The material selection for constituting metal nitride layer 110 compares silicon nitride with higher etching selection rate and more easily in the material of metal gates deposited atop, such as AlN.AlN is far longer than silicon nitride relative to the etching selection rate for the oxide for constituting interlayer dielectric layer, and it is easier to be deposited on the top of metal gates relative to silicon nitride, while it also has good space filling capacity, is adapted as the coating at the top of metal gates.
Using AlN as example, the precursor of the deposition is dimethylethyl amine aluminium alkane, by circulating the dimethylethyl amine aluminium alkane soaking flushing implemented successively and NH3/N2Corona treatment, completes the making of metal nitride layer 110.
Because the bond energy of Al-N coordinate bonds is relatively low, therefore, dimethylethyl amine aluminium alkane can just be decomposed when temperature is less than 350 degrees Celsius, and the AlN decomposited is easy to be attached on metal gate material layer 109 and be not easy to be attached on insulator, so as to realize that gapless is deposited.
Then, as shown in fig. 1H, interlayer dielectric layer 105 is formed again, covers Semiconductor substrate 100.Then, the contact hole 111 for exposing source/drain region and AlN layers 110 is formed in interlayer dielectric layer 105.As an example, using anisotropic dry etching formation contact hole 111.
So far, the processing step that according to an exemplary embodiment of the present one method is implemented is completed.It is understood that the present embodiment manufacturing method of semiconductor device not only include above-mentioned steps, before above-mentioned steps, among or may also include other desired step afterwards, it is included in the range of this implementation preparation method.
Compared with the prior art, according to the proposed method, by forming metal nitride layer 110, the thickness of the coating at the top of covering metal gate material layer 109 can be reduced, reduce the thickness that metal gate material layer 109 is removed by etch-back, and then reducing the resistance of metal gates, metal nitride layer 110 is easy to be attached on metal gate material layer 109 and be not easy to be attached on interlayer dielectric layer 105, so as to realize good gap filling.
[exemplary embodiment two]
The semiconductor devices that the processing step implemented first there is provided according to an exemplary embodiment of the present one method is obtained, as shown in fig. 1H, including：Semiconductor substrate 100, isolation structure and various traps (well) structure are formed with Semiconductor substrate 100, as an example, isolation structure, which is shallow trench, isolates (STI) structure or selective oxidation silicon (LOCOS) isolation structure.
High k- metal gate structures on a semiconductor substrate 100 are formed, as an example, the high k- metal gate structures include boundary layer 106, high k dielectric layer 107, workfunction setting metal layer 108 and the metal gate material layer 109 being laminated from bottom to top.
The constituent material of boundary layer 106 includes the suitable material that thermal oxide, nitrogen oxides, chemical oxide etc. can be formed by handling process in chemical vapor deposition, ald or stove, and the effect for forming boundary layer 106 is to improve the interfacial characteristics between the high k dielectric layer 107 being subsequently formed and Semiconductor substrate 100.
The k values (dielectric constant) of high k dielectric layer 107 are usually more than 3.9, its constituent material includes hafnium oxide, hafnium silicon oxide, nitrogen oxidation hafnium silicon, hafnium oxide tantalum, hafnium oxide zirconium, nitrogen oxidation hafnium zirconium, hafnium oxide lanthanum, lanthana, lanthana silicon, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminum oxide, alumina silicon, the suitable material that silicon nitride, oxynitride etc. can be formed by chemical vapor deposition, ald or physical gas-phase deposition.
For the PMOS areas of device, workfunction setting metal layer 108 includes one or more layers metal or metallic compound, its constituent material is carbide, nitride of the metal material suitable for PMOS, including titanium, ruthenium, palladium, platinum, tungsten and its alloy, in addition to above-mentioned metallic element etc..For the nmos area of device, workfunction setting metal layer 108 includes one or more layers metal or metallic compound, its constituent material is carbide, nitride of the metal material suitable for NMOS, including titanium, tantalum, aluminium, zirconium, hafnium and its alloy, in addition to above-mentioned metallic element etc..
The metal nitride layer 110 of coated metal gate material layers 109, the material selection for constituting metal nitride layer 110 compares silicon nitride with higher etching selection rate and more easily in the material of metal gates deposited atop, such as AlN.AlN is far longer than silicon nitride relative to the etching selection rate for the oxide for constituting interlayer dielectric layer, and it is easier to be deposited on the top of metal gates relative to silicon nitride, while it also has good space filling capacity, is adapted as the coating at the top of metal gates.
Using AlN as example, by circulating the dimethylethyl amine aluminium alkane soaking flushing implemented successively and NH3/N2Corona treatment, completes the making of metal nitride layer 110.
Because the bond energy of Al-N coordinate bonds is relatively low, therefore, dimethylethyl amine aluminium alkane can just be decomposed when temperature is less than 350 degrees Celsius, and the AlN decomposited is easy to be attached on metal gate material layer 109 and be not easy to be attached on insulator, so as to realize that gapless is filled.
The side wall construction 103 positioned at the high k- metal gate structures both sides on a semiconductor substrate 100 is formed, side wall construction 103 is made up of oxide, nitride or combination.
Interlayer dielectric layer 105 on a semiconductor substrate 100 is formed, interlayer dielectric layer 105 covers the high k- metal gate structures and side wall construction 103；The contact hole 111 in interlayer dielectric layer 105 is formed, exposes the top of AlN layers 110 and the top for the source/drain region being formed in Semiconductor substrate 100.
Then, the making of whole semiconductor devices is completed by subsequent technique, including：Self-aligned silicide is formed in the bottom of contact hole 111；Filling metal (being usually tungsten) forms the contact plug of interconnecting metal layer and the self-aligned silicide that connection is subsequently formed in contact hole 111；Multiple interconnecting metal layers are formed, are generally completed using dual damascene process；Form metal pad, wire bonding when being encapsulated for subsequent implementation device.
[exemplary embodiment three]
The present invention also provides a kind of electronic installation, and it includes according to an exemplary embodiment of the present two semiconductor devices.The electronic installation can be any electronic product such as mobile phone, tablet personal computer, notebook computer, net book, game machine, television set, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment or any include the intermediate products of the semiconductor devices.The electronic installation, due to having used the semiconductor devices, thus with better performance.
The present invention is illustrated by above-described embodiment, but it is to be understood that, the purpose that above-described embodiment is only intended to illustrate and illustrated, and be not intended to limit the invention in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the invention is not limited in above-described embodiment, more kinds of variants and modifications can also be made according to the teachings of the present invention, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention is defined by the appended claims and its equivalent scope.
Claims (10)
1. a kind of manufacture method of semiconductor devices, it is characterised in that including：
There is provided and be formed with interlayer dielectric layer and positioned at institute in Semiconductor substrate, the Semiconductor substrate
The groove in interlayer dielectric layer is stated, the groove exposes the Semiconductor substrate；
High k dielectric layer and work function setting gold are sequentially formed in the side wall of the groove and bottom
Belong to layer；
Metal gate material layer is formed, to be filled up completely with the groove；
High k dielectric layer described in etch-back and the workfunction setting metal layer, reserve deposited metal
The gap of nitride layer；
Metal gate material layer described in etch-back, is less than the top of the metal gate material layer
The top of the interlayer dielectric layer；
Implement the deposition of the metal nitride layer, to wrap up the metal gate material exposed
Layer.
2. according to the method described in claim 1, it is characterised in that to the high k dielectric
Layer and the workfunction setting metal layer implement etch-back corrosive liquid for dilution hydrofluoric acid and
Hydrogen peroxide.
3. according to the method described in claim 1, it is characterised in that to the metal gates
The etch-back of material layer is reactive ion etching.
4. according to the method described in claim 1, it is characterised in that implement to the metal
After the etch-back of gate material layers, the top of the metal gate material layer is higher than the high k
The top of dielectric layer and the workfunction setting metal layer.
5. according to the method described in claim 1, it is characterised in that the metal nitride
Layer includes AlN layers.
6. method according to claim 5, it is characterised in that described AlN layers of deposition
Precursor be dimethylethyl amine aluminium alkane, temperature be less than 350 degrees Celsius.
7. method according to claim 5, it is characterised in that real successively by circulation
The dimethylethyl amine aluminium alkane soaking flushing and NH applied3/N2Corona treatment, completes institute
State AlN layers of making.
8. according to the method described in claim 1, it is characterised in that implement the metal nitrogen
After the deposition of compound layer, in addition to another interlayer dielectric layer is formed, and in the interlayer dielectric
The step of contact hole for exposing source/drain region and the metal nitride layer is formed in layer.
9. the semiconductor devices of the method manufacture described in a kind of one of use claim 1-8.
10. a kind of electronic installation, it is characterised in that the electronic installation includes claim 9
Described semiconductor devices.
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