CN106952890A - A kind of the PUF schemes and circuit realiration of the principle that fused based on chip internal wire - Google Patents
A kind of the PUF schemes and circuit realiration of the principle that fused based on chip internal wire Download PDFInfo
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- CN106952890A CN106952890A CN201710177271.8A CN201710177271A CN106952890A CN 106952890 A CN106952890 A CN 106952890A CN 201710177271 A CN201710177271 A CN 201710177271A CN 106952890 A CN106952890 A CN 106952890A
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- circuit connection
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- puf
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09C—CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY
- G09C1/00—Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
- H01L2223/5444—Marks applied to semiconductor devices or parts containing identification or tracking information for electrical read out
Abstract
The present invention has put forward a kind of PUF schemes based on chip internal wire fusing principle and its physical circuit is realized.Selection chip internal has positive temperature coefficient material, in chip internal formation M（M is more than or equal to 1）Group circuit connection, and select N number of position on every group of circuit connection（N is more than or equal to 2）, position at the N is deliberately designed as than feature sizes are more tiny at other positions on circuit connection so that bigger at the resistance ratio other positions of position at the N.Add suitable voltage at circuit connection two ends, so that the electric current of suitable size flows through from circuit connection, circuit connection is generated heat, because the larger heating of resistance is more serious at thinner point, fused first at relatively large that of resistance in the comparatively fine position of feature sizes at final N.Using the discreteness of chip manufacturing process, the position of striking point is random on every circuit connection, realizes a kind of unclonable functional foundations of reliable and stable physics.
Description
Technical field：
The invention mainly relates to electronic installation uniqueness authentication techniques field, a kind of new thing realized in chip internal is refered in particular to
Manage unclonable function（PUF）.Using the natural differences of chip manufacturing process, a kind of unpredictable, not reproducible, nothing is realized
The chip " fingerprint " of human intervention.
Background technology：
Physics unclonable function（Physical Unclonable Function, abbreviation PUF）Earliest by Pappu in 2001
Propose design, it is intended to solve the uniqueness Verify Your Identity questions of electronic installation.As everyone has different biological characteristics（Such as refer to
Line, iris, voice etc.）As the discrimination factor of identification, electronic installation also be intended to find it is a kind of inherent intrinsic, without artificial
The feature of intervention as individual uniqueness difference, to realize the identification of electronic installation.
With integrated circuit（Integrated Circuit, abbreviation IC or chip）The high speed development of technology, based on chip
PUF be implemented as study hotspot.By using process deviation is inevitably produced in chip manufacturing proces, so as to obtain
Take a kind of unique, unpredictable, not reproducible possibility.In this, as logical foundations, by necessary logical process, shape
Into the digitized unique identities characteristic information of one single chip.Even chip manufacturer, using same manufacturing equipment, can not yet
Repeat to realize duplicate microcosmic manufacturing condition completely, it is impossible to copy two duplicate cores of identity characteristic information
Piece, greatly improves the level of security of electronic installation identification.
Occurred many PUF circuit structures based on chip in recent years.With circuit delay otherness, and without reset control
Latch initial value uncertainty principle be Typical Representative, realize such as loop oscillator frequecy characteristic, SRAM's
PUF structures of original state feature etc..The shortcoming of such PUF structures is that stability is poor, and chip is in different voltages, different temperatures bar
Under part, same chip may show different features, and the uniqueness of identification is relatively difficult to ensure card.
Need it is a kind of only sensitive to chip manufacturing process, to chip operating temperature, the insensitive PUF of the environmental factor such as voltage
Structure.To realize that different chips can obtain unique, different characteristic informations in the fabrication process, and this characteristic information is in core
With regard to stable existence after the completion of piece manufacture, do not influenceed by chip operation environment.
The content of the invention：
It is an object of the invention to provide a kind of new PUF organization plans and its circuit of the principle that fused based on chip internal wire
Realize, to solve the instability problem that traditional PUF is caused to working environment sensitivity.
The problem of present invention is solves described in technical background, the technical scheme used is realized：
A kind of PUF schemes and its physical circuit based on chip internal wire fusing principle are realized.Selecting chip internal has just
Warm coefficient material, in chip internal formation M（M is more than or equal to 1）The circuit connection of group suitable width, thickness and length, and every
N number of position is selected on group circuit connection（N is more than or equal to 2）, position at the N is deliberately designed as than other positions on circuit connection
Locate feature sizes more tiny so that bigger at the resistance ratio other positions of position at the N.Add suitably at circuit connection two ends
Voltage so that the electric current of suitable size flows through from circuit connection, makes circuit connection generate heat, due to the larger hair of resistance at thinner point
Heat is more serious, and temperature can be higher herein, then causes resistance further to become big, and heating is more serious, feature sizes at final N
Fused first at relatively large that of resistance in comparatively fine position, circuit connection open circuit is flowed through, circuit there is no electric current
Line other positions keep connective constant.Using the discreteness of chip manufacturing process, M bar circuit connections during manufacture per chips
The otherness that upper N multiplies the resistance of the relatively fine position of size at M is in random distribution.On every circuit connection the position of striking point with
Connected state after machine, and fusing is stablized relatively, characterizes unpredictable, the not reproducible uniqueness of chip in itself, realizes
A kind of unclonable functional foundations of reliable and stable physics.
The PUF schemes and circuit realiration of a kind of described principle that fused based on chip internal wire, it is characterised in that：
As shown in figure 1, electrically conductive and with positive temperature coefficient using chip internal（Become big with temperature rise resistance）Material exist
Chip internal designs the conductive circuit connection of a suitable width, length and thickness（Wire）.Looked on circuit connecting wire
To at suitable N（N is more than or equal to 2）Position, by the connection line size at these location points（Width dimensions, or thickness, or
Width and thickness）It is designed to more tiny than line other positions.
Apply suitable voltage at the two ends of circuit connection, make there is the electric current of suitable size to flow through on circuit connection, and make
Circuit connection generates heat；Because fine size position local electrical resistance is bigger than other positions at N, so temperature is relative at these positions
Other positions are higher；Due to the positive temperature coefficient characteristic of circuit connection material, these fine size position local electrical resistances are caused to enter one
Step rise, a positive feedback is formed with this.
By to select suitably sized value at fine position, selecting suitable conducting electric current, by controlling heating temp,
Circuit connection fine size position may finally be fused；Fine size position is in series relationship at N on one circuit connection, only
Want position at one to be fused by high temperature, then whole piece circuit connection is off, then do not have electric current and flowed through again from circuit connection.
Due to the inevitable otherness of chip manufacturing process, N number of fine position size will not be complete on a circuit connection
Exactly the same, heating temp is also differed when electric current flows through, and it is uncertain to cause the position being finally blown, and can not be reappeared
, and once after fusing, state is small by chip operation environmental factor.
Only have fine position at one under maximum probability to be blown, by detecting that fine position is distinguished at N on circuit connection
Whether fuse, the 1 ~ N position encoded information of N kinds can be obtained；It is possible that multiple positions are blown under minimum probability, pass through
Logical process, can obtain the additional coding information beyond N kinds coding.
On the basis of above description, as shown in Fig. 2 M groups can be designed in chip（M is more than or equal to 1）Described spy
The circuit connection of property.Suitable voltage is added to every group of circuit connection two ends at the same time or separately, suitable current is flowed through every group of circuit company
Line, by detecting fusing positional information, can obtaining at least N, to multiply M kinds unpredictable, can not reappear, unique coding information；Enter
One step, appropriate selection N and M size realizes sufficiently large space encoder.
The advantage of the invention is that：
1. the PUF schemes based on chip internal wire fusing principle provide a kind of only to chip manufacturing processing technology for chip
Minor deviations are sensitive, to voltage, temperature, and the chip operation environment such as humidity is extremely insensitive, can characterize chip uniqueness difference naturally
The implementation of property.
2. relative at present it is common based on unit be delayed and latch initial value theorem PUF, its characteristic more stablize,
It is reliable.
3. implementation is simple.
Brief description of the drawings：
Fig. 1 is single conductor of the present invention fusing PUF general principles
Fig. 2 is PUF scheme of the present invention based on chip internal wire fusing principle
Fig. 3 is a kind of PUF implementations for the principle that fused based on chip internal wire of the present invention
Specific implementation：
To enable the above objects, features and advantages of the present invention more obvious understandable, below in conjunction with the accompanying drawings to the tool of the present invention
Body embodiment is described in detail.
Referring to Fig. 3, set of circuits line is designed using its plain conductor in chip internal, and devises thereon T1 ~ T4
The tiny place of size everywhere, the two ends of wire respectively by two switch Sp and Sn and analog power VCC and simulation VSS be connected,
The suitable supply voltage value between VCC and VSS is selected, can be by the tiny place of size on wire within the suitable time that is powered
Fusing, and the chip that wire other positions and wire are depended on is unaffected in itself；The centre of wire is by switching Kp and logic
Power vd D is connected, and T1 ~ T4 is connected by Kn1 ~ Kn4 with logically GNG respectively at each size fine position, VDD and GND it
Between the voltage of chip internal logical device work that is depended on by wire of power supply.The unclonable letter of physics is obtained in order to realize
Breath coding, it is necessary to complete following steps：1, Sp and Sn is closed, guiding line two ends apply suitable voltage, until wire somewhere is thin
Small size position is blown, and disconnects Sp, disconnects Sn；2, Kp is closed, Kn2 is closed, by measuring the electric current between VDD and GND, sentences
Whether it is blown at disconnected T2；3, if be not blown at T2, Kn2 is disconnected, Kn1 is closed, by measuring between VDD and GND
Electric current, judges whether be blown at T；4, Kn1, Kn2 are disconnected, Kn3 is closed, by measuring the electric current between VDD and GND, judged
Whether it is blown at T3, if T3 is not blown, disconnects Kn3, close Kn4, by measuring the electric current between VDD and GND, is judged
Whether it is blown at T4.If be blown at T1, note PUF's is encoded to " 00 ", if be blown at T2, and note PUF's is encoded to
" 01 ", if be blown at T3, note PUF's is encoded to " 10 ", if be blown at T4, and note PUF's is encoded to " 11 ".Due to core
The inevitable natural deviation of piece manufacturing process, causes the size at T1 ~ T4 will not be completely the same, when wire is powered
When, which position can be blown at T1 ~ T4, unpredictable, can not be reappeared, and the PUF of 2 codings are realized with this principle.
Claims (9)
1. a kind of the PUF schemes and circuit realiration of the principle that fused based on chip internal wire, its core are included：
Chip internal is with positive temperature coefficient（Its resistance, which is raised, with temperature becomes big）The M groups of conductive material formation（M is more than or equal to 1）Electricity
Road connecting line, and have on wire at the N in series winding relation（N is more than or equal to 2）Other positions on feature sizes opposing circuit line
Comparatively fine shape design.
2. according to claim 1, it is characterised in that the circuit connection is integrated in chip internal, further, institute
Stating the material of circuit connection has ptc characteristics, i.e. circuit connection resistance becomes big with the rise of its temperature.
3. according to claim 1, it is characterised in that there is being dimensioned for line width at N on every group of circuit connection
Other positions are more tiny on opposing circuit line.
4. further, the relatively fine position of feature sizes is in series relationship on circuit connection at the N.
5. according to claim 3, it is characterised in that every group of circuit connection size and thereon at N fine position line
Wide size selection desired value, to meet：When applying suitable voltage at every group of circuit connection two ends, the electricity produced on circuit connection
Flow and generate heat, at the right time can be with certain in size fine position at the N on Zapping circuit line（Minimum probability
Under a few places）, and circuit connection other positions will not be blown.
6. according to claim 3, it is characterised in that when chip production is manufactured, feature sizes are thin at N on every group of circuit connection
The desired value of the specific size value of small position is consistent, and selects suitable target dimension values, makes to manufacture in chip production
Cheng Zhong, inevitably manufactures the actual size of feature sizes fine position at N on the circuit connection that accuracy error is introduced
Change in suitable scope, to meet：As claimed in claim 5, when applying voltage at every group of circuit connection two ends, circuit connects
The probability that the tiny place of feature sizes is blown because circuit generates heat at N on line causes line width by the deviation of manufacturing process completely
The actual value of size is determined.
7. according to claim 1, it is characterised in that N multiplies the tiny shape of feature sizes at M on the M groups circuit connection
Design location on whole chip is in random distribution, and spacing is sufficiently large, to meet：Each tiny place of feature sizes by
There is no correlation between the influence of manufacturing process.
8. according to claim 1, further characterized in that, a kind of PUF side for the principle that fused based on chip inside conductor
Case and circuit realiration, every group of circuit connection are used to be powered after fusing in circuit connection comprising a set of, judge feature sizes at N thereon
The specific logic circuit being blown at which in fine position.
9. according to claim 7, further characterized in that, the logic circuit of detection fusing position, makes its encoded radio be
Certain complex mapping relation of fusing position, mapping relations include but is not limited to：Hash algorithm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710177271.8A CN106952890A (en) | 2017-03-23 | 2017-03-23 | A kind of the PUF schemes and circuit realiration of the principle that fused based on chip internal wire |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710177271.8A CN106952890A (en) | 2017-03-23 | 2017-03-23 | A kind of the PUF schemes and circuit realiration of the principle that fused based on chip internal wire |
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| CN106952890A true CN106952890A (en) | 2017-07-14 |
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| CN201710177271.8A Pending CN106952890A (en) | 2017-03-23 | 2017-03-23 | A kind of the PUF schemes and circuit realiration of the principle that fused based on chip internal wire |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107918741A (en) * | 2017-11-24 | 2018-04-17 | 北京中电华大电子设计有限责任公司 | A kind of reinforced electric line structure for realizing the unclonable function of physics |
| WO2020102934A1 (en) * | 2018-11-19 | 2020-05-28 | 深圳市汇顶科技股份有限公司 | Signal-generating circuit and related method |
| CN111639370A (en) * | 2020-06-11 | 2020-09-08 | 威海银创微电子技术有限公司 | Nonvolatile SRAM data encryption device |
| CN113728510A (en) * | 2019-04-25 | 2021-11-30 | 三洋电机株式会社 | Voltage detection line and voltage detection line assembly |
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| JPH08213464A (en) * | 1995-02-01 | 1996-08-20 | Toshiba Corp | Semiconductor integrated circuit provided with identifying function |
| US20020063267A1 (en) * | 2000-09-04 | 2002-05-30 | Seiko Epson Corporation | Semiconductor device |
| US20060131575A1 (en) * | 2004-12-17 | 2006-06-22 | Matsushita Electric Industrial Co., Ltd. | Electronic device and manufacturing method thereof |
| US20060291316A1 (en) * | 2005-06-28 | 2006-12-28 | Jenne Fredrick B | Antifuse circuit with dynamic current limiter |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08213464A (en) * | 1995-02-01 | 1996-08-20 | Toshiba Corp | Semiconductor integrated circuit provided with identifying function |
| US20020063267A1 (en) * | 2000-09-04 | 2002-05-30 | Seiko Epson Corporation | Semiconductor device |
| US20060131575A1 (en) * | 2004-12-17 | 2006-06-22 | Matsushita Electric Industrial Co., Ltd. | Electronic device and manufacturing method thereof |
| US20060291316A1 (en) * | 2005-06-28 | 2006-12-28 | Jenne Fredrick B | Antifuse circuit with dynamic current limiter |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107918741A (en) * | 2017-11-24 | 2018-04-17 | 北京中电华大电子设计有限责任公司 | A kind of reinforced electric line structure for realizing the unclonable function of physics |
| WO2020102934A1 (en) * | 2018-11-19 | 2020-05-28 | 深圳市汇顶科技股份有限公司 | Signal-generating circuit and related method |
| CN113728510A (en) * | 2019-04-25 | 2021-11-30 | 三洋电机株式会社 | Voltage detection line and voltage detection line assembly |
| CN113728510B (en) * | 2019-04-25 | 2024-01-05 | 三洋电机株式会社 | Voltage detection line assembly |
| CN111639370A (en) * | 2020-06-11 | 2020-09-08 | 威海银创微电子技术有限公司 | Nonvolatile SRAM data encryption device |
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