CN106952821A - A kind of transistor and forming method thereof - Google Patents
A kind of transistor and forming method thereof Download PDFInfo
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- CN106952821A CN106952821A CN201610008853.9A CN201610008853A CN106952821A CN 106952821 A CN106952821 A CN 106952821A CN 201610008853 A CN201610008853 A CN 201610008853A CN 106952821 A CN106952821 A CN 106952821A
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- ion
- injection region
- conduction type
- substrate
- ion implanting
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- 238000000034 method Methods 0.000 title claims abstract description 59
- 238000002347 injection Methods 0.000 claims abstract description 92
- 239000007924 injection Substances 0.000 claims abstract description 92
- 239000000758 substrate Substances 0.000 claims abstract description 66
- 238000009826 distribution Methods 0.000 claims abstract description 28
- 238000000137 annealing Methods 0.000 claims abstract description 22
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 11
- 150000002500 ions Chemical class 0.000 claims description 134
- -1 Phosphonium ion Chemical class 0.000 claims description 20
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 15
- 229910052796 boron Inorganic materials 0.000 claims description 13
- 238000002513 implantation Methods 0.000 claims description 11
- 229910052757 nitrogen Inorganic materials 0.000 claims description 8
- 239000011261 inert gas Substances 0.000 claims description 3
- 240000007594 Oryza sativa Species 0.000 claims 1
- 235000007164 Oryza sativa Nutrition 0.000 claims 1
- 235000009566 rice Nutrition 0.000 claims 1
- 238000002955 isolation Methods 0.000 abstract description 14
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 241000580063 Ipomopsis rubra Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of transistor and forming method thereof, wherein, the forming method of the transistor includes：Substrate is provided, the substrate has the first conduction type；Injection region is formed by ion implanting mode in the substrate, carry out annealing process, make the injection region uniform from a surface to ion concentration distribution at the following desired depth in surface, the injection region has the second conduction type, second conduction type is opposite with the first conduction type；Ldmos transistor is formed in the injection region.The embodiment of the present invention in the substrate with the first ion implanting and the second ion implanting by way of form injection region, and carrying out annealing process makes the ion distribution in the injection region uniform, the technique of substrate surface formation epitaxial layer is substituted in this, reach and epitaxial layer identical isolation effect and ion distribution level, technological process is greatly simplified, process costs are reduced.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, to a kind of transistor and forming method thereof.
Background technology
, it is necessary in substrate surface formation epitaxial layer with isolation liner bottom in some transistors for being applied to high pressure
Interior active area, while stopping the noise from substrate.Especially, in lateral diffused metal oxide half
The design of conductor (Laterally Diffused Metal-Oxide Semiconductor, LDMOS) transistor
In, the selection of epitaxial wafer (wafer) is the work taken very much, is also unfavorable for the optimization of device.
Also, the special forming process of epitaxial wafer causes its price sufficiently expensive.
For this reason, it may be necessary to which a kind of transistor and forming method thereof, replaces epitaxial layer with new structure and technique
Effect in the transistor, simplifies technological process and can reach identical technological parameter.
The content of the invention
Present invention solves the technical problem that being to provide a kind of transistor and forming method thereof, it is not necessary to form outer
Prolong layer and can reach active area in isolated transistor, to meet the requirement of high tension apparatus.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of transistor and forming method thereof, bag
Include：Substrate is provided, the substrate has the first conduction type；Pass through ion implanting side in the substrate
Formula formation injection region, and annealing process is carried out, make the injection region from a surface to the following desired depth in surface
Locate ion concentration distribution uniform, the injection region has the second conduction type, second conduction type with
First conduction type is opposite；In the injection region formation ldmos transistor.
Alternatively, the injection region is uniform from a surface to ion concentration distribution at the following desired depth in surface,
Including the ion concentration excursion at from the injection region surface to below surface 4 microns to 6 microns not
More than the 30% of injection region surface concentration.
Alternatively, the ion implanting include the first ion implanting and the second ion implanting, described first from
The ionic conduction type of son injection is the second conduction type, the ionic conduction type of second ion implanting
For the first conduction type.
Alternatively, the depth of second ion implanting is the 2/5 to 3/5 of the depth of the first ion implanting.
Alternatively, the ion of first ion implanting is phosphonium ion, the ion of second ion implanting
For boron ion.
Alternatively, the Implantation Energy scope of first ion implanting is 2MeV to 3MeV, dosage model
Enclose is for 1E13atom/cm2To 2E13atom/cm2；The Implantation Energy scope of second ion implanting
It is 300KeV to 600KeV, dosage range is 6E12atom/cm2To 1E13atom/cm2。
Alternatively, the dose-difference of the ion and the ion of the first conduction type of second conduction type is
4E12atoms/cm2。
Alternatively, the ion of first ion implanting is boron ion, the ion of second ion implanting
For phosphonium ion.
Alternatively, the energy range of first ion implanting is 1MeV to 1.5MeV, and dosage range is
1E13atom/cm2To 2E13atom/cm2；The energy range of second ion implanting be 500KeV extremely
1MeV, dosage range is 6E12atom/cm2To 1E13atom/cm2。
Alternatively, the dose-difference of the ion and the ion of the first conduction type of second conduction type is
4E12atoms/cm2。
Alternatively, the annealing process includes：Annealing region is 1100 degrees Celsius to 1200 Celsius
Degree；Annealing time is 20 hours to 30 hours；Annealing atmosphere includes nitrogen or inert gas, the nitrogen
The flow of gas is 20 standard liter/mins to 30 standard liter/mins.
In order to solve the above technical problems, the embodiment of the present invention additionally provides a kind of transistor, including：Substrate,
The substrate has the first conduction type；Injection region in the substrate, the injection region is from surface
Ion concentration distribution is uniform to the following desired depth in surface, and the injection region has the second conduction type,
Second conduction type is opposite with the first conduction type；LDMOS positioned at the injection region is brilliant
Body pipe.
Alternatively, the injection region is uniform from a surface to ion concentration distribution at the following desired depth in surface,
Including the ion concentration excursion at from the injection region surface to below surface 4 microns to 6 microns not
More than the 30% of injection region surface concentration.
Alternatively, PN junction is formed between the injection region and the substrate, the junction depth of the PN junction is 8
Micron is to 10 microns.
Alternatively, from the injection region surface to the second conductive type ion change in concentration scope at PN junction
For 6E15atom/cm3To 5E13atom/cm3；4 below from the injection region surface to injection region surface
The concentration distribution excursion of micron to the second conductive type ion at 6 microns is 6E15atom/cm3Extremely
4E15atom/cm3。
Compared with prior art, the technical scheme of the embodiment of the present invention has the advantages that：
The embodiment of the present invention in the substrate with the first ion implanting and the second ion implanting by way of formed
Injection region, and make the ion distribution in the injection region uniform by annealing process, lining is substituted in this
The technique of basal surface formation epitaxial layer, has reached and epitaxial layer identical isolation effect and ion distribution level.
Also, formation process of the technique compared to prior art epitaxial layers of injection region, pole are formed in substrate
The earth simplifies technological process, reduces process costs.
Brief description of the drawings
Fig. 1 to Fig. 2 is the corresponding section knot of each step of forming method of the transistor of one embodiment of the invention
Structure schematic diagram；
Fig. 3 is the ion concentration distribution curve map of the transistor of one embodiment of the invention.
Embodiment
The present invention provides a kind of transistor and forming method thereof, is described in detail below in conjunction with the accompanying drawings.
Fig. 1 to Fig. 2 is the corresponding section knot of each step of forming method of the transistor of one embodiment of the invention
Structure schematic diagram.
With reference to Fig. 1 there is provided substrate 100, injection region 110 is formed in the substrate 100.
The substrate 100 can be silicon substrate, germanium substrate, silicon carbide substrates or germanium silicon substrate.In this reality
Apply in example, the substrate 100 is monocrystalline substrate.
The substrate 100 is the first conduction type, and the injection region 110 has the second conduction type, institute
The second conduction type and the first conduction type are stated on the contrary, between the injection region 110 and the substrate 100
Form PN junction.
The injection region 110 is formed using the technique of ion implanting, and the technique of the ion implanting includes the
One ion implanting and the second ion implanting.The ionic conduction type of first ion implanting is second conductive
Type, the ionic conduction type of second ion implanting is the first conduction type.The first ion note
The concentration of the ion of the second conduction type entered be more than second ion implanting the first conduction type from
The concentration of son.The depth of second ion implanting is the 2/5 to 3/5 of the depth of the first ion implanting.
It should be noted that after the first ion implanting and the second ion implanting is carried out, the injection region
Ion concentration in 110 is in Gaussian Profile.In the embodiment of the present invention, the depth of first ion implanting with
The depth of second ion implanting refers to the peak in Gaussian Profile.
If the conduction type of the substrate is p-type, the injection region is N-type, first ion implanting
Ion can be phosphonium ion, the ion of second ion implanting can be boron ion.In an implementation
In example, the ion concentration range of the substrate 100 is 1E15atom/cm3To 2E15atom/cm3；Institute
The Implantation Energy scope for stating the phosphonium ion of the first ion implanting is 2MeV to 3MeV, and dosage is 1E13
atom/cm2To 2E13atom/cm2；The Implantation Energy scope of the boron ion of second ion implanting is 300
KeV to 600KeV, dosage range is 5E12atom/cm2To 1E13atom/cm2。
In one embodiment, the ion concentration of the P type substrate 100 is 1.5E15atom/cm3；Institute
The Implantation Energy for stating the phosphonium ion of the first ion implanting is 2.5MeV, and dosage is 1.3E13atom/cm2；
The Implantation Energy of the boron ion of second ion implanting is 500KeV, and dosage is 9E12atom/cm2。
If the conduction type of the substrate is N-type, the injection region is p-type, first ion implanting
Ion can be boron ion, the ion of second ion implanting can be phosphonium ion.In an implementation
In example, the ion concentration range of the N-type substrate 100 is 1E15atom/cm3To 2E15atom/cm3；
The Implantation Energy scope of the boron ion of first ion implanting is 1MeV to 1.5MeV, dosage range
It is 1E13atom/cm2To 2E13atom/cm2；The Implantation Energy of the phosphonium ion of second ion implanting
Scope is 500KeV to 1MeV, and dosage range is 5E12atom/cm2To 1E13atom/cm2。
In one embodiment, the ion concentration of the substrate 100 is 1.5E15atom/cm3；Described
The Implantation Energy of the boron ion of one ion implanting is 1MeV, and dosage is 1.3E13atom/cm2；Described
The Implantation Energy of the phosphonium ion of two ion implantings is 900KeV, and dosage is 9E12atom/cm2。
Formed injection region 110 after, also including carry out annealing process make in the injection region 110 from
Son is evenly distributed.The annealing region of the annealing process is 1100 degrees Celsius to 1200 degrees Celsius,
Annealing time scope is 20 hours to 30 hours, and annealing atmosphere includes nitrogen or inert gas, described lazy
Property gas can be argon gas, the flow of the nitrogen is 20 standard liter/mins to 30 standard liter/mins.
In an embodiment of the invention, the annealing temperature of the annealing process is 1150 degrees Celsius, annealing
Time range is 24 hours, and annealing atmosphere is nitrogen, and the flow of the nitrogen is 25 standard liter/mins.
After the annealing process, the injection region can be realized from a surface to the following desired depth in surface
Locate ion concentration distribution uniform, thus the injection region is suitable as epitaxial layer and uses.Specifically, from institute
The ion concentration excursion below the surface of injection region 110 to surface at 4 microns to 6 microns is stated to be no more than
The 30% of the surface concentration of injection region 110.
In one embodiment, from the injection region surface to below surface 4 microns at the second conductive-type
The concentration distribution excursion of type ion is 6E15atom/cm3To 4.5E15atom/cm3。
In another embodiment, from the injection region surface to below surface 6 microns at it is second conductive
The concentration distribution excursion of types of ion is 5.5E15atom/cm3To 4.2E15atom/cm3。
It should be noted that to make the injection region 110 have with the PN junction of the formation of substrate 100 with serving as a contrast
When forming epitaxial layer on bottom 100, epitaxial layer has identical junction depth, this hair with the PN junction that substrate is formed
Bright embodiment also includes making the dose-difference of first ion implanting and the second ion implanting to be in fixed numbers.
Specifically, in an embodiment of the invention, the dosage of first ion implanting and the second ion implanting
Difference is 4E12atom/cm2。
It should be noted that the order of first ion implanting and the second ion implantation technology can be overturned,
The first ion implanting, the second ion implantation technology can be used successively by forming the injection region；Can also
The second ion implanting, the first ion implantation technology are used successively.
With reference to Fig. 2, ldmos transistor is formed in the region of injection region 110.
The region of injection region 110 includes the region in injection region 110 and the area more than surface of injection region 110
Domain.Forming the method for the ldmos transistor includes：Region in the injection region 110 forms drift
Move area 120 and body area 130；The first isolation structure 121 is formed in the drift region 120, in the body area
The second isolation structure 131 is formed in 130；Region more than the surface of injection region 110 forms grid structure
140；Source region 133 and drain region 122 are formed in the body area 130 and drift region 120 respectively.
Before source region 133 is formed, it is additionally included in the body area 130 and forms lightly doped district 132；In shape
Into after source region 133 and drain region 122, second isolation structure 131 is additionally included in away from the source region
Body contact zone 134 is formed in the injection region 110 of 133 sides, the body contact zone 134 is formed at the body
In area 130；Pass through the phase of the second isolation structure 131 between the lightly doped district 132 and body contact zone 134
Isolation.
Transistor described in the embodiment of the present invention can be that N-type ldmos transistor or p-type LDMOS are brilliant
Body pipe, but ldmos transistor is not limited to, it can also be other high voltage transistors.
Correspondingly, the embodiment of the present invention also provides a kind of structure for the transistor that use above method is formed.
With continued reference to Fig. 2, the transistor includes：Substrate 100, the substrate 100 has the first conduction
Type；Injection region 110, in the substrate 100, the injection region 110 from a surface to surface with
Ion concentration distribution is uniform at lower desired depth, and the injection region 110 has the second conduction type, described
Second conduction type is opposite with the first conduction type；Ldmos transistor, positioned at the injection region 110
It is interior.
Wherein, from the surface of injection region 110 to below surface 4 microns to 6 microns at ion concentration
Excursion is no more than the 30% of the surface concentration of injection region 110；The injection region 110 and the substrate 100
Between form PN junction, the junction depth scope for forming the PN junction is 8 microns to 10 microns.
In one embodiment, the substrate 100 is monocrystalline substrate, from the surface of injection region 110
The concentration distribution excursion of the second conductive type ion below to surface at 4 microns is 6E15
atom/cm3To 4.5E15atom/cm3；PN is formed between the injection region 110 and the substrate 100
The junction depth of knot is 8.8 microns, from the surface of injection region 110 to the second conductive type ion at PN junction
Change in concentration scope is 6E15atom/cm3To 5E13atom/cm3。
In another embodiment, the substrate 100 is monocrystalline substrate, from the table of injection region 110
The concentration distribution excursion of the second conductive type ion below face to surface at 6 microns is 5.5E15
atom/cm3To 4.2E15atom/cm3；PN is formed between the injection region 110 and the substrate 100
The junction depth of knot is 9.2 microns, from the surface of injection region 110 to the second conductive type ion at PN junction
Change in concentration scope is 5.5E15atom/cm3To 8E13atom/cm3。
The ldmos transistor includes：Drift region 120 and body area 130, positioned at the injection region 110
It is interior；Grid structure 140, body area 130 described in covering part and the part drift region 120；Source region 133,
In the injection region 110 of the side of grid structure 140, and the source region 133 is located at the body area
In 130；Drain region 122, in the injection region 110 of the opposite side of grid structure 140, and the leakage
Area 122 is located in the drift region 120.
In certain embodiments, the ldmos transistor also includes being located in the drift region 120
First isolation structure 121, the second isolation structure 131 in the body area 130.The source region 133
Between the grid structure 140 and second isolation structure 131, the drain region 122 is located at institute
State side of first isolation structure 121 away from the grid structure 140.
In certain embodiments, the ldmos transistor also includes lightly doped district 132, described to be lightly doped
Area 132 is located between second isolation structure 131 and the source region 133.
In certain embodiments, the ldmos transistor also includes body contact zone 134, the body contact
Area 134 is located in injection region 110 of second isolation structure 131 away from the side of source region 133,
And the body contact zone 134 is located in the body area 130.
It is the ion concentration distribution curve map of the transistor of one embodiment of the invention with reference to Fig. 3.Abscissa is
The concentration of Doped ions is taken the logarithm, and (unit of concentration is atom/cm3), ordinate is apart from crystal tube lining
The depth (unit for μm) of basal surface.Matched curve 200 is that the embodiment of the present invention passes through the shape in substrate
The ion concentration distribution curve map of the transistor formed into injection region；Matched curve 210 is existing skill
Pass through the ion concentration distribution curve map of the transistor that formation epitaxial layer is formed on substrate in art.Pass through
Compare matched curve 200 and matched curve 210 is understood, the ion concentration of the transistor of the embodiment of the present invention
Approximate coincidence can be reached with the ion concentration distribution of the transistor of prior art formation by being distributed, and illustrate this hair
Bright embodiment forms injection region in substrate in the way of ion implanting, can be substituted in substrate surface and be formed
The technique of epitaxial layer, greatly simplifies technological process, reduces process costs.
In addition, the surface of the transistor of the embodiment of the present invention (is specially 0.2 micrometer range below substrate surface
It is interior) the concentration differences of Doped ions be approximately 1E16atom/cm3, formed in the prior art compared to using
Transistor surface doping ion concentration difference be more than 1E17atom/cm3For, to subsequent device characteristic institute
The influence brought is smaller.
It should be noted that matched curve 200 is close at substrate surface, ion concentration skyrockets, and draws
The reason for playing this phenomenon is the diffusion rate that the diffusion rate of boron in the substrate is more than phosphorus, and due to boron
Easily pierce the oxide layer two that the oxide layer silica of substrate surface, phosphorus are then easily attracted to substrate surface
Silicon oxide surface, causes the concentration of substrate surface phosphorus to be higher than boron.This phenomenon can be by the later stage in substrate
The trap ion implanting that surface carries out shallow depth carrys out adjusting threshold voltage, so that the ion concentration of substrate surface
Recover normal level.
In summary, the transistor formed using the forming method of the present embodiment, wherein injection region and lining
The junction depth for the PN junction that bottom is formed, can reach the PN junction phase formed during with forming epitaxial layer on substrate
Same junction depth；And the ion distribution level described in the present embodiment in PN junction after annealed technique with
Ion distribution level in the PN junction formed by extension layer process has good uniformity.In addition, this
Mix on the surface (below surface in 0.2 micrometer range) for the transistor that the forming method of inventive embodiments is formed
The concentration difference of heteroion is approximately 1E16atom/cm3, the influence brought to subsequent device characteristic is smaller.
Therefore, the injection region of the embodiment of the present invention can be taken as epitaxial layer and use, and form LDMOS wherein
Deng high voltage transistor.Formation of the technique compared to prior art epitaxial layers of injection region is formed in substrate
Technique, greatly simplifies technological process, reduces process costs.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, it can make various changes or modifications, therefore the guarantor of the present invention
Shield scope should be defined by claim limited range.
Claims (15)
1. a kind of forming method of transistor, it is characterised in that including：
Substrate is provided, the substrate has the first conduction type；
Injection region is formed by ion implanting mode in the substrate, and carries out annealing process, is made described
Injection region is uniform from a surface to ion concentration distribution at the following desired depth in surface, and the injection region has the
Two conduction types, second conduction type is opposite with the first conduction type；
In the injection region formation ldmos transistor.
2. forming method as claimed in claim 1, it is characterised in that the injection region from a surface to surface with
Ion concentration distribution is uniform at lower desired depth, including from the injection region surface to below surface 4 micro-
Rice to the ion concentration excursion at 6 microns is no more than the 30% of injection region surface concentration.
3. forming method as claimed in claim 1 or 2, it is characterised in that the ion implanting includes first
Ion implanting and the second ion implanting, the ionic conduction type of first ion implanting are conductive for second
Type, the ionic conduction type of second ion implanting is the first conduction type.
4. forming method as claimed in claim 3, it is characterised in that the depth of second ion implanting is
The 2/5 to 3/5 of the depth of first ion implanting.
5. forming method as claimed in claim 3, it is characterised in that the ion of first ion implanting is
Phosphonium ion, the ion of second ion implanting is boron ion.
6. forming method as claimed in claim 5, it is characterised in that the injection energy of first ion implanting
It is 2MeV to 3MeV to measure scope, and dosage range is for 1E13atom/cm2To 2E13atom/cm2；
The Implantation Energy scope of second ion implanting is 300KeV to 600KeV, and dosage range is 6
E12atom/cm2To 1E13atom/cm2。
7. forming method as claimed in claim 6, it is characterised in that the ion of second conduction type with
The dose-difference of the ion of first conduction type is 4E12atoms/cm2。
8. forming method as claimed in claim 3, it is characterised in that the ion of first ion implanting is
Boron ion, the ion of second ion implanting is phosphonium ion.
9. forming method as claimed in claim 8, it is characterised in that the energy model of first ion implanting
It is 1MeV to 1.5MeV to enclose, and dosage range is 1E13atom/cm2To 2E13atom/cm2；Institute
The energy range for stating the second ion implanting is 500KeV to 1MeV, and dosage range is 6E12
atom/cm2To 1E13atom/cm2。
10. forming method as claimed in claim 9, it is characterised in that the ion of second conduction type with
The dose-difference of the ion of first conduction type is 4E12atoms/cm2。
11. forming method as claimed in claim 1, it is characterised in that the annealing process includes：Annealing temperature
It is 1100 degrees Celsius to 1200 degrees Celsius to spend scope；Annealing time is 20 hours to 30 hours；Move back
Internal heat atmosphere includes nitrogen or inert gas, and the flow of the nitrogen is 20 standard liter/mins to 30 standards
Liter/min.
12. a kind of transistor, it is characterised in that including：
Substrate, the substrate has the first conduction type；
Injection region in the substrate, the injection region from a surface at the following desired depth in surface from
Sub- uniform concentration distribution, the injection region has the second conduction type, second conduction type and first
Conduction type is opposite；
Positioned at the ldmos transistor of the injection region.
13. transistor as claimed in claim 12, it is characterised in that the injection region from a surface to surface below
Ion concentration distribution is uniform at desired depth, including from the injection region surface to 4 microns below surface
Ion concentration excursion to 6 microns is no more than the 30% of injection region surface concentration.
14. the transistor as described in claim 12 or 13, it is characterised in that the injection region and the substrate
Between form PN junction, the junction depth of the PN junction is 8 microns to 10 microns.
15. transistor as claimed in claim 14, it is characterised in that at from the injection region surface to PN junction
The second conductive type ion change in concentration scope be 6E15atom/cm3To 5E13atom/cm3；From
The concentration of the second conductive type ion at the injection region surface to below surface 4 microns to 6 microns
Changes in distribution scope is 6E15atom/cm3To 4E15atom/cm3。
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| CN1641886A (en) * | 2004-01-16 | 2005-07-20 | 崇贸科技股份有限公司 | Isolated high-voltage LDMOS transistor having a split well structure |
| CN101312211A (en) * | 2007-05-25 | 2008-11-26 | 东部高科股份有限公司 | Semiconductor device and its manufacture method |
| CN102130168A (en) * | 2010-01-20 | 2011-07-20 | 上海华虹Nec电子有限公司 | Isolated LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof |
| CN102376762A (en) * | 2010-08-26 | 2012-03-14 | 上海华虹Nec电子有限公司 | Super junction LDMOS(Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof |
| TW201413795A (en) * | 2012-08-22 | 2014-04-01 | Advanced Ion Beam Tech Inc | Doping a non-planar semiconductor device |
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2016
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1641886A (en) * | 2004-01-16 | 2005-07-20 | 崇贸科技股份有限公司 | Isolated high-voltage LDMOS transistor having a split well structure |
| CN101312211A (en) * | 2007-05-25 | 2008-11-26 | 东部高科股份有限公司 | Semiconductor device and its manufacture method |
| CN102130168A (en) * | 2010-01-20 | 2011-07-20 | 上海华虹Nec电子有限公司 | Isolated LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof |
| CN102376762A (en) * | 2010-08-26 | 2012-03-14 | 上海华虹Nec电子有限公司 | Super junction LDMOS(Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof |
| TW201413795A (en) * | 2012-08-22 | 2014-04-01 | Advanced Ion Beam Tech Inc | Doping a non-planar semiconductor device |
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