CN106936451B - Has the transmitter of pulling effect compensation mechanism - Google Patents
Has the transmitter of pulling effect compensation mechanism Download PDFInfo
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- CN106936451B CN106936451B CN201511032176.6A CN201511032176A CN106936451B CN 106936451 B CN106936451 B CN 106936451B CN 201511032176 A CN201511032176 A CN 201511032176A CN 106936451 B CN106936451 B CN 106936451B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
- H04B1/0475—Circuits with means for limiting noise, interference or distortion
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- H—ELECTRICITY
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- H04B17/00—Monitoring; Testing
- H04B17/10—Monitoring; Testing of transmitters
- H04B17/11—Monitoring; Testing of transmitters for calibration
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Abstract
The invention discloses a kind of transmitters for having pulling effect compensation mechanism, include correction unit and output unit.Correcting unit includes storage circuit and address production electric circuit.Storage circuit stores look-up table, and wherein look-up table record corresponds to in-phase data signal, the correction data of orthogonal data signals and an at least system parameter.Address production electric circuit generates address according to in-phase data signal, orthogonal data signals and an at least system parameter, to pass through correction data output calibration signal.Output unit is mixed to generate modulating signal correction signal according to oscillator signal, and amplifies modulating signal, to generate output signal.
Description
Technical field
The present invention relates to a kind of transmitters, and in particular to there is the transmitter for the mechanism for eliminating pulling effect to eliminate with it
Method.
Background technique
In various wireless communication systems, transmitter can carry out frequency modulating by oscillator signal caused by oscillator,
To generate the radiofrequency signal for being suitble to wireless communication.However, the size with transmitter is smaller and smaller, this radiofrequency signal may coupling
Oscillator is closed back, causes the oscillator signal of oscillator to generate phase error, reduces the overall efficiency of transmitter.Above-mentioned phenomenon is general
Referred to as pull-in phenomena (pulling effect).
In some technologies, eliminate pull-in phenomena correction mechanism be set to frequency mixer after.In this way, required for correction mechanism
Bandwidth it is higher, cause transmitter cost and design complexities increase.In other technologies, the correction of pull-in phenomena is eliminated
Circuit is set in phase-locked loop.In this way, unnecessary phase noise may be introduced, the overall efficiency of transmitter is reduced.
Summary of the invention
An aspect of the invention is in providing a kind of transmitter.Transmitter includes correction unit and output unit.Correction is single
Member includes storage circuit and the first address production electric circuit.Storage circuit stores look-up table, and wherein look-up table record corresponds to same phase
The correction data of data-signal, orthogonal data signals and an at least system parameter.First address production electric circuit is according to in-phase data
Signal, orthogonal data signals and an at least system parameter generate the first address, to pass through correction data output calibration signal.Output
Unit is mixed to generate modulating signal correction signal according to oscillator signal, and amplifies modulating signal, to generate output letter
Number.
In conclusion different set-up modes, which are utilized, in transmitter provided by the present invention presets multiple groups look-up table, with
The error generated according to the received fundamental frequency signal elimination of the system operating condition of transmitter and institute by pulling effect.In this way,
The system effectiveness of transmitter and the precision of transmission signal are improved.
Detailed description of the invention
For above and other purpose, feature, advantage and the embodiment of present disclosure can be clearer and more comprehensible, specification is attached
Figure is described as follows:
Figure 1A is the schematic diagram of an embodiment of transmitter according to the present invention；
Mathematical equivalent model schematic when pull-in phenomena occurs for the transmitter that Figure 1B is Figure 1A；
Fig. 1 C is a kind of mathematical equivalent for the correction matrix for inhibiting pull-in phenomena according to depicted in one embodiment of the invention
Model schematic；
Fig. 2 is a kind of schematic diagram of transmitter according to depicted in one embodiment of the invention；
Fig. 3 A is the schematic diagram for correcting an embodiment of unit；
Fig. 3 B is the schematic diagram for correcting another embodiment of unit；
Fig. 4 is the schematic diagram for correcting another embodiment of unit；
Fig. 5 A is the schematic diagram for correcting another embodiment of unit；
Fig. 5 B is the schematic diagram for correcting an embodiment of counting circuit；
Fig. 6 A is the schematic diagram of an embodiment of address production electric circuit；And
Fig. 6 B is the schematic diagram of another embodiment of address production electric circuit.
Description of symbols:
100,200: transmitter 220,300,300A, 400,500: correction
110: digital analog converter unit
120: low-pass filter 240: output unit
130: voltage controlled oscillator 222: storage circuit
140: local oscillated signal generator 224,600,600A: address production electric circuit
150: frequency mixer AD: address
160: power amplifier I (t), I [n]: in-phase data signal
170: antenna Q (t), Q [n]: orthogonal data signals
SDBB: fundamental frequency signal C1, C1 [n], C2, C2 [n]: coefficient
SABB: analog signal g: system parameter
SVCO: oscillator signal 222A, 222B: look-up table
SLO: local oscillated signal I ' (t)+jQ ' (t), I ' [n]+jQ ' [n]: correction signal
SVM: modulating signal Q [n-1]~Q [n-L]: previous orthogonal data signals
SVO: output signal I0[n]+jQ0[n]~IL[n]+jQL[n]: thermal compensation signal
100A: correction matrix 320: delay circuit
θ (t): phase error 410,512A~512E, 620,630~632:
I [n-1]~I [n-L]: previous in-phase data signal multiplier
α [n]~α [n-L], β [n]~β [n-L]: phase I2[n]、Q2[n]、I[n]Q[n]、I2[n]-Q2[n]:
Position correction signal operation values
α [n]+j β [n]~α [n-L]+j β [n-L]: pre- C1 [n] * (I2[n]-Q2[n])
First thermal compensation signal C2 [n] * (I2[n]-Q2[n]): operation values
340,514,640: adder PAD, PAD1~PAD3: compiling preparatory address
510: correction counting circuit code
513: subtracter
515: coordinate converter
θ [n]: phase error
610: data combiner
Specific embodiment
" signal A (t) " used herein refers to the continuous signal of analog form." signal A [n] " refer to digital form from
Scattered signal, and it is corresponding to signal A (t).In some embodiments, signal A [n] can be converted by digital analog converter to correspondence
Signal A (t), in other embodiments, signal A (t) can be converted by analog-digital converter to corresponding signal A [n].
Figure 1A is the schematic diagram of an embodiment of transmitter according to the present invention.
Digital analog converter 110 receives fundamental frequency signal SDBB, and according to fundamental frequency signal SDBBGenerate corresponding analog signal
SABB.Low-pass filter 120 removes analog signal SABBOn because of the mirror image caused by digital-to-analogue conversion.Voltage controlled oscillator 130 produces
It is raw that there is frequency fVCOOscillator signal SVCOTo local oscillated signal generator 140.Local oscillated signal generator 140 can be accordingly
To oscillator signal SVCOFrequency elimination is carried out, there is local frequency f to generateLOLocal oscillated signal SLOTo frequency mixer 150.Frequency mixer
150 can be according to local oscillated signal SLOTo through filtered analog signal SABBRaising frequency is carried out, to export modulating signal SVM.Power
Amplifier 160 amplifies modulating signal SVMPower and generate output signal SVO.Antenna 170 externally emits output signal SVO.Its
In, above-mentioned output signal SVOIt is represented by following formula (1) in the time domain:
SVO=GABB(t)cos(ωLOt+θBB(t)+σ)…(1)。
In formula (1), G is the entire gain of transmitter 100, ABBIt (t) is analog signal SABBAmplitude, ωLOFor correspondence
Local frequency fLOAngular frequency, θBBIt (t) is analog signal SABBPhase, and σ be fundamental frequency signal SDBBPassing through transmitter 100
When introduced extra phase.
If voltage controlled oscillator 130 generates traction (pulling) phenomenon, output signal S above-mentionedVOFollowing formula can be modified to
(2):
SVO=GABB(t)cos(ωLOt+θBB(t)+σ+θ(t))…(2)。
Wherein, θ (t) is the introduced phase error of pull-in phenomena.If assuming, extra phase σ is 0 in formula (2), and is emitted
Gain G=1 of device 100, can be by output signal SVOIt is further simplified as following formula (3):
SVO=ABB(t)cos(ωLOt+θBB(t)+θ(t))…(3)。
Expansion (3) is available:
SVO=[ABB(t)cos(θBB(t))cos(θ(t))cos(ωLOt)]
+[ABB(t)sin(θBB(t))cos(θ(t))(-sin(ωLOt)]
+[ABB(t)cos(θBB(t))sin(θ(t))(-sin(ωLOt)]
-[ABB(t)sin(θBB(t))sin(θ(t))(cos(ωLOt)]
=[I (t) cos (θ (t)) cos (ωLOt)+Q(t)cos(θ(t))(-sin(ωLOt))]
+[I(t)sin(θ(t))(-sin(ωLOt)-Q(t)sin(θ(t))(cos(ωLOt))]…(4)。
Wherein, I (t)=ABB(t)cos(θBB(t)), and I (t) is corresponding to fundamental frequency signal SDBBSame phase (in-phase)
Data-signal.Q (t)=ABB(t)sin(θBB(t)), and Q (t) is corresponding to fundamental frequency signal SDBBOrthogonal (quadrature) number
It is believed that number.
Figure 1B be when the transmitter as shown in Figure 1A according to depicted in one embodiment of the invention generates pull-in phenomena when
Mathematical equivalent model schematic under domain.
Fig. 1 C is a kind of mathematical equivalent for the correction matrix for inhibiting pull-in phenomena according to depicted in one embodiment of the invention
Model schematic.By mathematical equivalent model shown in Figure 1B, the present invention proposes a kind of bearing calibration for inhibiting pull-in phenomena, says
It is bright as follows.
In some embodiments, in fundamental frequency signal SABBBefore being first mixed, using correction matrix 100A shown in Fig. 1 C to base
Frequency signal SABBIt is corrected, to eliminate the introduced phase error theta (t) of pull-in phenomena.It is shown respectively according to Figure 1B and Fig. 1 C
Mathematical equivalent model, it can be seen that in-phase data signal I (t) and orthogonal data signals Q (t) meet following formula (5):
Therefore, according to formula (5), by correction matrix 100A to fundamental frequency signal SABBOperation is carried out in advance, and it is existing can to eliminate traction
As introduced phase error theta (t).A mode is changed to explain, if formula (5) is expressed as following formula (6) in the form of complex function:
I'(t)+jQ'(t)=[I (t)+Q (t)] e[-jθ(t)]=[I (t)+Q (t)] [α (t)+j β (t)] ... (6).
Wherein, I ' (t)+jQ ' (t) is the correction signal after corrected matrix 100A operation, and phase correction signal α
It (t) is cos (θ (t)) that phase correction signal β (t) is-sin (θ (t)).For equivalent, fundamental frequency is believed by correction matrix 100A
Number SABBOperation is carried out in advance, can produce preparatory phase correction signal φ (t), and φ (t)=- θ (t).In this way, correcting
When signal I ' (t)+jQ ' (t) is mixed by frequency mixer 150, preparatory phase correction signal φ (t) can be with phase error theta
(t) it offsets each other, and then is influenced caused by elimination pull-in phenomena.
Fig. 2 is a kind of schematic diagram of transmitter according to depicted in one embodiment of the invention.As shown in Fig. 2, transmitter
200 contain correction unit 220 and output unit 240, wherein output unit 240 include aforementioned digital analog converter 110, it is low
Bandpass filter 120, voltage controlled oscillator 130, local oscillated signal generator 140, frequency mixer 150, power amplifier 160 and antenna
170, therefore its correlation function is not repeated to describe.
Correcting unit 220 includes storage circuit 222 and address production electric circuit 224.Storage circuit 222 can for buffer or with
Machine temporary storage memory etc..Storage circuit 222 stores an at least look-up table, this look-up table record corresponds to in-phase data
The correction data of signal I [n], orthogonal data signals Q [n] and an at least system parameter g.
Referring to the relevant technologies file (Pulling Mitigation in Wireless Transmitter IEEE JSSC
Vol.49, NO.9, Sep.2014.) related content and Fig. 3, phase error theta (t) and fundamental frequency signal SDBBIt is related, wherein fundamental frequency
Signal SDBBCorresponding analog signal SABBIt can be formed by in-phase data signal I (t) and orthogonal data signals Q (t) superposition, i.e. ABB
=I (t)+jQ (t).According to Fig. 3 of above-mentioned technological document and formula (6), it can be seen that phase correction signal φ (t) is in coordinate in advance
Following formula (7) are represented by after conversion:
φ [n]=C1(I2[n]-Q2[n])+C2(2I[n]Q[n])…(7)。
In above formula (7), coefficient C1 and coefficient C2 and system parameter g (such as: the output power of power amplifier 160 with
The operation temperature etc. of transmitter 200) it is related.It therefore, can be according to above-mentioned formula (6)~formula (7), different system parameter g, same to phase
Data-signal I [n] and orthogonal data signals Q [n] calculated in advance measure desired correction signal I ' [n]+jQ ' [n], and record
For correction data above-mentioned, content will be described in detail in rear paragraph herein.
Address production electric circuit 224 generates phase according to in-phase data signal I [n], orthogonal data signals Q [n] and system parameter g
The address AD answered, with the query correction data from look-up table, and output calibration signal I ' [n]+jQ ' [n] is to output unit 240.
In this way, output unit 240 can be filtered to correction signal I ' [n]+jQ ' [n], be mixed the operation of also amplifying power, with
Generate output signal SVO。
Following paragraphs will propose each embodiment, to illustrate the function and application of above-mentioned correction unit 220.It should be noted
It is, for clear explanation, to describe aforementioned fundamental frequency signal S in the attached drawing of aftermentioned each embodiment in the form of complex functionDBB(i.e. I
[n]+jQ [n]) with being associated between each circuit.Those skilled in the art can adjust the reality of correction unit 220 according to each attached drawing
Apply mode, therefore the present invention and embodiment not only set forth below is limited.
Fig. 3 A is the schematic diagram for correcting an embodiment of unit.As shown in Figure 3A, in this example, storage circuit 222 is stored
Look-up table 222A and look-up table 222B.Correction data in look-up table 222A stores multiple precalculated in-phase datas
Value I0[n], and the correction data in look-up table 222B stores multiple precalculated orthogonal data value Q0[n].Address generates
Circuit 224 can be according to in-phase data signal I [n], orthogonal data signals Q [n] and system parameter the g generation pair received at present
The address answered, to select corresponding in-phase data values I respectively from look-up table 222A and look-up table 222B0[n] and orthogonal function
According to value Q0[n], to generate corresponding thermal compensation signal I0[n]+jQ0[n], and export as correction signal I ' [n]+jQ ' [n] to rear
The output unit 240 of side.
For equivalent, in this example, calculated in advance by formula (6), the correction data in storage circuit 222 stores
The precalculated thermal compensation signal I of multiple groups0[n]+jQ0[n].Address production electric circuit 224 in-phase data can be believed based on the received
Number I [n], orthogonal data signals Q [n] and system parameter g and select corresponding one group of thermal compensation signal I from look-up table0[n]+jQ0
[n], with output for correction signal I ' [n]+jQ ' [n].
Fig. 3 B be correct unit another embodiment schematic diagram, correction unit 300A contain multiple delay circuits 320,
Multiple address production electric circuits 224, multiple look-up table 222A and 222B and adder 340.
As shown in Figure 3B, multiple 320 coupled in series of delay circuit, with according to in-phase data signal I [n], orthogonal function it is believed that
Number Q [n] sequentially exports multiple previous in-phase data signal I [n-1]~I [n-L] and multiple previous orthogonal data signals Q [n-1]
~Q [n-L].Multiple address production electric circuits 224 receive multiple previous fundamental frequency signal I [n-1]+jQ [n-1]~I [n-L]+jQ respectively
[n-L].In this way, each address production electric circuit 224 fundamental frequency signal I [n]+jQ [n] or previous fundamental frequency can be believed based on the received
Number I [n-1]+jQ [n-1]~I [n-L]+jQ [n-L] and system parameter g generates corresponding address AD, is looked into self-corresponding
Table 222A is looked for select corresponding multiple groups thermal compensation signal I with 222B0[n]+jQ0[n]~IL[n]+jQL[n].Adder 340 is by multiple groups
Thermal compensation signal I0[n]+jQ0[n]~IL[n]+jQL[n] is added, to generate correction signal I ' [n]+jQ ' [n].
Compared to Fig. 3 A, the shadow that memory effect under broadband system (memory effect) is more contemplated in unit 300A is corrected
It rings.Correspond to the preceding received fundamental frequency signal S of L moment institute by settingDBBMultiple groups look-up table 222A and 222B, correct unit
300A can eliminate voltage controlled oscillator 130 in caused total phase error of preceding L moment internal cause pulling effect.Such one
Come, the efficiency of transmitter 200 can further be improved.
Fig. 4 is the schematic diagram for correcting the another embodiment of unit.Compared to Fig. 3 B, correction unit 400 further comprises multiple
Multiplier 410.In this example, the correction data in multiple look-up table 222A stores multiple precalculated multiple phases respectively
Position correction signal α [n]~α [n-L], and the correction data in multiple look-up table 222B store respectively it is multiple precalculated
Multiple phase correction signal β [n]~β [n-L].Accordingly, multiple address production electric circuits 224 are respectively according to received fundamental frequency signal I
[n]+jQ [n], previous fundamental frequency signal I [n-1]+jQ [n-1]~I [n-L]+jQ [n-L] and system parameter g are corresponding to generate
Address AD selects corresponding phase correction signal α [n]~α [n-L] and corresponding phase with self-corresponding look-up table 222A and 222B
Position correction signal β [n]~β [n-L], to generate multiple pre-compensation signal alpha [n]+j β [n]~α [n-L]+j β [n-L].It is multiple
410 multiplication fundamental frequency signal I [n]+jQ [n] of multiplier and pre-compensation signal alpha [n]+j β [n], and multiple previous bases that are multiplied respectively
Frequency signal I [n-1]+jQ [n-1]~I [n-L]+jQ [n-L] and multiple pre-compensation signal alpha [n-1]+j β [n-1]~α [n-L]+
J β [n-L], to generate multiple thermal compensation signal I0[n]+jQ0[n]~IL[n]+jQL[n-L].Adder 340 is by multiple groups thermal compensation signal
I0[n]+jQ0[n]~IL[n]+jQL[n] is added, to generate correction signal I ' [n]+jQ ' [n].
In further embodiments, correction unit 400 can also use set-up mode as shown in Figure 3A, single being used only
Multiplier 410, single address production electric circuit 224, under single look-up table 222A and look-up table 222B, according to fundamental frequency signal
I [n]+jQ [n] generates thermal compensation signal I0[n]+jQ0[n], and it is single to exporting as correction signal I ' [n]+jQ ' [n] output
Member 240.The explanation of relevant operation is similar with previous paragraph, therefore it is no longer repeated.
Fig. 5 A is the schematic diagram for correcting the another embodiment of unit, and compared to Fig. 4, correcting unit 500 also includes multiple schools
Positive counting circuit 510.Multiple precalculated multiple coefficient C1 are stored in multiple look-up table 222A in correction unit 500
[n]~C1 [n-L], and multiple precalculated multiple coefficient C2 [n]~C2 [n-L] are stored in multiple look-up table 222B.
Multiple address production electric circuits 224 can be respectively according to system parameter g, received fundamental frequency signal I [n]+jQ [n] or previous fundamental frequency signal
I [n-1]+jQ [n-1]~I [n-L]+jQ [n-L] generates corresponding address AD, with self-corresponding look-up table 222A with it is corresponding
Look-up table 222B selects corresponding coefficient C1 [n] and coefficient C2 [n] respectively.Counting circuit 510 is corrected according to corresponding coefficient
C1 [n] and coefficient C2 [n], in-phase data signal I [n] and orthogonal data signals Q [n] generate phase correction signal α [n] and phase
Correction signal β [n].In this way, multiple correction counting circuits 510 can produce multiple groups pre-compensation signal alpha [n]+j β [n]~α [n-L]
+jβ[n-L].Multiple 410 multiplication fundamental frequency signal I [n]+jQ [n] of multiplier and pre-compensation signal alpha [n]+j β [n], and phase respectively
Multiply multiple previous fundamental frequency signal I [n-1]+jQ [n-1]~I [n-L]+jQ [n-L] and multiple pre-compensation signal alpha [n-1]+j β
[n-1]~α [n-L]+j β [n-L], to generate multiple groups thermal compensation signal I0[n]+jQ0[n]~IL[n]+jQL[n].Adder 340 will
Multiple groups thermal compensation signal I0[n]+jQ0[n]~IL[n]+jQL[n] is added, to generate correction signal I ' [n]+jQ ' [n].
In further embodiments, correction unit 500 can also use set-up mode as shown in Figure 3A, single being used only
Correction counting circuit 510, single multiplier 410, single address production electric circuit 224, single look-up table 222A with look into
It looks under table 222B, thermal compensation signal I is generated according to fundamental frequency signal I [n]+jQ [n]0[n]+jQ0[n], and as correction signal I '
[n]+jQ ' [n] is exported to output unit 240.Relevant operation is similar with the explanation of previous paragraph, therefore it is no longer repeated.
Fig. 5 B corrects the schematic diagram of an embodiment of counting circuit.As shown in Figure 5 B, correction counting circuit 510 includes multiple
Multiplier 512A~512E, subtracter 513, adder 514 and coordinate converter 515.
512A squares of multiplication in-phase data signal I [n] of multiplier, to generate operation values I2[n].512B squares of phase of multiplier
Multiply orthogonal data signals Q [n], to generate operation values Q2[n].Multiplier 512C multiplication in-phase data signal I [n] and orthogonal data
Signal Q [n], to generate operation values I [n] Q [n].513 additive operation value I of subtracter2[n] and operation values Q2[n], to generate operation
Value I2[n]-Q2[n].Multiplier 512D multiplied value I2[n]-Q2[n] and coefficient C1 [n], and generate operation values C1 [n] * (I2[n]-
Q2[n]).Multiplier 512E multiplied value I [n] Q [n] and coefficient C2 [n], and generate operation values C2 [n] * (I [n] Q [n]).Addition
514 sum operation value C1 [n] * (I of device2[n]-Q2[n]) and operation values C0 [n] * (I [n] Q [n]), to generate phase error θ
[n].Coordinate converter carries out coordinate conversion according to phase error θ [n], to generate phase correction signal α [n] and phase respectively
Correction signal β [n], wherein phase correction signal α [n]=cos (θ [n]), and phase correction signal β [n]=- sin (θ [n]).
For equivalent, in this example, correction counting circuit 510 can be calculated sequentially most according to formula above-mentioned (7) and formula (6)
Composition parameter required for correction signal I ' (t)+jQ ' (t) exported eventually.
Fig. 6 A is the schematic diagram of an embodiment of address production electric circuit.As shown in Figure 6A, address production electric circuit 600 includes number
According to combiner 610 and multiplier 620.Data combiner 610 merges in-phase data signal I [n] and orthogonal data signals Q [n], with
Export preparatory address code PAD.Multiplier 620 is multiplied preparatory address code PAD and system parameter g, with output address AD.
For example, in-phase data signal I [n] and orthogonal data signals Q [n] are all the numerical data with 5 bits,
And system parameter g=2 (for example, the gain of transmitter 200 is 2 times).The bit value of in-phase data signal I [n] is " 01001 ",
And the bit value of orthogonal data signals Q [n] is " 10101 ".Data combiner 610 can be by in-phase data signal I [n] and orthogonal function
It is believed that number Q [n] is attached, to generate the preparatory address code PAD of 10 bits, wherein the bit value of preparatory address code PAD
For " 0100110101 ".Multiplier 620 can export the address AD with 10 bits accordingly, and wherein the bit value of address AD is "
1001101010”。
Fig. 6 B is the schematic diagram of an embodiment of address production electric circuit.As shown in Figure 6B, address production electric circuit 600A includes
Multiple multipliers 630~632 and adder 640.630 squares of multiplication in-phase data signal I [n] of multiplier, to generate in advance
Location encodes PAD1.631 squares of multiplication orthogonal data signals Q [n] of multiplier, to generate preparatory address code PAD2.Adder 640
It is added preparatory address code PAD1 and preparatory address code PAD2, to generate preparatory address code PAD3.Multiplier 640 is multiplied pre-
First address code PAD3 and system parameter g, with output address AD.
For example, in-phase data signal I [n] and orthogonal data signals Q [n] are all the numerical data with 5 bits,
And system parameter g=2 (for example, the gain of transmitter 200 is 2 times).The bit value of in-phase data signal I [n] is " 01001 ",
And the bit value of orthogonal data signals Q [n] is " 01101 ".Multiplier 630 can generate the preparatory address code of 10 bits accordingly
PAD1, wherein the bit value of preparatory address code PAD1 is " 0001010001 ".Multiplier 631 can generate the pre- of 10 bits accordingly
First address code PAD2, wherein the bit value of preparatory address code PAD2 is " 0010101001 ".Adder 640 will be above-mentioned two
After preparatory address code PAD1 is added with PAD2, preparatory address code PAD3 can produce, wherein the position of preparatory address code PAD3
First value is " 0011111010 ".Multiplier 640 can export the address AD with 10 bits accordingly, wherein the bit value of address AD
For " 0111110100 ".Above-mentioned Fig. 6 A and Fig. 6 B is merely illustrative, other coding electricity of various implementable address production electric circuits 224
Road should be considered as in practical range of the invention.
In conclusion different set-up modes, which are utilized, in transmitter provided by the present invention presets multiple groups look-up table, with
The error generated according to the received fundamental frequency signal elimination of the system operating condition of transmitter and institute by pulling effect.In this way,
The system effectiveness of transmitter and the precision of transmission signal are improved.
Although the present invention is disclosed as above with embodiment, so itself and the non-limiting present invention, anyone skilled in the art,
Without departing from the spirit and scope of the present invention, when can make various variation and retouching, therefore protection scope of the present invention is when view
Subject to appended claims institute defender.
Claims (10)
1. a kind of transmitter, which is characterized in that include a correction unit and an output unit；
Wherein, which includes:
One storage circuit, store a look-up table, wherein the look-up table record correspond to an in-phase data signal, an orthogonal function it is believed that
A correction data number with an at least system parameter；And
One first address production electric circuit is produced according to the in-phase data signal, the orthogonal data signals and an at least system parameter
Raw one first address, to export a correction signal by the correction data；And
The output unit generates a modulating signal for being mixed according to an oscillator signal to the correction signal, and amplifying should
Modulating signal, to generate an output signal.
2. transmitter as described in claim 1, wherein the correction data includes multiple first thermal compensation signals, and first address
Generation circuit selects the corresponding person in the multiple first thermal compensation signal from the look-up table according to first address, using as this
Correction signal.
3. transmitter as claimed in claim 2, wherein the look-up table is also recorded corresponding to before a previous in-phase data signal, one
Multiple second thermal compensation signals of secondary orthogonal data signals and an at least system parameter, and the correction unit also includes:
One delay circuit postpones the in-phase data signal and the orthogonal data signals, with generate the previous in-phase data signal with
The previous orthogonal data signals；
One second address production electric circuit, according to the previous in-phase data signal, the previous orthogonal data signals and an at least system
Parameter of uniting generates one second address, to select the corresponding person in the multiple second thermal compensation signal from the look-up table；And
One adder, pair being added in corresponding person and the multiple second thermal compensation signal in the multiple first thermal compensation signal
Ying Zhe, to generate the correction signal.
4. transmitter as described in claim 1, wherein the correction data includes multiple first phase correction signals and multiple the
Two phase correction signal, first address production electric circuit select the multiple first from the look-up table according to first address respectively
One corresponding person of one corresponding person of phase correction signal and the multiple second phase correction signal, and the correction unit also wraps
Contain:
One first multiplier, one fundamental frequency signal of multiplication and one first pre-compensation signal are to generate one first thermal compensation signal, to make
For the correction signal；
Wherein the fundamental frequency signal is formed by the in-phase data signal and the orthogonal data signals superposition, and first pre-compensation is believed
It number is changed by the corresponding person of the corresponding person and the multiple second phase correction signal of the multiple first phase correction signal
Add to be formed.
5. transmitter as claimed in claim 4, wherein the look-up table also records multiple third phase correction signals and multiple the
Four phase correction signals, and the correction unit also includes:
One delay circuit postpones the in-phase data signal and the orthogonal data signals, with generate a previous in-phase data signal with
One previous orthogonal data signals；
One second address production electric circuit, according to the previous in-phase data signal, the previous orthogonal data signals and an at least system
Parameter of uniting generates one second address, to select the corresponding person and choosing in the multiple third phase correction signal from the look-up table
Select the corresponding person in the multiple 4th phase correction signal；And
One second multiplier, one previous fundamental frequency signal of multiplication and one second pre-compensation signal are to generate one second thermal compensation signal；
One adder is added first thermal compensation signal and second thermal compensation signal, to generate the correction signal；
Wherein the previous fundamental frequency signal is formed by the previous in-phase data signal and the previous orthogonal data signals superposition, and this
Two pre-compensation signals by the multiple third phase correction signal the corresponding person and the multiple 4th phase correction signal
The corresponding person superposition formed.
6. transmitter as described in claim 1, wherein the correction data includes multiple first coefficients and multiple second coefficients, it is somebody's turn to do
First address production electric circuit selects the corresponding person in the multiple first coefficient according to first address respectively from the look-up table
With the corresponding person in the multiple second coefficient, and the correction unit also includes:
One first correction counting circuit, according in the multiple first coefficient the corresponding person, in the multiple second coefficient
The corresponding person, the in-phase data signal and the orthogonal data signals generate a first phase correction signal and a second phase is corrected
Signal；And
One first multiplier, one fundamental frequency signal of multiplication and one first pre-compensation signal are to generate one first thermal compensation signal, to make
For the correction signal；
Wherein the fundamental frequency signal is formed by the in-phase data signal and the orthogonal data signals superposition, and first pre-compensation is believed
It number is formed by the first phase correction signal and the second phase correction signal superposition.
7. transmitter as claimed in claim 6, wherein the correction data also includes multiple third coefficients and multiple 4th coefficients,
And the correction unit also includes:
One delay circuit postpones the in-phase data signal and the orthogonal data signals, with generate a previous in-phase data signal with
One previous orthogonal data signals；
One second address production electric circuit, according to the previous in-phase data signal, the previous orthogonal data signals and an at least system
Parameter of uniting generates one second address, to select the corresponding person in the multiple third coefficient and described more respectively from the look-up table
A corresponding person in a 4th coefficient；
One second correction counting circuit, according in the multiple third coefficient the corresponding person, in the multiple 4th coefficient
The corresponding person, the previous in-phase data signal and the previous orthogonal data signals generate one second pre-compensation signal；
One second multiplier, be multiplied a previous fundamental frequency signal and the second pre-compensation signal to generate one second thermal compensation signal,
Wherein the previous fundamental frequency signal is formed by the previous in-phase data signal and the previous orthogonal data signals superposition；And
One adder is added first thermal compensation signal and second thermal compensation signal, to generate the correction signal.
8. transmitter as claimed in claim 6, wherein the first correction counting circuit includes:
One second multiplier, square be multiplied the in-phase data signal, to generate one first operation values；
One third multiplier, square be multiplied the orthogonal data signals, to generate one second operation values；
One the 4th multiplier, the in-phase data signal that is multiplied and the orthogonal data signals, to generate a third operation values；
One subtracter subtracts each other first operation values and second operation values, to generate one the 4th operation values；
Corresponding person in one the 5th multiplier, the 4th operation values that are multiplied and the multiple first coefficient, to generate one the 5th
Operation values；
Corresponding person in one the 6th multiplier, the third operation values that are multiplied and the multiple second coefficient, to generate one the 6th
Operation values；
One adder is added the 5th operation values and the 6th operation values, to generate a phase error；And
One coordinate converter generates the first phase correction signal and the second phase correction signal according to the phase error.
9. transmitter as described in claim 1, wherein first address production electric circuit includes:
One data combiner merges the in-phase data signal and the orthogonal data signals, to generate a preparatory address code；And
One multiplier, be multiplied the preparatory address code and an at least system parameter, to generate first address.
10. transmitter as described in claim 1, wherein first address production electric circuit includes:
One first multiplier, square be multiplied the in-phase data signal, to generate one first coding in advance；
One second multiplier, square be multiplied the orthogonal data signals, to generate one second coding in advance；
One adder is added the first preparatory coding and the second preparatory coding, is encoded in advance with one third of generation；And
One third multiplier, the third that is multiplied encodes in advance and an at least system parameter, to generate first address.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511032176.6A CN106936451B (en) | 2015-12-31 | 2015-12-31 | Has the transmitter of pulling effect compensation mechanism |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511032176.6A CN106936451B (en) | 2015-12-31 | 2015-12-31 | Has the transmitter of pulling effect compensation mechanism |
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| CN106936451B true CN106936451B (en) | 2019-05-07 |
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| CN201511032176.6A Active CN106936451B (en) | 2015-12-31 | 2015-12-31 | Has the transmitter of pulling effect compensation mechanism |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007000632A2 (en) * | 2005-06-27 | 2007-01-04 | Nokia Corporation | Automatic receiver calibration with noise and fast fourier transform |
| CN101420242A (en) * | 2007-10-26 | 2009-04-29 | 瑞昱半导体股份有限公司 | Transmitter, receiver and regulating method thereof |
| CN203775241U (en) * | 2013-12-31 | 2014-08-13 | 天津朗波微电子有限公司 | Orthogonal mismatch correction circuit applied to transmitter in radio frequency transmitter-receiver |
-
2015
- 2015-12-31 CN CN201511032176.6A patent/CN106936451B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007000632A2 (en) * | 2005-06-27 | 2007-01-04 | Nokia Corporation | Automatic receiver calibration with noise and fast fourier transform |
| CN101420242A (en) * | 2007-10-26 | 2009-04-29 | 瑞昱半导体股份有限公司 | Transmitter, receiver and regulating method thereof |
| CN203775241U (en) * | 2013-12-31 | 2014-08-13 | 天津朗波微电子有限公司 | Orthogonal mismatch correction circuit applied to transmitter in radio frequency transmitter-receiver |
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| CN106936451A (en) | 2017-07-07 |
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