CN106934158A - Phase transition storage analogy method and system - Google Patents
Phase transition storage analogy method and system Download PDFInfo
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
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Abstract
The present invention relates to a kind of phase transition storage analogy method and system, detect be configured with Wear leveling algorithm when, obtain and write data of the number of times more than predetermined threshold value in memory block in each memory block, the data obtained from memory block are migrated using Wear leveling algorithm according to default time interval.After transactions requests are received, from Wear leveling algorithm is used extract data corresponding with transactions requests after Data Migration in corresponding memory block and be stored in current line Buffer Pool.According to transactions requests to the data simulation treatment in current line Buffer Pool, and export analog result.Data are migrated by using Wear leveling algorithm, write operation is distributed in memory block as homogeneously as possible, prevent part of storage block from prematurely being write bad, evade the short problem of phase transition storage service life more realistically to react the operative scenario of phase transition storage, preferably reflect the characteristic of phase transition storage, allow researchers more easily can carry out correlative study to phase transition storage.
Description
Technical field
The present invention relates to the analogue technique field of memory, more particularly to a kind of phase transition storage analogy method and it is
System.
Background technology
DRAM (dynamic random access memory, dynamic RAM) is a kind of the random of high speed
Memory is accessed, is the byte rank arbitrary access for supporting high speed the characteristics of its is maximum, therefore be largely used to internal memory field, base
This has turned into the standard memory device in internal memory market.DRAM using electric capacity as basic unit of storage, with the charging of electric capacity with put
Electric two states are maintained to represent 0/1 two kinds of data, and the voltage of the charged state of electric capacity needs stabilization, once power-off, electricity
Hold and return reset state, the data of preservation will also lose, i.e. DRAM is volatile devices.
DRAMSim2 is a DRAM simulators being widely used, it can each of accurate simulation DRAM operated
Journey, simulation precision reaches time rank.The state of each clock cycle of DRAMSim2 can be looked into, including in controller
Queue, the state of Bank (internal memory), refresh process, read-write process etc..And the statistical information output that can be simulated these is arrived
Archives.The simulation process of DRAMSim2 is based on Trace (track).Trace has been usually noted right under some typical applications
The access sequence of DRAM.In simulation process, DRAMSim2 order read access sequences simultaneously create corresponding access request and are sent to
Controller, by controller coordinate simulation process, and final output analog result.
Compared with DRAM, PCM (phase change memory, phase transition storage) possesses integrated level higher, lower
Energy consumption, the advantages of need not be periodically flushed and be non-volatile.PCM generally stores material substantially using sulfide as it, its storage number
According to two kinds of typicalnesses for depending on sulfide.One kind is crystalline state (low impedance state), the SET shapes of correspondence memory cell
State；Another kind is amorphous state (high impedance status), correspondence RESET state.Write operation can change both states of sulfide,
Two kinds of PCM write process：RESET operation increases high and of short duration transient current to memory cell, crystal moment is heated and is turned
Become amorphous state, and SET operation then applies that one low and rush of current long, makes sulfide have time enough to crystallize, so that
It is converted into crystalline state.
Due to being carried out using PCM product, research cost is high, and design is difficult, the reason such as experimental period is long, to the internal memory of PCM
The research of application is very limited, and how to allow PCM correlative study persons more easily to carry out correlative study is one urgently to be resolved hurrily
Problem.
The content of the invention
Based on this, it is necessary to regarding to the issue above, there is provided a kind of phase change memory for being easy to study phase transition storage
Device analogy method and system.
A kind of phase transition storage analogy method, comprises the following steps：
Detect be configured with Wear leveling algorithm when, obtain and write in each memory block in memory block number of times more than predetermined threshold value
Data；
The data obtained from the memory block are migrated using Wear leveling algorithm according to default time interval；
After transactions requests are received, the corresponding memory block from after Data Migration is carried out using the Wear leveling algorithm
It is middle to extract data corresponding with the transactions requests and be stored in current line Buffer Pool；
According to the transactions requests to the data simulation treatment in the current line Buffer Pool, and export simulation knot
Really.
A kind of phase transition storage simulation system, including：
Data acquisition module, for detect be configured with Wear leveling algorithm when, obtain in memory block in each memory block
Write data of the number of times more than predetermined threshold value；
Data Migration module, for according to default time interval using Wear leveling algorithm to being obtained from the memory block
The data for taking are migrated；
Data extraction module, for after transactions requests are received, being moved from data are carried out using the Wear leveling algorithm
Data corresponding with the transactions requests are extracted after shifting in corresponding memory block and is stored in current line Buffer Pool；
Data processing module, at according to the transactions requests to the data simulation in the current line Buffer Pool
Reason, and export analog result.
Above-mentioned phase transition storage analogy method and system, detect be configured with Wear leveling algorithm when, obtain memory block
Data of the number of times more than predetermined threshold value are write in interior each memory block, according to default time interval using Wear leveling algorithm to from depositing
The data obtained in storage block are migrated.After transactions requests are received, from after carrying out Data Migration using Wear leveling algorithm
Data corresponding with transactions requests are extracted in corresponding memory block and is stored in current line Buffer Pool.According to transactions requests to current
Data simulation treatment in row buffering pond, and export analog result.Data are simulated after transactions requests are received
Treatment, can be with the actual access behavior of analogue data, for memory system research provides prototype and theory analysis basis.For
The very sensitive life problems of phase transition storage material, by the number for being more than predetermined threshold value to writing number of times using Wear leveling algorithm
According to being migrated, write operation is distributed in memory block as homogeneously as possible, prevents part of storage block from prematurely being write bad, evade phase
The short problem of transition storage service life, more realistically to react the operative scenario of phase transition storage, can preferably reflect phase
The characteristic of transition storage, allows researchers more easily can carry out correlative study to phase transition storage.
Brief description of the drawings
Fig. 1 is the flow chart of phase transition storage analogy method in an embodiment；
Fig. 2 is the flow chart of phase transition storage analogy method in another embodiment；
Fig. 3 is the frame diagram of PCM simulators in an embodiment；
Fig. 4 is the schematic diagram of BankState classes modification in an embodiment；
Fig. 5 is the structure chart of phase transition storage simulation system in an embodiment；
Fig. 6 is the structure chart of phase transition storage simulation system in another embodiment.
Specific embodiment
PCM used as a kind of new storage material, all very similar with DRAM in very many performances, such as seek by byte
Location, access delay is in same order of magnitude etc. with DRAM so that PCM is expected to turn into the substitute of DRAM.But PCM also has it to lack
Point：Erasable energy consumption high and limited erasable number of times (i.e. the life-span is low), and life problems will likely be extensive as obstruction PCM
It is applied to the topmost factor in internal memory market.
Write operation is the main consume source of PCM.When PCM is repeatedly heated, sulfide will become no longer to stablize, crystalline state
Boundary between amorphous state thickens, finally cannot correct record information.The important indicator that the life-span is PCM is write,
Usually ten eight power.More than this boundary, PCM will become no longer available, write the life-span and also be paid close attention to the most as researchers
An index.Abrasion equilibrium is a kind of technology in conventional extension PCM life-spans, and its core concept is Data Migration：Frequency will be write
Numerous Data Migration to write free time data block so that the frequency of writing of each PCM cell is tried one's best uniformly, so as to postpone as far as possible
The out-of-service time of PCM.
In one embodiment, a kind of phase transition storage analogy method, as shown in figure 1, comprising the following steps：
Step S120：Detect be configured with Wear leveling algorithm when, to obtain that write number of times in each memory block in memory block big
In the data of predetermined threshold value.
When configuration Wear leveling algorithm has been detected, then data are migrated, if being configured without Wear leveling algorithm
Data Migration is not carried out then.Memory block can be divided into multiple memory blocks for data storage, the size of each memory block in advance
Can be the same or different.The specific value of predetermined threshold value is not also unique, can be adjusted according to actual conditions.Operating personnel can
According to the actual requirements, control central processing unit sends transactions requests and carries out accessing operation to the data stored in each memory block.Write
Number of times is more than the data of predetermined threshold value and writes frequent data item, by the reading and writing data in each memory block in monitor in real time memory block
Operation, frequent data item is write in each memory block of extraction.
Step S130：The data obtained from memory block are carried out using Wear leveling algorithm according to default time interval
Migration.
The specific value of default time interval is not also unique, and it can be specifically that will write frequent number that data be migrated
Frequent data item is write according in more data block, in moving to not or having the less data block for writing frequent data item.Abrasion is equal
The particular type for accounting method is not also unique, can be that one kind can also be that set is various.In the present embodiment, Wear leveling algorithm bag
Include Start-Gap algorithms and Security-Refresh algorithms, both algorithms not only effect is significant, and efficiency of algorithm is higher,
Expense is smaller.It is appreciated that user can also be according to selecting suitable Wear leveling algorithm the need for oneself.
In one embodiment, the data obtained from memory block are moved using Wear leveling algorithm in step S130
Move, including step 132 and step 134.
Step 132：The address of cache process of Wear leveling algorithm is called, the data that will be obtained from memory block are logically
Location is converted into physical address.The different Data Migrating Strategy of different Wear leveling algorithm correspondences and different address of cache are calculated
Method.Logical address is to write the address before frequent data item migration, and physical address is to write the data after frequent data item migration.
Step 134：Data Migration is performed according to physical address, and rejects transactions requests until Data Migration is completed.
Due to the actual storage address of data during migration and do not know, in order to ensure the correctness of data access, in data
Controller will reject all upper strata transactions requests in transition process.
PCM memory cell write number of times it is limited in the case of, Wear leveling algorithm by by write operation as homogeneously as possible
Memory block is distributed in, prevents partial data block from prematurely being write bad, the life-span is write so as to effectively improve PCM memory.And with
The standard configuration that abrasion equilibrium strategy has become PCM memory, various conventional abrasion equilibriums is directly integrated in simulator and is calculated
Method, not only enables simulator environment more conform to true PCM environment, is also very easy to use the PCM of simulator to study people
Member, can be placed in their characteristics of concern for more energy and time by they, how realize abrasion rather than flower
Account in method.The core of Wear leveling algorithm is address of cache and Data Migration.
Data Migration：Per at regular intervals, by fixed policy by data block migration.It is all afterwards for these data
Access will all be redirected to new address, and write operation is fifty-fifty mapped into whole memory space relatively.
Address of cache：After Data Migration occurs, the storage location of data has changed, when needing to access the data again
When, it is necessary to calculate the actual address of current accessed data, address of cache is the calculating from logical address to actual physical address
Method.
Step S140：It is corresponding from after Data Migration is carried out using Wear leveling algorithm after transactions requests are received
Data corresponding with transactions requests are extracted in memory block and is stored in current line Buffer Pool.
Transactions requests can specifically include read request and write request, and memory block includes multiple data for data storage
OK.Address of cache caused by Data Migration is carried out using Wear leveling algorithm, can be according to specific algorithm depending on.Specifically can first examine
Survey whether the data corresponding to transactions requests migrate, if directly being obtained according to original storage mapping relation without if
Access evidence is operated；In the event of migrating then in follow-up transactions requests are operated, carried out from Wear leveling algorithm is used
The data row of corresponding memory block finds data corresponding with transactions requests after Data Migration, and is stored in corresponding with the data row
In current line Buffer Pool, in order to be simulated treatment.
Step S150：According to transactions requests to the data simulation treatment in current line Buffer Pool, and export simulation knot
Really.
The data in current line Buffer Pool are read according to transactions requests and WriteMode treatment, and are exported analog result,
The actual access behavior of analogue data, for memory system research provides prototype and theory analysis basis.
In one embodiment, as shown in Fig. 2 after step S150, phase transition storage analogy method also includes step
S160。
Step S160：The monitoring each memory block in memory block writes number of times, will write number of times and reaches that correspondence is default to write depositing for life-span
In data copy to default replacement block in storage block, and correspondence replacement information is updated to replacement mapping table.
Each memory block be allocated in initialization one it is random write the life-span, if a memory block has reached its
The life-span is write, then the block cannot continue write operation.Problem for the short life of PCM carries out life-span management, the replacement for pre-setting
Block, shifts to writing data of the number of times in the memory block in its life-span, further improves the service life of PCM, truly
React the operative scenario of PCM.
Accordingly, when carrying out Data Migration in step S140, first will logically according to the mapping address algorithm of abrasion equilibrium
Whether location A is converted to logical address B, be replaced further according to the data replaced in mapping table detection address B, if then according to replacement
Information in mapping table finds actual physical address C and takes out data from the C of address, if otherwise directly being taken out from the B of address
Data.
Further, in one embodiment, before step S120, phase transition storage analogy method also includes step
S110。
Step S110：Piecemeal is carried out to memory block and obtains memory block, and each memory block distribution obedience normal state is divided at random
Cloth writes the life-span.
Memory block is carried out piecemeal obtain memory block mode it is not unique, memory block write the life-span obey be desired for μ, mark
Quasi- difference is normal state random distribution N (μ, the δ of δ2).Wherein μ and δ are available for configuration as parameter.The characteristic of normal distribution each side
All agree with very much the stochastic variable produced due to fabrication error, and normal distribution has also been widely used in describing such
Stochastic variable.
It is appreciated that in a preferred embodiment, phase transition storage analogy method can also include simultaneously step S110 and
Step S160, adds PCM life models to carry out memory block division and life-span management, PCM materials has been agreed with well very sensitive
Life problems.
In one embodiment, before step S140, phase transition storage analogy method is further comprising the steps of：
If current line Buffer Pool has been expired, the block that is eliminated in current line Buffer Pool is obtained, and detect the data of the block that is eliminated
Whether it is written over after being loaded.If so, then according to default replacement mapping table by revised write back data to corresponding
In memory block；If it is not, the corresponding data row of current line Buffer Pool then is set into the free time.
Current line Buffer Pool has completely referred to that the data of storage reach buffer memory capacity, it is impossible to add new data.Data from
Memory block is loaded into current line Buffer Pool and is processed again, if present transaction request data in current line Buffer Pool if
Need not load, read while write is carried out both for current line Buffer Pool, memory block will not be write.If data are not in current line
Buffer Pool is accomplished by preloading, if this when of current line Buffer Pool will completely eliminate a number of current line Buffer Pool
According to block, that is, be eliminated block.The specific strategy for searching the block that is eliminated is not unique, can be stored into earliest data block as quilt
Eliminate block, or the maximum data block of capacity as the block that is eliminated will be taken.If the block that is eliminated is being loaded into currently
Row buffering is written over behind pond, it is necessary to revised write back data to buffering area, if not being written over that direct replacement
Fall this part just.It is appreciated that when write back data is carried out, can judge to need the data institute of write-back by replacing mapping table
Memory block whether carried out bad block replace, if without if directly according to original storage mapping relation carry out data return
Write；Replaced in the event of bad block, then in the data block after the replacement that will be mapped in write back data to replacement mapping table.
For PCM, reading as data is nondestructive, and this is meant that when there is Bank conflicts, might not be needed
Data row in current line Buffer Pool is written back to memory block.Whether the data in forward Buffer Pool are written over judging
Whether write back data process is performed, more meets the real work scene of PCM, preferably reflect the characteristic of phase transition storage, enter one
Step is easy to the research to PCM.
Above-mentioned phase transition storage analogy method, is processed data simulation after transactions requests are received, and can be simulated
The actual access behavior of data, for memory system research provides prototype and theory analysis basis.For phase change memory equipment
The very sensitive life problems of matter, are migrated to writing number of times by using Wear leveling algorithm more than the data of predetermined threshold value,
Write operation is distributed in memory block as homogeneously as possible, prevents part of storage block from prematurely being write bad, evading phase transition storage makes
With the problem of short life, more realistically to react the operative scenario of phase transition storage, can preferably reflect phase transition storage
Characteristic, allows researchers more easily can carry out correlative study to phase transition storage.
In order to more fully understand above-mentioned phase transition storage analogy method, with reference to the PCM simulators based on Dramsim2
Carry out detailed explanation.
Experiment shows that PCM is closely similar on numerous characteristics with DRAM, such as byte addressing, read or write speed is approximate.
In internal structure, PCM and DRAM also uses identical framework.In view of the technology of DRAM is quite ripe, while industry is also
There is the simulator write specifically designed for DRAM, be improved on the basis of existing DRAM simulators so as to write PCM simulators just
Become feasible and relatively easy.
PCM simulators based on Dramsim2 do according to the property difference of DRAM and PCM on the basis of DRAMSim2
Go out following modification：There is leaky in the electric capacity for being used for preserving data in DRAM, and the sulfide material in PCM need not be any
Voltage can just preserve data, therefore PCM simulators do not need refresh process.The read procedure of DRAM is destructive reading, that is, work as
After certain row in Bank is read out to row buffering pond, the data in former cell row are lost immediately.When the data in row buffering pond will
Replaced by new row, the row being replaced has to be written back memory block, and this process is referred to as write-back.Because the read procedure of PCM is
It is nondestructive, therefore replaced row is not written over and do not need write-back.The electric capacity used in DRAM is several in charge and discharge process
Without loss, and the sulfide that PCM is used then can lentamente be lost in ablation process, therefore life problems set into PCM
Problem of greatest concern in standby.Increase life model on the basis of DRAMSim2, more realistically to react the yard of PCM
Scape.
By contrasting the similarities and differences of DRAM and PCM, corresponding modification is made on the basis of DRAM simulators DRAMSim2, obtained
To the PCM simulators based on Dramsim2 of the above-mentioned phase transition storage analogy method of application, Fig. 3 is the frame diagram of PCM simulators.
Concrete modification is as follows：
First, refresh process is cancelled
Because DRAM has adopted electric capacity data storage, and there is leaky in electric capacity, it is therefore desirable to regularly to the number of DRAM
Refreshed according to row.In fact, JEDEC (Joint Electron Device Engineering Council, joint electronics
Plant engineering meeting) standard regulation must be to Bank in 64ms every a line at least refresh once.In the realization of DRAMSim2
In, the refreshing between each Rank (row) and in each Rank between Bank is separate, and refresh process is by Memory Controller Hub
(Memory Controller classes) is triggered and controlled：During initialization, controller is that each Rank retains a timer, every
Individual time cycle, controller checks the timer of each Rank, puts a refresh command if the timer of certain Rank is zero
In the top of command queue.All Bank in the Rank can be placed in Flushing status by the order, and suspend read-write process until
Each Rank refreshes completion (needing the time of TRFC).But the two states that PCM adopts sulfide carry out data storage, at both
Under state, if without external force effect (usually write current), the state of memory cell is change that will not be over time and occurs
Transformation, therefore the state of memory cell need not be maintained using the refresh process of similar DRAM.Therefore on the basis of DRAMSim2
On directly skip refresh process.Specific practice is：Remove the Refresh Timer of each Rank in Memory Controller Hub.In week each time
Phase, also no longer each Rank is done and refreshed countdown inspection, no longer inserted refresh command to the command queue of Memory Controller Hub, and its
Its read-write process then maintains original order constant.
Cancel refresh process specific as follows：
Renewal in deletion MemoryController classes steplike function (update) to each Rank Refresh Timers, and
Do not reexamine.
It is REFRESH to delete in MemoryController classes steplike function (update) to current BusPacket types
Processing procedure, it is no longer necessary to.
It is the place of the Bank of REFRESH to delete in MemoryController classes steplike function (update) to current state
Reason process, it is no longer necessary to.
Delete Refresh Timer refreshCountdown member variables and construction letter in MemoryController classes
To the initialization of refreshCountdown in number.
Deletion CommandQueue classes go out the treatment in group function (pop) to refresh process, it is no longer necessary to.
To BusPacket types for REFRESH is treated in deletion Rank classes receiver function (receiveFromBus)
Journey, it is no longer necessary to.
REFRESH_PERIOD configuration items in sweep equipment configuration file, and delete configuration file reading class
(IniReader) to the relevant treatment of the configuration item in.The configuration item indicates the refresh cycle, it is no longer necessary to.
2nd, the write-back process in modification row buffering pond
DRAM carrys out data storage by the electronics in electric capacity, when the amplifier of passing through of a data in Bank amplifies and reads
Go out to Buffer Pool, the data in former memory cell will lose.This characteristic of DRAM is referred to as destructive reading, works as CPU
(Central Processing Unit, central processing unit) need access the Bank another row when, it is necessary to first by current cache
The data row in pond is written back to memory block, and the data row that then will will be accessed reads row buffering pond.Mono- complete reading of DRAM
Cycle is as follows：
Precharge (preactivate, the PREACTIVE) stage：After the completion of i.e. previous internal storage access, by current cache area
Data row is written back to memory block, and starts activation and will be accessed for data row.The time delay in the stage is generally represented with tRP.
Line activating (ACTIVE) stage：After i.e. row address activation command sends, row address is parsed and will be corresponding
Row data read row buffering pond, and begin to send out row read command.The stage time delay is generally represented with tRCD.
Row read (READ) stage：That is row read command sends, and column address is parsed and by the data read-out of corresponding unit to always
Line, a complete read cycle namely completion.The stage time delay is generally represented with CL.
For an internal memory read command, if target line has been activated, (i.e. current request accesses Bank's with previous request
Same a line), represent that the row data have been read out to row buffering pond, then read command is converted into a row read command.When work as
When preceding read command will cause Bank conflicts (i.e. current request accesses not going together for Bank with previous request), read command is translated into
Three orders, i.e. precharge, line activating and row read.
And for PCM, if need for the data row in Current buffer pond to be written back to memory block, depending on Current buffer pond
In data row whether changed (write operation) upon activation, if changed, need to be written back to memory block, otherwise not
Need write-back.The flow of one internal storage access order is：When target line has been activated, then visit order is converted into a row
Read command；When current accessed order causes Bank to conflict, and data row is not changed in Buffer Pool, and visit order is converted to preliminary filling
Bank is only set to the free time, does not carry out write-back by electricity, line activating and row reading order, precharge command now；When current
Visit order causes Bank to conflict, and data row in Buffer Pool, when being changed, visit order is converted to precharge, row and swashs
It is living to read three orders with row, and precharge command now performs real write back operations.
The precharge process for changing Bank is specific as follows：
Increase bool (Boolean type variable) type attribute in BankState (internal storage state) class：isBuffDirty.Should
Attribute then represents that the data row in row buffering pond is changed for true, and write-back is needed in pre-charging stage.If the attribute is
False then represents row buffering pond or is sky, or still end is changed upon activation.Fig. 4 lists amended BankState
Class.
After a Bank is activated (certain row is activated), the isBuffDirty attributes of the Bank are put into false.Specifically
For：Steplike function (update) is the processing procedure of ACTIVATE to BusPacket types in MemoryController classes
End, adds code below：
BankStates [rank] [bank] .isBuffDirty=false；
After a Bank completes write operation, the isBuffDirty attributes of the Bank are set to true.Specially：
Steplike function (update) is the processing procedure end of WRITE to BusPacket types in MemoryController classes, is added
Code below：
BankStates [rank] [bank] .isBuffDirty=true；
Change precharge (PRECHARGE) process of Bank：If the isBuffDirty of the Bank is false, directly jump
Go to next flow.If isBuffDirty is true, (process is all by time-consuming tRP clock to go to write-back process
Phase).Amended precharge processing procedure is as follows：
3rd, PCM life models are added
Compared with DRAM (erasing and writing life 10^12), the life-span of PCM (erasing and writing life 10^9) wants much shorter, and this is by respective
Storage material determine.Therefore in general, the simulator related to DRAM be all without consideration life problems, and for PCM
Simulator will must just be taken into account in the life-span in design, and also as the PCM life-spans set up rational model.
With access unit (JEDEC_DATA_BUS_BITS) piecemeal of data, each piecemeal is at the beginning of simulator for PCM memory blocks
Be allocated during beginningization one it is random write the life-span, if memory block reached it write the life-span, the block cannot continue
Write operation.
Specifically, several (nR) spare blocks will be increased in each Rank as standby pool, and a length reflecting for nR
Firing table.When a memory block writes number of times beyond its life-span (referred to as bad block), then take out one piece in standby pool and replaced, and will
In fallback relationship write-in mapping table.If new bad block occurs and standby pool exhausts, whole simulator is stopped.Introduce bad
After block standby pool, the browsing process to Rank will also change：Need first to check mapping table before accessing every time, if mapping table
In have the record of object block, then it is to access spare block that request is redirected.
Add the detailed process of life model as follows：
By each rank independent block, the size of each piecemeal is JEDEC_DATA_BUS_BITS.Due to each rank's
Size is：NUM_ROWS*NUM_COLS*NUM_BANKS*JEDEC_DATA_BUS_BITS, then each rank block count (nB)
For：The numbering of NUM_ROWS*NUM_COLS*NUM_BANKS, wherein each piecemeal is respectively row*col*bank.
One random event simulation device MR of construction, the chance event is obeyed and is desired for μ, and standard deviation is divided at random for the normal state of δ
Cloth N (μ, δ2), nB random number is generated using MR, this nB random number is then the life-span of each piecemeal in rank.
For each rank sets up the reserved mapping table that a size is nR.Every a line in mapping table be divided into two Addr and
Data, wherein Addr represent the piecemeal number replaced by current line, and Data is then the data for being replaced block, and size is that piecemeal is big
It is small.Addr is set to -1 when initial, represents the piecemeal do not replaced by the reservation row.
Address of cache process in rank is as follows：Take the bank of current BusPacket, the product conduct of row, col tri-
The address aB of piecemeal.The reserved mapping table of current rank is examined in, if being matched with aB in the presence of the Addr of certain row.Then take the row
Terminate as final address, address of cache the address of Data.If not finding occurrence, with original (bank, row, col) three
Tuple terminates as final address, mapping.
Each write operation is completed, and subtracts 1 by the life-span of writing of correspondence piecemeal.If the current age of piecemeal is zero, bad block is carried out
Replace.
Bad block replacement process is as follows in rank：The reserved mapping table of current rank is examined in, the row that Addr is -1 is searched.
Behavior rF is remembered if having, the bad replacement of block is carried out, if not finding, then it represents that reservation blocks have exhausted, write error is reported, replaced
Terminate.When carrying out block evil idea replacement, by the Data areas of the data copy of former piecemeal to rF, and the block number of former piecemeal is write rF's
Addr.Replacement process terminates.
4th, integral wear equalization algorithm
A transaction queues (Transaction Queue) are provided with Dramsim2, in Memory Controller Hub.Work as execution
When updating (Update) operation, affairs are parsed into corresponding bus line command one by one, are then added in command queue, this
Operation needs for transaction address (namely internal storage access address) to be converted into corresponding [Rank, Bank, Row, Col] four-tuple, this
Individual process is referred to as address of cache.Address of cache is divided into two processes in PCM simulators：Abrasion equilibrium address of cache and routinely
Location maps, and the address of cache of abrasion equilibrium will be mapped into row, the output conduct of abrasion equilibrium address of cache prior to conventional address
The input of conventional address of cache.Address of cache schematic diagram is given in Fig. 3.
Memory Controller Hub in due course can trigger data transition process, this opportunity depends on the specific calculation for using
Method.When Data Migration occurs, the corresponding read-write affairs of Data Migration are added transaction queues by controller, and wait affairs complete
Into controller will reject all upper strata transactions requests in data migration process.
PCM simulators are integrated with two kinds of the more commonly used Wear leveling algorithms：Start-Gap and Security-Refresh
Algorithm.Both algorithms not only should be relatively wide, also represent two kinds of classifications (Memory Controller Hub level and the Bank of Wear leveling algorithm
Level Wear leveling algorithm).
Realize that details is as follows for Start-Gap algorithms：
Whole storage address is divided into Num_Regions subregion, each subregion is by independent operating Start-Gap algorithms.
It is unit piecemeal that each subregion is pressed into Line_Size (Line_Size is the integral multiple of JEDEC_DATA_BUS_BITS).
One migration queue (migrationQueue) of initialization, the queue indicates currently have which subregion is carrying out data
Migration, is empty when initial.
The metadata of each subregion includes：Start pointers, Gap pointers, Data Migration timer DMCD, and size is
The Gap blocks of Line_Size.Start pointers point to No. 0 block, Gap pointers and point to Gap blocks when initial, and DMCD is set to migration interval.
Before each Transaction is added into transaction queues, the address of cache of Start-Gap algorithms is first called, will
Virtual address is converted into physical address, and address of cache will be carried out according to Start pointers with Gap pointers.
Each write operation is completed, and subtracts 1 by DMCD, when DMCD is kept to 0, calls the data migration process of the subregion.
Data migration process：
A. current bay pointer is added into migration queue.
B. the data block pointed by Gap-1 is read, corresponding read request is generated and is added to transaction queues.If Gap pointers refer to
To Gap blocks, then the subregion last block is read.Gap blocks are read if being zero if Gap pointers.
C. after having read data, the data block pointed by Gap pointers is write data into, generates corresponding write request and add
To transaction queues.
D.Gap pointers subtract 1.If current Gap pointers are zero, Gap pointers points to Gap blocks, while adding 1 by Start pointers.
E. current bay pointer is removed into migration queue.DMCD is reset into migration interval.
Condition judgment is added in the WillAcceptTransaction methods of MemoryController：Migration queue
Not for space-time directly returns to false.Namely no longer receive to calculate the request of CPU during Data Migration generation.
Integrated Security-Refresh algorithms：
Security-Refresh algorithms will realize mill for security consideration (preventing malicious attack) inside each Bank
Damage equalization algorithm.The algorithm progressively carries out Data Migration by mapping key (key) is regularly updated, equal so as to reach abrasion
The effect of weighing apparatus.Realize that details is as follows for Security-Refresh algorithms：
By each Bank, according to Line_Size, for unit is divided into nBlock blocks, (Line_Size is JEDEC_DATA_
The integral multiple of BUS_BITS), Line_Size is the unit of Data Migration.
Initialization Bank metadata：Including last round of mapping key PK=0, CK is [0, nBlock] interval random number,
Current refresh pointer CRP=0, Data Migration timer DMCD=migration interval.
Each Bank calls the address of cache process of Security-Refresh by currently before read-write, first
The access address of BusPacket is converted into physical address from logical address.Address of cache and PK, CK and CRP are relevant.
Each write operation is completed, and subtracts 1 by DMCD, when DMCD is kept to 0, calls the data migration process of the subregion.
Data migration process：
A. CRP^PK=arp, CPR^CK=arc are calculated.The two numbers represent two blocks for being currently needed for exchange data
Number.
B. arp, two data of piecemeal of arc are exchanged.
C. to the increased direction retrieval of block number since CRP pointers.Search first not yet exchange data in epicycle
Block.The block aBlock of not yet exchange data meets relation：aBlock^CK^PK>CRP.CRP is pointed into the block number if finding.
Represent that the wheel Data Migration has been completed if it can not find, start new round Data Migration (d).
D. new round exchange is started：Generate mapping keys of the random number n in [0, nBlock] interval as the wheel.By CK
PK is set to, PK is set to n, and CRP sets to 0, while DMCD is reset into migration interval.
PCM simulators based on Dramsim2 be able to can be simulated to the level research and analysis of phase transition storage memory system
The actual access behavior of data, for memory system research provides prototype and theory analysis basis.Simulator can repeat profit
With being that cost has been saved in other simulations for PCM.In the PCM simulators based on Dramsim2 integral life management and
Wear leveling algorithm, there is provided relevant interface gives other PCM researchers, can use corresponding algorithm for the research of oneself
Evade the short problem of PCM service lifes, improve performance.
In one embodiment, a kind of phase transition storage simulation system, as shown in figure 5, including data acquisition module 120,
Data Migration module 130, data extraction module 140 and data processing module 150.
Data acquisition module 120 be used for detect be configured with Wear leveling algorithm when, obtain memory block in each memory block
In write number of times more than predetermined threshold value data.
When configuration Wear leveling algorithm has been detected, then data are migrated, if being configured without Wear leveling algorithm
Data Migration is not carried out then.The specific value of predetermined threshold value is not also unique, can be adjusted according to actual conditions.Operating personnel can root
According to actual demand, control central processing unit sends transactions requests and carries out accessing operation to the data stored in each memory block.Write secondary
Number is more than the data of predetermined threshold value and writes frequent data item, is grasped by the reading and writing data in each memory block in monitor in real time memory block
Make, frequent data item is write in each memory block of extraction.
Data Migration module 130 is used for according to default time interval using Wear leveling algorithm to being obtained from memory block
Data migrated.
The specific value of default time interval is not also unique, and it can be specifically that will write frequent number that data be migrated
Frequent data item is write according in more data block, in moving to not or having the less data block for writing frequent data item.This implementation
In example, Wear leveling algorithm includes Start-Gap algorithms and Security-Refresh algorithms, and not only effect shows both algorithms
Write, and efficiency of algorithm is higher, expense is smaller.It is appreciated that user can also be equal according to the suitable abrasion of selection the need for oneself
Account method.
In one embodiment, Data Migration module 130 includes address conversioning unit and data migration unit.
Address conversioning unit is used to call the address of cache process of Wear leveling algorithm according to default time interval, will be from
The logical address of the data obtained in memory block is converted into physical address.The different data of different Wear leveling algorithm correspondences are moved
Move tactful and different mapping address algorithm.Logical address is to write the address before frequent data item migration, and physical address is to write frequency
Data after numerous Data Migration.
Data migration unit is used to perform Data Migration according to physical address, and rejects transactions requests until data are moved
Move and complete.Due to the actual storage address of data during migration and do not know, in order to ensure the correctness of data access,
Controller will reject all upper strata transactions requests in data migration process.
Data extraction module 140 is used for after transactions requests are received, and data are carried out from using the Wear leveling algorithm
Data corresponding with transactions requests are extracted after migration in corresponding memory block and is stored in current line Buffer Pool.
Transactions requests can specifically include read request and write request, and memory block includes multiple data for data storage
OK, the data row of corresponding memory block finds number corresponding with transactions requests from after Data Migration is carried out using Wear leveling algorithm
According to, and be stored in current line Buffer Pool corresponding with the data row, in order to be simulated treatment.
Data processing module 150 is used for according to transactions requests to the data simulation treatment in current line Buffer Pool, and
Output analog result.
The data in current line Buffer Pool are read according to transactions requests and WriteMode treatment, and are exported analog result,
The actual access behavior of analogue data, for memory system research provides prototype and theory analysis basis.
In one embodiment, as shown in fig. 6, phase transition storage simulation system also includes life-span monitoring modular 160.
Life-span monitoring modular 160 is used in data processing module 150 according to transactions requests to the number in current line Buffer Pool
Processed according to simulation, and after exporting analog result, the monitoring each memory block in memory block writes number of times, will write number of times and reaches correspondence
In data copy to default replacement block in the default memory block for writing the life-span, and correspondence replacement information is updated to default
Replace mapping table.
Each memory block be allocated in initialization one it is random write the life-span, if a memory block has reached its
The life-span is write, then the block cannot continue write operation.Problem for the short life of PCM carries out life-span management, the replacement for pre-setting
Block, shifts to writing data of the number of times in the memory block in its life-span, further improves the service life of PCM, truly
React the operative scenario of PCM.
Accordingly, when data extraction module 140 carries out Data Migration, will first be patrolled according to the mapping address algorithm of abrasion equilibrium
Collect address A and be converted to logical address B, whether be replaced further according to the data replaced in mapping table detection address B, if then basis
The information replaced in mapping table finds actual physical address C and takes out data from the C of address, if otherwise directly from the B of address
Take out data.
Further, in one embodiment, phase transition storage simulation system also includes memory block piecemeal module 110.
Memory block piecemeal module 110 is big for writing number of times in each memory block in the acquisition of data acquisition module 120 memory block
Before the data of predetermined threshold value, piecemeal is carried out to memory block and obtains memory block, and the distribution of each memory block is obeyed normal state with
What machine was distributed writes the life-span.
Memory block is carried out piecemeal obtain memory block mode it is not unique, memory block write the life-span obey be desired for μ, mark
Quasi- difference is normal state random distribution N (μ, the δ of δ2).Wherein μ and δ are available for configuration as parameter.The characteristic of normal distribution each side
All agree with very much the stochastic variable produced due to fabrication error, and normal distribution has also been widely used in describing such
Stochastic variable.
It is appreciated that in a preferred embodiment, phase transition storage simulation system can also simultaneously include memory block piecemeal
Module 110 and life-span monitoring modular 160, add PCM life models to carry out memory block division and life-span management, agree with well
The very sensitive life problems of PCM materials.
In one embodiment, phase transition storage simulation system also includes data detection module.
Data detection module is used in data extraction module 140 after transactions requests are received, wear and tear equal from using described
The method of accounting extract data corresponding with transactions requests in corresponding memory block after Data Migration and be stored in current row buffering
Before in pond, if current line Buffer Pool has been expired, be eliminated block in the acquisition current line Buffer Pool, and the block that is eliminated described in detection
Data whether be written over after being loaded；If so, then according to it is default replacement mapping table by revised write back data extremely
In corresponding memory block；If it is not, the corresponding data row of current line Buffer Pool then is set into the free time.
Whether the data in forward Buffer Pool are written over judging whether to perform write back data process, more meet PCM
Real work scene, preferably reflect phase transition storage characteristic, be further easy to the research to PCM.
Data are entered simulation treatment by above-mentioned phase transition storage simulation system after transactions requests are received, can be with mould
Intend the actual access behavior of data, for memory system research provides prototype and theory analysis basis.For phase transition storage
The very sensitive life problems of material, are moved to writing number of times by using Wear leveling algorithm more than the data of predetermined threshold value
Move, write operation is distributed in memory block as homogeneously as possible, prevent part of storage block from prematurely being write bad, evade phase transition storage
The short problem of service life, more realistically to react the operative scenario of phase transition storage, can preferably reflect phase transition storage
Characteristic, allow researchers more easily can carry out correlative study to phase transition storage.
Each technical characteristic of embodiment described above can be combined arbitrarily, to make description succinct, not to above-mentioned reality
Apply all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, the scope of this specification record is all considered to be.
Embodiment described above only expresses several embodiments of the invention, and its description is more specific and detailed, but simultaneously
Can not therefore be construed as limiting the scope of the patent.It should be pointed out that coming for one of ordinary skill in the art
Say, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to protection of the invention
Scope.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (10)
1. a kind of phase transition storage analogy method, it is characterised in that comprise the following steps：
Detect be configured with Wear leveling algorithm when, obtain and write in each memory block in memory block number of the number of times more than predetermined threshold value
According to；
The data obtained from the memory block are migrated using Wear leveling algorithm according to default time interval；
After transactions requests are received, carried in corresponding memory block after Data Migration is carried out using the Wear leveling algorithm
Take data corresponding with the transactions requests and be stored in current line Buffer Pool；
According to the transactions requests to the data simulation treatment in the current line Buffer Pool, and export analog result.
2. phase transition storage analogy method according to claim 1, it is characterised in that described according to the transactions requests pair
Data simulation treatment in the current line Buffer Pool, and the step of export analog result after, it is further comprising the steps of：
Monitor each memory block in the memory block writes number of times, will write the number during number of times reaches the default memory block for writing the life-span of correspondence
According to being copied in default replacement block, and correspondence replacement information is updated to default replacement mapping table.
3. phase transition storage analogy method according to claim 2, it is characterised in that described to be configured with abrasion detecting
During equalization algorithm, obtain write in each memory block in memory block number of times more than predetermined threshold value data the step of before, also including with
Lower step：
Piecemeal is carried out to the memory block and obtains memory block, and the longevity is write to each memory block distribution obedience normal state random distribution
Life.
4. phase transition storage analogy method according to claim 1, it is characterised in that the use Wear leveling algorithm pair
The data obtained from the memory block are migrated, including：
The address of cache process of Wear leveling algorithm is called, the logical address of the data obtained from the memory block is converted into
Physical address；
Data Migration is performed according to the physical address, and rejects transactions requests until Data Migration is completed.
5. phase transition storage analogy method according to claim 1, it is characterised in that described to receive transactions requests
Afterwards, extract corresponding with the transactions requests in memory block corresponding after Data Migration is carried out using the Wear leveling algorithm
Data and the step that is stored in current line Buffer Pool before, it is further comprising the steps of：
If current line Buffer Pool has been expired, the block that is eliminated in the current line Buffer Pool is obtained, and the block that is eliminated described in detection
Whether data are written over after being loaded；
If so, then according to default replacement mapping table by revised write back data to corresponding memory block；
If it is not, the corresponding data row of current line Buffer Pool then is set into the free time.
6. a kind of phase transition storage simulation system, it is characterised in that including：
Data acquisition module, for detect be configured with Wear leveling algorithm when, obtain and write in each memory block in memory block time
Data of the number more than predetermined threshold value；
Data Migration module, for using Wear leveling algorithm to the acquisition from the memory block according to default time interval
Data are migrated；
Data extraction module, for after transactions requests are received, from after carrying out Data Migration using the Wear leveling algorithm
Data corresponding with the transactions requests are extracted in corresponding memory block and is stored in current line Buffer Pool；
Data processing module, for being processed the data simulation in the current line Buffer Pool according to the transactions requests,
And export analog result.
7. phase transition storage simulation system according to claim 6, it is characterised in that also include：
Life-span monitoring modular, in the data processing module according to the transactions requests in the current line Buffer Pool
Data simulation is processed, and after exporting analog result, monitor each memory block in memory block writes number of times, will write number of times and reaches
To in data copy to the default replacement block in the default memory block for writing the life-span of correspondence, and correspondence replacement information is updated to
Default replacement mapping table.
8. phase transition storage simulation system according to claim 7, it is characterised in that also include：
Memory block piecemeal module, write in each memory block in memory block number of times more than default for being obtained in the data acquisition module
Before the data of threshold value, piecemeal is carried out to the memory block and obtains memory block, and it is random to obey normal state to the distribution of each memory block
What is be distributed writes the life-span.
9. phase transition storage simulation system according to claim 6, it is characterised in that the Data Migration module includes：
Address conversioning unit, the address of cache process for calling Wear leveling algorithm according to default time interval will be from institute
The logical address for stating the data obtained in memory block is converted into physical address；
Data migration unit, for performing Data Migration according to the physical address, and rejects transactions requests until data
Migration is completed.
10. phase transition storage simulation system according to claim 6, it is characterised in that also include：
Data detection module, in the data extraction module after transactions requests are received, from use the abrasion equilibrium
Algorithm extract data corresponding with the transactions requests and be stored in current line in corresponding memory block after Data Migration delaying
Before rushing in pond, if current line Buffer Pool has been expired, be eliminated block in the acquisition current line Buffer Pool, and is eliminated described in detection
Whether the data of block are written over after being loaded；If so, then according to default mapping table of replacing by revised write back data
Into corresponding memory block；If it is not, the corresponding data row of current line Buffer Pool then is set into the free time.
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