CN106933716A - A kind of embedded memory simulation test development platform is erroneously inserted mechanism - Google Patents
A kind of embedded memory simulation test development platform is erroneously inserted mechanism Download PDFInfo
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- CN106933716A CN106933716A CN201511032635.0A CN201511032635A CN106933716A CN 106933716 A CN106933716 A CN 106933716A CN 201511032635 A CN201511032635 A CN 201511032635A CN 106933716 A CN106933716 A CN 106933716A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
- G06F11/2733—Test interface between tester and unit under test
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
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- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Mechanism is erroneously inserted the invention provides a kind of embedded memory simulation test development platform, including system and method, system and method are respectively provided with and use in embedded memory simulation test development platform, platform includes device systems and test system, device systems are used to simulate embedded memory, and test system is used to simulate extraneous PC, realizes the test to device systems, insertion for simulating embedded memory error message, while including：Error listing module, is provided with error listing, the error message for recording all insertions；Error module is set, and for the setting of mistake, test system handle is erroneously inserted in error listing；Error module is checked, for traveling through error listing, type, the numerical value of mistake is checked；Triggering error module, for returning an error to device systems.The present invention is simple and easy to apply, meets the demand tested the recognition capability of FTL wrong data.
Description
Technical field
The present invention relates to computer realm, more particularly to a kind of embedded memory simulation test development platform
Be erroneously inserted mechanism.
Background technology
Embedded memory (Embedded Multi Media Card, eMMC) be it is a kind of mainly in
The embedded memory of the electronic equipment such as mobile phone or panel computer.Wherein, contained in embedded memory
Nand Flash, at present, Nand Flash are increasingly becoming one of primary storage medium of embedded system,
The data bulky complex for being stored, it is necessary to managed using file system.
For the ease of the data on management Nand Flash, introduce FTL (Flash Translation Layer,
File transport layer), once FTL goes wrong, then and reading and writing data can be made to make a mistake, it is even more serious
Be that embedded memory cannot be accessed；As can be seen here, the stability and efficiency of FTL are deposited to embedded
It is most important for reservoir.Data in application FTL is to eMMC on Nand Flash are managed
When, FTL should be tested first, wherein one of important content tested is exactly FTL to mistake
The recognition capability of data.
In the prior art, it is necessary to constantly access on Nand Flash in the test process of FTL
Data, the stability and efficiency of FTL are judged by feedback result, including the stabilization recognized to wrong data
Property and efficiency, therefore, use simulation Nand Flash devices storage test data in, it is necessary to enough
Enough wrong data, it is clear that how to obtain enough wrong data is the important technical links for testing FTL.
The content of the invention
In consideration of it, the embodiment of the present invention provides a kind of mistake of embedded memory simulation test development platform
Insertion mechanism, system and method is simple and easy to apply, meets and the recognition capability of FTL wrong data is tested
Demand.
The embodiment of the invention provides a kind of being erroneously inserted for embedded memory simulation test development platform
System, the system is arranged in embedded memory simulation test development platform, and the platform includes setting
Standby system and test system, the device systems are used to simulate embedded memory, and the test system is used
In simulation external world PC, the test to device systems is realized, it is characterised in that for simulating embedded depositing
The insertion of reservoir error message, including：
Error listing module, is provided with error listing, the error message for recording all insertions；
Error module is set, and for the setting of mistake, test system handle is erroneously inserted in error listing；
Error module is checked, for traveling through error listing, type, the numerical value of mistake is checked；
Triggering error module, for returning an error to device systems.
Preferably, the device systems include front end hardware analog module, file transport layer FTL and bag
The back-end hardware analog module of NAND analog modules is included, the front end hardware analog module is with test
System connection, for the parsing to test command and the transmission of test command and data, FTL is hard with front end
Part analog module is connected, and for analyzing the identification of test command and wrong data, and data is entered into row address
Data are stored in back-end hardware analog module by mapping management, and back-end hardware analog module is connected with FTL,
For the storage of data,
The triggering error module, for returning an error to device systems back-end hardware analog module.
Preferably, the setting error module, including：
Wrong interface, is erroneously inserted in error listing for the test system by wrong interface handle.
On the other hand, the invention also discloses a kind of mistake of embedded memory simulation test development platform
Insertion method, methods described is performed in embedded memory simulation test development platform, the platform bag
Device systems and test system are included, the device systems are used to simulate embedded memory, the test system
Unite for simulating extraneous PC, realize the test to device systems, it is characterised in that
Including：
Error procedure is set, mistake is set, test system handle is erroneously inserted in error listing；
Error procedure is checked, error listing is traveled through, type, the numerical value of mistake is checked；
Triggering error procedure, returns an error to device systems.
Preferably, methods described is performed in embedded memory simulation test development platform, the equipment
After system is including front end hardware analog module, file transport layer FTL and including NAND analog modules
End hardware simulation module, the front end hardware analog module is connected with test system, for test command
Parsing and test command and data transmission, FTL is connected with front end hardware analog module, for point
The identification of analysis test command and wrong data, and data are carried out into address of cache management, after data are stored in
End hardware simulation module, back-end hardware analog module is connected with FTL, for the storage of data,
The triggering error procedure, returns an error to device systems back-end hardware analog module；
Identification error procedure, FTL identification wrong data, and report test system.
Preferably, the setting error procedure, including：
The test system is erroneously inserted in error listing by wrong interface handle.
The present invention has advantages below：
Mechanism is erroneously inserted the invention provides a kind of embedded memory simulation test development platform, i.e.,
System and method is erroneously inserted, the system is arranged in embedded memory simulation test development platform, side
Method is also performed in embedded memory simulation test development platform, for simulating embedded memory mistake
The insertion of information, the need for satisfaction is tested FTL, it is easy to operate and use.
Brief description of the drawings
Fig. 1 is that a kind of system that is erroneously inserted of embedded memory simulation test development platform of the invention is implemented
The structure chart of example 1；
Fig. 2 is that a kind of system that is erroneously inserted of embedded memory simulation test development platform of the invention is implemented
The structure chart of example 2；
Fig. 3 is that a kind of method that is erroneously inserted of embedded memory simulation test development platform of the invention is implemented
The flow chart of example 1；
Fig. 4 is that a kind of embedded memory simulation test development platform of the invention is erroneously inserted method reality
Apply the flow chart of example 2.
Specific embodiment
To enable the above objects, features and advantages of the present invention more obvious understandable, below in conjunction with the accompanying drawings
The present invention is further detailed explanation with specific embodiment.
Reference picture 1, shows that a kind of mistake of embedded memory simulation test development platform of the invention is inserted
Enter the structure chart of the embodiment 1 of system 103, the system is arranged on the exploitation of embedded memory simulation test
In platform, the platform includes device systems 101 and test system 102, and the device systems 101 are used
In simulation embedded memory, the test system 102 is used to simulate extraneous PC, realizes to equipment system
The test of system 101, the device systems 101 include front end hardware analog module 111, file transport layer
FTL121 and the back-end hardware analog module 131 including NAND analog modules 1311, the front end are hard
Part analog module 111 is connected with test system 102, for the parsing to test command and test command
With the transmission of data, FTL121 is connected with front end hardware analog module 111, for analyzing test command
With the identification of wrong data, and data are carried out into address of cache management, data are stored in back-end hardware simulation
Module 131, back-end hardware analog module 131 is connected with FTL121, for the storage of data,
This is erroneously inserted system 103 is used to simulate the insertion of embedded memory error message, including：
Error listing module 113, is provided with error listing, the error message for recording all insertions；
Error module 143 is set, and for the setting of mistake, test system handle is erroneously inserted in error listing；
Error module 133 is checked, for traveling through error listing, type, the numerical value of mistake is checked；
Triggering error module 123, for returning an error to device systems back-end hardware analog module 131,
It is NAND analog modules 1311.
Reference picture 2, shows that a kind of mistake of embedded memory simulation test development platform of the invention is inserted
Enter the structure chart of the embodiment 2 of system 203, the system is arranged on the exploitation of embedded memory simulation test
In platform, the platform includes device systems 201 and test system 202, and the device systems 201 are used
In simulation embedded memory, the test system 202 is used to simulate extraneous PC, realizes to equipment system
The test of system 201, the device systems 201 include front end hardware analog module 211, file transport layer
FTL221 and the back-end hardware analog module 231 including NAND analog modules 2311, the front end are hard
Part analog module 211 is connected with test system 202, for the parsing to test command and test command
With the transmission of data, FTL221 is connected with front end hardware analog module 211, for analyzing test command
With the identification of wrong data, and data are carried out into address of cache management, data are stored in back-end hardware simulation
Module 231, back-end hardware analog module 231 is connected with FTL221, for the storage of data,
This is erroneously inserted system 203 is used to simulate the insertion of embedded memory error message, including：
Error listing module 213, is provided with error listing, the error message for recording all insertions；
Error module 243 is set, and for the setting of mistake, test system handle is erroneously inserted in error listing；
Error module 233 is checked, for traveling through error listing, type, the numerical value of mistake is checked；
Triggering error module 223, for returning an error to device systems back-end hardware analog module 231, i.e.,
It is NAND analog modules 2311.
The setting error module 243, including：
Wrong interface 2431, is erroneously inserted for the test system 202 by wrong interface 2431
In error listing.
Reference picture 3, shows a kind of mistake of embedded memory simulation test development platform of the invention
The flow chart of insertion method embodiment 1, methods described is in embedded memory simulation test development platform
Perform, the platform includes device systems and test system, the device systems are used to simulate embedded depositing
Reservoir, the test system is used to simulate extraneous PC, realizes the test to device systems, the equipment
After system is including front end hardware analog module, file transport layer FTL and including NAND analog modules
End hardware simulation module, the front end hardware analog module is connected with test system, for test command
Parsing and test command and data transmission, FTL is connected with front end hardware analog module, for point
The identification of analysis test command and wrong data, and data are carried out into address of cache management, after data are stored in
End hardware simulation module, back-end hardware analog module is connected with FTL, for the storage of data,
This is erroneously inserted method includes：
Error procedure 301 is set, mistake is set, test system is erroneously inserted mistake by wrong interface handle
In list；
Error procedure 302 is checked, error listing is traveled through, type, the numerical value of mistake is checked；
Triggering error procedure 303, it is NAND to return an error to device systems back-end hardware analog module
Analog module；
Also include that FTL recognizes error procedure 304, FTL identification wrong data, and report test system.
Reference picture 4, shows a kind of mistake of embedded memory simulation test development platform of the invention
The flow chart of insertion method embodiment 2, the embodiment introduces use-case and carrys out further description this mistake
Insertion method, the method that is mistakenly inserted is performed in embedded memory simulation test development platform, described
Platform includes device systems 401 and test system 402, and the device systems 401 are embedded for simulating
Memory, the test system is used to simulate extraneous PC, realizes the test to device systems 402, institute
Device systems 401 are stated including front end hardware analog module, file transport layer FTL and including NAND moulds
Intend the back-end hardware analog module of module, the front end hardware analog module is connected with test system, is used for
The transmission of parsing and test command and data to test command, FTL connects with front end hardware analog module
Connect, the identification for analyzing test command and wrong data, and data are carried out into address of cache management, will
Data are stored in back-end hardware analog module, and back-end hardware analog module is connected with FTL, for depositing for data
Storage,
This is erroneously inserted method includes：
Use-case is set up：The use-case of test system 402 starts and starts；
Error procedure 403 is set, mistake is set, test system 402 is erroneously inserted by wrong interface handle
In error listing；
The beginning NAND of 402 commander equipment system of test system 401 analog modules (write, read,
Wipe sassafras) operation 404；
Set after the completion of error procedure 403, carry out checking error procedure 405, travel through error listing, bag
The type for checking mistake is included, write error, read error, sassafras mistake, and erroneous values is wiped；
Check after the completion of error procedure 405, carry out triggering error procedure 406, return an error to equipment system
System back-end hardware analog module is NAND analog modules；
After the completion of triggering error procedure 406, test system 402 starts to perform transmission FTL access NAND
Analog module commands steps 407；
FTL identification error procedures 408 are proceeded by afterwards, and report test system by recognition result；
Finally perform use-case and destroy step 409, complete to use use-case process.
Each embodiment in its this specification is described by the way of progressive, each embodiment emphasis
What is illustrated is all the difference with other embodiment, and identical similar part is mutual between each embodiment
Referring to.For embodiment of the method, because it is substantially similar to system embodiment, so description
It is fairly simple, the relevent part can refer to the partial explaination of embodiments of method.
A kind of mistake of embedded memory simulation test development platform provided by the present invention is inserted above
Enter mechanism (system and method), be described in detail, specific case used herein is to the present invention
Principle and implementation method be set forth, the explanation of above example is only intended to help and understands the present invention
Method and its core concept；Simultaneously for those of ordinary skill in the art, according to think of of the invention
Think, will change in specific embodiments and applications, in sum, in this specification
Appearance should not be construed as limiting the invention.
Claims (6)
1. a kind of embedded memory simulation test development platform is erroneously inserted system, it is characterised in that
The system is arranged in embedded memory simulation test development platform, and the platform includes device systems
And test system, for simulating embedded memory, the test system is for simulating for the device systems
Extraneous PC, realizes the test to device systems, and the system is used to simulate embedded memory mistake letter
The insertion of breath, including：
Error listing module, is provided with error listing, the error message for recording all insertions；
Error module is set, and for the setting of mistake, test system handle is erroneously inserted in error listing；
Error module is checked, for traveling through error listing, type, the numerical value of mistake is checked；
Triggering error module, for returning an error to device systems.
2. system is erroneously inserted as claimed in claim 1, it is characterised in that：The device systems bag
Include front end hardware analog module, file transport layer FTL and the back-end hardware including NAND analog modules
Analog module；
The front end hardware analog module is connected with test system, for parsing and survey to test command
Examination order and the transmission of data；
The file transport layer FTL is connected with front end hardware analog module, for analyzing test command and mistake
The identification of data by mistake, and data are carried out into address of cache management, data are stored in back-end hardware analog module；
The back-end hardware analog module is connected with FTL, for the storage of data；
The triggering error module, for returning an error to device systems back-end hardware analog module.
3. system is erroneously inserted as claimed in claim 1 or 2, it is characterised in that the setting is wrong
Module is missed, including：
Wrong interface, the test system is erroneously inserted in error listing by wrong interface handle.
4. a kind of embedded memory simulation test development platform is erroneously inserted method, it is characterised in that
Methods described is performed in embedded memory simulation test development platform, and the platform includes device systems
And test system, for simulating embedded memory, the test system is for simulating for the device systems
Extraneous PC, realizes the test to device systems；Methods described includes：
Error procedure is set, mistake is set, test system handle is erroneously inserted in error listing；
Error procedure is checked, error listing is traveled through, type, the numerical value of mistake is checked；
Triggering error procedure, returns an error to device systems.
5. as claimed in claim 4 to be erroneously inserted method, methods described is simulated in embedded memory
Performed in test development platform, the device systems include front end hardware analog module, file transport layer
FTL and the back-end hardware analog module including NAND analog modules, the front end hardware analog module
It is connected with test system, for the parsing to test command and the transmission of test command and data, FTL
It is connected with front end hardware analog module, the identification for analyzing test command and wrong data, and by data
Carry out address of cache management, data be stored in back-end hardware analog module, back-end hardware analog module with
FTL is connected, for the storage of data, it is characterised in that：
The triggering error procedure, returns an error to device systems back-end hardware analog module；
Identification error procedure, FTL identification wrong data, and report test system.
6. method is erroneously inserted as described in claim 4 or 5, methods described is in embedded memory
Performed in simulation test development platform, it is characterised in that the setting error procedure, including：
The test system is erroneously inserted in error listing by wrong interface handle.
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| CN201511032635.0A CN106933716A (en) | 2015-12-31 | 2015-12-31 | A kind of embedded memory simulation test development platform is erroneously inserted mechanism |
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| CN201511032635.0A CN106933716A (en) | 2015-12-31 | 2015-12-31 | A kind of embedded memory simulation test development platform is erroneously inserted mechanism |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109062808A (en) * | 2018-09-17 | 2018-12-21 | 浪潮电子信息产业股份有限公司 | SSD development performance testing method and device and related equipment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102789416A (en) * | 2012-06-13 | 2012-11-21 | 北京航空航天大学 | Memory fault injection method and simulator thereof for software built-in test (BIT) |
| US8707104B1 (en) * | 2011-09-06 | 2014-04-22 | Western Digital Technologies, Inc. | Systems and methods for error injection in data storage systems |
| CN105068909A (en) * | 2015-08-13 | 2015-11-18 | 北京京存技术有限公司 | Simulation test development platform for embedded storage |
-
2015
- 2015-12-31 CN CN201511032635.0A patent/CN106933716A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8707104B1 (en) * | 2011-09-06 | 2014-04-22 | Western Digital Technologies, Inc. | Systems and methods for error injection in data storage systems |
| CN102789416A (en) * | 2012-06-13 | 2012-11-21 | 北京航空航天大学 | Memory fault injection method and simulator thereof for software built-in test (BIT) |
| CN105068909A (en) * | 2015-08-13 | 2015-11-18 | 北京京存技术有限公司 | Simulation test development platform for embedded storage |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109062808A (en) * | 2018-09-17 | 2018-12-21 | 浪潮电子信息产业股份有限公司 | SSD development performance testing method and device and related equipment |
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