CN106932976A - Display device, array base palte and pixel cell - Google Patents
Display device, array base palte and pixel cell Download PDFInfo
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- CN106932976A CN106932976A CN201710312097.3A CN201710312097A CN106932976A CN 106932976 A CN106932976 A CN 106932976A CN 201710312097 A CN201710312097 A CN 201710312097A CN 106932976 A CN106932976 A CN 106932976A
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- 239000010408 film Substances 0.000 claims abstract description 51
- 239000010409 thin film Substances 0.000 claims abstract description 47
- 238000009826 distribution Methods 0.000 claims description 8
- 239000013078 crystal Substances 0.000 claims description 3
- 238000000926 separation method Methods 0.000 claims 2
- 238000000034 method Methods 0.000 description 29
- 238000010586 diagram Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 6
- 239000004973 liquid crystal related substance Substances 0.000 description 6
- 230000006978 adaptation Effects 0.000 description 2
- 239000003086 colorant Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000002834 transmittance Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
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- Crystallography & Structural Chemistry (AREA)
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- Power Engineering (AREA)
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Abstract
The disclosure provides a kind of display device, array base palte and pixel cell.The pixel cell includes multiple sub-pixs, and each sub-pix includes the first sub- sub-pix and the second sub- sub-pix；First sub- sub-pix includes the first pixel electrode and first film transistor, multiple first sub-electrodes that the first pixel electrode has the slit of multiple first width and separated by each slit；The control end of first film transistor is connected to the first grid line, first end and is connected to the first data wire, the second end and is connected to the first pixel electrode；Second sub- sub-pix includes the second pixel electrode and the second thin film transistor (TFT), multiple second sub-electrodes that the second pixel electrode has the slit of multiple second width and separated by each slit, and the second width is unequal with the first width；The control end of the second thin film transistor (TFT) is connected to the second grid line, first end and is connected to the second data wire, the second end and is connected to the second pixel electrode.
Description
Technical field
This disclosure relates to display technology field, in particular to a kind of display device, array base palte and pixel cell.
Background technology
At present, in Thin Film Transistor-LCD field, (fringing field is imitated for IPS (plane field-effect) displays and FFS
Should) two kinds of display because its have the advantages that wide viewing angle, high transmittance, quick response obtain be widely applied.It is right
For existing IPS displays and FFS displays, the array base palte of the two includes the pixel cell of multiple array distributions,
Each pixel cell includes multiple sub-pixs；The pixel electrode of these sub-pixs is typically using the slit that upper and lower pair of farmland is symmetrical
Electrode.Wherein, the electrode spacing of gap electrode has more obvious influence for display effect.For tool it, electrode spacing
Smaller, then the transmitance and driving voltage of liquid crystal molecule are higher, therefore brightness and power consumption are higher；Electrode spacing is larger, then liquid crystal
Molecule transmitance and driving voltage are relatively low, therefore brightness and power consumption are relatively low.
In the prior art, the structure and mode of operation of existing pixel cell are single, want to obtain high transmittance and high brightness,
To improve display effect, then can raise driving voltage, power consumption is also increased；To reduce power consumption, then can make transmitance and
Brightness is also decreased, and is only able to display the display effect of the picture of low GTG and low-light level；Thus cannot realize various levels of brightness and
Different power consumption demand, the scope of application is smaller, is unfavorable for that user is adjusted according to actual conditions.
It should be noted that information is only used for strengthening the reason of background of this disclosure disclosed in above-mentioned background section
Solution, therefore can include not constituting the information to prior art known to persons of ordinary skill in the art.
The content of the invention
The purpose of the disclosure is to provide a kind of display device, array base palte and pixel cell, and then at least in certain journey
Overcome on degree due to one or more problem caused by the limitation of correlation technique and defect.
According to an aspect of this disclosure, there is provided a kind of pixel cell, including multiple sub-pixs, each sub-pix is wrapped
Include the first sub- sub-pix and the second sub- sub-pix；Wherein：
The first sub- sub-pix includes：
First pixel electrode, first pixel electrode has the slit of multiple first width and by each slit point
Every multiple first sub-electrodes；
First film transistor, the control end of the first film transistor is connected to the first grid line, first end and is connected to
First data wire, the second end are connected to first pixel electrode；
The second sub- sub-pix includes：
Second pixel electrode, second pixel electrode has the slit of multiple second width and by each slit point
Every multiple second sub-electrodes, and second width is unequal with first width；
Second thin film transistor (TFT), the control end of second thin film transistor (TFT) is connected to the second grid line, first end and is connected to
Second data wire, the second end are connected to second pixel electrode.
In a kind of exemplary embodiment of the disclosure, the control end of the first film transistor and second film
The control end of transistor is connected to same grid line, and first grid line and second grid line are same grid line；
The first end of the first end of the first film transistor and second thin film transistor (TFT) is connected to different numbers
According to line, first data wire and second data wire are different data wires.
In a kind of exemplary embodiment of the disclosure, the control end of the first film transistor and second film
The control end of transistor is connected to different grid lines, and first grid line and second grid line are different grid lines；
The first end of the first end of the first film transistor and second thin film transistor (TFT) is connected to same data
Line, first data wire and second data wire are same data wire.
In a kind of exemplary embodiment of the disclosure, first pixel electrode includes first area and second area,
Be distributed with multiple first sub-electrodes in the first area and second area, and the first sub-electrode in the second area with
The first sub-electrode in the first area is arranged and non-intersect in the first angle, and first angle is less than 180 °；
Second pixel electrode includes the 3rd region and the 4th region, is distributed in the 3rd region and the 4th region
There is the second sub-electrode in the second sub-electrode in multiple second sub-electrodes, and the 4th region and the 3rd region in the
Two angles are arranged and non-intersect, and second angle is less than 180 °.
In a kind of exemplary embodiment of the disclosure, first width and width for first sub-electrode it
Be 7.35 μm；Second width and a width sum for second sub-electrode are 8.8 μm.
According to an aspect of this disclosure, there is provided a kind of array base palte, including：
Multiple is in the pixel cell described in the above-mentioned any one of array distribution；
Multiple grid lines, in the same pixel cell, the control end of each first film transistor and each described
The control end of two thin film transistor (TFT)s is connected to the same grid line；
Multiple data wires, are staggered with the multiple grid line, in the same pixel cell, each the first film
The first end of the first end of transistor and each second thin film transistor (TFT) is connected to the different data wires.
In a kind of exemplary embodiment of the disclosure, sub-pix described in the same a line in pixel cell described in same a line
In, each first sub- sub-pix is divided to two rows to set with each second sub- sub-pix, wherein,
Each first sub- sub-pix is respectively positioned on same a line, and each second sub- sub-pix is respectively positioned on another row；Or
Each first sub- sub-pix is with each second sub- sub-pix apart from one another by setting.
According to an aspect of this disclosure, there is provided a kind of array base palte, including：
Multiple is in the pixel cell described in the above-mentioned any one of array distribution；
Multiple grid lines, in the same pixel cell, the control end of each first film transistor and each described
The control end of two thin film transistor (TFT)s is connected to the different grid lines；
Multiple data wires, are staggered with the multiple grid line, in the same pixel cell, each the first film
The first end of transistor is connected to the same data wire with the first end of each second thin film transistor (TFT).
In a kind of exemplary embodiment of the disclosure, sub-pix described in the same a line in pixel cell described in same a line
In, each first sub- sub-pix is divided to two rows to set with each second sub- sub-pix, wherein,
Each first sub- sub-pix is respectively positioned on same a line, and each second sub- sub-pix is respectively positioned on another row；Or
Each first sub- sub-pix is with each second sub- sub-pix apart from one another by setting.
According to an aspect of this disclosure, there is provided a kind of display device, including the array base palte described in above-mentioned any one.
The display device of the disclosure, array base palte and pixel cell, in the same sub-pix of same pixel cell, first
First pixel electrode of sub- sub-pix has the slit of the first width, and the second pixel electrode of the second sub- sub-pix has second
The slit of width；So that same sub-pix can have two kinds of electrode spacings；Meanwhile, the first sub- sub-pix can be by the first film crystal
Management and control system, the second sub- sub-pix can be controlled by the second thin film transistor (TFT)；So that can be by controlling the first pixel electrode or the second picture
One of plain electrode works independently or the two works simultaneously, the transmitance and driving voltage of adjustable liquid crystal display molecule, to realize to bright
The regulation of degree and power consumption.Thus, it is easy to better meet user's request according to actual conditions.
It should be appreciated that the general description of the above and detailed description hereinafter are only exemplary and explanatory, not
The disclosure can be limited.
Brief description of the drawings
Accompanying drawing herein is merged in specification and constitutes the part of this specification, shows the implementation for meeting the disclosure
Example, and it is used to explain the principle of the disclosure together with specification.It should be evident that drawings in the following description are only the disclosure
Some embodiments, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
These accompanying drawings obtain other accompanying drawings.
Fig. 1 is the schematic diagram of the implementation method of disclosure pixel cell one.
Fig. 2 is the schematic diagram of the first sub- sub-pix in Fig. 1.
Fig. 3 is the schematic diagram of the second sub- sub-pix in Fig. 1.
Fig. 4 is the schematic diagram of another implementation method of disclosure pixel cell.
Fig. 5 is the schematic diagram of the first implementation method of disclosure array base palte.
Fig. 6 is the schematic diagram of second implementation method of disclosure array base palte.
Fig. 7 is the schematic diagram of the third implementation method of disclosure array base palte.
Fig. 8 is the 4th kind of schematic diagram of implementation method of disclosure array base palte.
Specific embodiment
Example embodiment is described more fully with referring now to accompanying drawing.However, example embodiment can be with various shapes
Formula is implemented, and is not understood as limited to example set forth herein；Conversely, thesing embodiments are provided so that the disclosure will more
Fully and completely, and by the design of example embodiment those skilled in the art is comprehensively conveyed to.Described feature, knot
Structure or characteristic can be combined in one or more implementation methods in any suitable manner.In the following description, there is provided perhaps
Many details are so as to provide fully understanding for implementation method of this disclosure.It will be appreciated, however, by one skilled in the art that can
Omit one or more in the specific detail to put into practice the technical scheme of the disclosure, or other groups can be used
Unit, device etc..In other cases, it is not shown in detail or describes known solution and the disclosure is caused to avoid that a presumptuous guest usurps the role of the host
Each side thicken.
Term " one ", " one ", " being somebody's turn to do " and " described " be used to represent exist one or more elements/part/etc.；With
Language " comprising " and " having " is used to represent the open meaning being included and refers to key element/composition portion except listing
Also there may be outside divide/waiting other key element/part/etc.；Term " first " and " second " etc. are only used as mark, no
It is the quantity limitation to its object；" multiple " represents two or more.
Pixel cell
Disclosure example embodiment provides a kind of pixel cell, can be used for thin-film transistor array base-plate, such as Fig. 1~figure
3, the pixel cell of present embodiment can include multiple sub-pixs 1, be a sub-pix 1 in Fig. 1 in dotted line frame；Each is sub-
Pixel 1 can be used to show different colors, for example, when a pixel cell includes three sub-pixs 1, three sub-pixs 1 can
It is respectively intended to show three kinds of colors of red, blue and green；The quantity not to the sub-pix 1 in same pixel cell makees special limit herein
Fixed, it can be three, four or more；Each sub-pix 1 may each comprise the first sub- sub-pix 11 and the second sub- sub-pix
12。
In the present embodiment, such as Fig. 2, the first sub- sub-pix 11 can include the first pixel electrode 111 and the first film
Transistor 112, wherein：
It is the first width d that first pixel electrode 111 can have multiple width1Slit 1111 and by 1111 points of each slit
Every multiple first sub-electrodes 1112；The quantity of the sub-electrode 1112 of slit 1111 and first is not particularly limited herein.Further
, first area and second area can be marked off on the first pixel electrode 111, it is distributed in the first area and second area
There are multiple first sub-electrodes 1112；The first sub-electrode 1112 in first area can be parallel to each other, the first son in second area
Electrode 1112 can be parallel to each other, and the first sub-electrode 1112 in first area can with the first sub-electrode 1112 in second area
Arranged and non-intersect with the first angle, so as to form double farmlands gap electrode；The angle of first angle can be less than 180 °, example
Such as 60 °, 90 ° or 120 °.
First width d1With the width d of any one the first sub-electrode 11122Sum is the electrode of the first pixel electrode 111
Space D1, i.e. d1+d2=D1；Electrode spacing D1Can be 7.35 μm, i.e. D1=7.35 μm；Wherein, the first width d1Can be 4.45 μ
M, the width d of the first sub-electrode 11122It can be 2.9 μm；But above-mentioned D1、d1And d2Value be merely illustrative, should not be construed as
Restriction to value, in the other embodiment of the disclosure, D1、d1And d2Value can also be other numerical value, if meet
d1+d2=D1, will not enumerate herein.
First film transistor 112 can have control end, first end and the second end, and its control end can be grid, can be used for
It is connected to the first grid line；Its first end can be source electrode, can be used to be connected to the first data wire；Its second end can be drain electrode, can use
In being connected to the first pixel electrode 111.
In the present embodiment, such as Fig. 3, the second sub- sub-pix 12 can include the second pixel electrode 121 and the second film
Transistor 122, wherein：
It is the second width d that second pixel electrode 121 can have multiple width1The slit 1211 of ＇ and by each slit
1211 multiple second sub-electrodes 1212 for separating, and the second width d1＇ can be with the first width d1It is unequal；Second sub-electrode 1212
Quantity be not particularly limited herein.Further, the 3rd region and the 4th region can be marked off on the second pixel electrode 121,
Multiple second sub-electrodes 1212 are distributed with 3rd region and the 4th region；The second sub-electrode 1212 in 3rd region
Can be parallel to each other, the second sub-electrode 1212 in the 4th region can be parallel to each other, and the second sub-electrode 1212 in the 3rd region
Can be arranged in the second angle and non-intersect with the second sub-electrode 1212 in the 4th region, so as to form double farmlands gap electrode；
The angle of second angle can be less than 180 °, such as 60 °, 90 ° or 120 ° etc..Second angle can be with the first above-mentioned angle
It is identical or different.
Second width d1The width d of ＇ and any one the second sub-electrode 12122＇ sums are the electricity of the second pixel electrode 121
Die opening D2, i.e. d1＇+d2＇=D2；Electrode spacing D2Can be 8.8 μm, i.e. D2=8.8 μm；Wherein, the second width d1＇ can be
5.9 μm, the width d of the second sub-electrode 12122＇ can be 2.9 μm；But above-mentioned D2、d1＇ and d2The value of ＇ is merely illustrative,
Should not be construed as the restriction to value；In the other embodiment of the disclosure, D2、d1＇ and d2The value of ＇ can also be other
Numerical value, as long as meeting d1＇+d2＇=D2, and D2It is not equal to D1, will not enumerate herein.
Second thin film transistor (TFT) 122 can have control end, first end and the second end, and its control end can be grid, can be used for
It is connected to the second grid line；Its first end can be source electrode, can be used to be connected to the second data wire；Its second end can be drain electrode, can use
In being connected to the second pixel electrode 121.
In the present embodiment, the control end of the control end of first film transistor 112 and the second thin film transistor (TFT) 122 is equal
Same grid line is may be connected to, the first above-mentioned grid line and the second grid line can be same grid line；So that can be by same grid line simultaneously
To the output signal of 112 and second thin film transistor (TFT) of first film transistor 122, for the array base palte with multiple pixel cells
For, telecommunications can be exported to multiple first film transistors 112 and multiple second thin film transistor (TFT)s 122 by same grid line simultaneously
Number.
The first end of the first end of first film transistor 112 and the second thin film transistor (TFT) 122 can be respectively connecting to difference
Data wire, the first above-mentioned data wire and the second data wire can be different data wires；In order to pass through different data wires
The control thin film transistor (TFT) 122 of first film transistor 112 and second, so that can be by different of data line traffic control first Asia pictures
One of sub- sub-pix 12 of element 11 and second works independently or while works.
In the other embodiment of the disclosure, the first end of first film transistor 112 and the second thin film transistor (TFT) 122
First end may be connected to same data wire, the first above-mentioned data wire and the second data wire can be same data wire；So that can
By same data wire simultaneously to the output signal of 112 and second thin film transistor (TFT) of first film transistor 122, for multiple
For the array base palte of pixel cell, can be by same data wire simultaneously to multiple first film transistors 112 and multiple second
The output signal of thin film transistor (TFT) 122.
The control end of the control end of first film transistor 112 and the second thin film transistor (TFT) 122 can also be respectively connecting to not
Same grid line, above-mentioned the first grid line and the second grid line is different grid lines；Grid line control first in order to pass through different is thin
The thin film transistor (TFT) 122 of film transistor 112 and second, so that the first sub- sub-pix 11 and the second son can be controlled by different grid lines
One of sub-pix 12 works independently or while works.
In the present embodiment, for the first sub- sub-pix 11 in sub-pix 1 and the relative position of the second sub- sub-pix 12
Put the relative position relation and the and of the second thin film transistor (TFT) 122 of relation, the sub- sub-pix 11 of first film transistor 112 and first
The relative position relation of the second sub- sub-pix 12 is not particularly limited, and can change above-mentioned relative position according to actual conditions and close
System.For example, in same pixel cell, such as Fig. 1, each first sub- sub-pix 11 can be located at same a line, each second son
Sub-pix 12 can be located at another row；Or, such as Fig. 4, the first 11 points of sub- sub-pix is set for two rows, and adjacent two first sons Asia picture
A second sub- sub-pix 12, i.e., the first sub- sub-pix 11 and the interval setting of the second sub- sub-pix 12 are provided between element 11.
The operation principle of the pixel cell of disclosure example embodiment：
When the only first sub- sub-pix 11 works, due to the electrode spacing D of the first sub- sub-pix 111It is smaller, liquid crystal it is saturating
Cross that rate is higher, power consumption now is medium, and the brightness of display is medium；When the only second sub- sub-pix 12 works, due to the second son
The electrode spacing D of sub-pix 122Larger, the transmitance of liquid crystal is relatively low, and power consumption now is smaller, and brightness is relatively low；When the first son Asia picture
The sub- sub-pix 12 of element 11 and second works simultaneously when, the overall transmitance highest of liquid crystal, power consumption highest now, the brightness of display
Highest.
Based on the operation principle of above-mentioned pixel cell, the pixel cell of disclosure example embodiment, be easy to user according to
Actual conditions select brightness and power consumption, expand the scope of application.
The first implementation method of disclosure array base palte
Disclosure example embodiment provides a kind of array base palte, and such as Fig. 5, the array base palte of present embodiment can include
Grid line 2, data wire 3 and pixel cell.
In the present embodiment, the composition of pixel cell refers to the pixel list in the implementation method of above-mentioned pixel cell
Unit；The quantity of the pixel cell can be multiple, and multiple pixel cells can have multirow in array distribution, i.e. array base palte
With multiple row pixel cell, the sub-pix 1 in the pixel cell can also be arranged in rows and columns.For example, in same a line
In same a line sub-pix 1 in pixel cell, such as Fig. 5, each first sub- sub-pix 11 and each second sub- sub-pix 12 can divide
For two rows are set, wherein, each first sub- sub-pix 11 can be respectively positioned on same a line, and each second sub- sub-pix 12 can be respectively positioned on separately
A line.
The quantity of grid line 2 can be multiple, and multiple grid lines 2 parallel can be distributed；In same pixel cell, each first
The control end of the control end of thin film transistor (TFT) 112 and each the second thin film transistor (TFT) 122 is connected to same grid line 2, i.e., same
The thin film transistor (TFT) 122 of first film transistor 112 and second in pixel cell can be separated by a grid line 2.
The quantity of data wire 3 can be multiple, and multiple data wires 3 can be staggered with multiple grid lines 2, each pixel list
Unit can respectively be located at multiple data wires 3 and interlock in area defined with multiple grid lines 2；In same pixel cell, each
The first end of one thin film transistor (TFT) 112 and the first end of each the second thin film transistor (TFT) 122 may be connected to different data wires 3.
Second implementation method of disclosure array base palte
Disclosure example embodiment provides a kind of array base palte, and such as Fig. 6, the array base palte of present embodiment can include
Grid line 2, data wire 3 and pixel cell.
In the present embodiment, the composition of pixel cell refers to the pixel list in the implementation method of above-mentioned pixel cell
Unit；Such as Fig. 6, the set-up mode of grid line 2 and data wire 3 refers to phase in the first implementation method of above-mentioned array base palte inside the Pass
Hold, this is not being repeated；Separately, each first sub- sub-pix 11 can be divided into the setting of two rows with each second sub- sub-pix 12, and
The first sub- sub-pix 11 and the second sub- sub-pix 12 are distributed with any row, often go in the first sub- sub-pix 11 and the second son
Sub-pix 12 is apart from one another by setting.
The first above-mentioned implementation method and second array base palte of implementation method, operationally, can be same by grid line 2
When to the sending signal of 112 and second thin film transistor (TFT) of first film transistor 122 for being connected to the grid line 2；Then by difference
Data wire 3 respectively to the sending signal of 112 and second thin film transistor (TFT) of first film transistor 122 so that pass through the first film
One of 112 and second thin film transistor (TFT) of transistor 122 control the first sub- sub-pixel unit 11 and the second sub- sub-pixel unit 12 are single
Solely work or work simultaneously；According to the operation principle of above-mentioned pixel cell, it is capable of achieving that there is different brightness and the display of power consumption
Effect, is easy to user to be carried out selecting brightness and power consumption according to actual conditions, expands the scope of application.
The third implementation method of disclosure array base palte
Disclosure example embodiment provides a kind of array base palte, and such as Fig. 7, the array base palte of present embodiment can include
Grid line 2, data wire 3 and pixel cell.
In the present embodiment, the composition of pixel cell refers to the pixel list in the implementation method of above-mentioned pixel cell
Unit；The quantity of the pixel cell can be multiple, and multiple pixel cells can have multirow in array distribution, i.e. array base palte
With multiple row pixel cell, the sub-pix 1 in the pixel cell can also be arranged in rows and columns.For example, in same a line
In same a line sub-pix 1 in pixel cell, such as Fig. 7, each first sub- sub-pix 11 and each second sub- sub-pix 12 can divide
For two rows are set, wherein, each first sub- sub-pix 11 can be respectively positioned on same a line, and each second sub- sub-pix 12 can be respectively positioned on separately
A line；The quantity of grid line 2 can be multiple, and multiple grid lines 2 parallel can be distributed；In same pixel cell, each is first thin
The control end of the control end of film transistor 112 and each the second thin film transistor (TFT) 122 may be connected to different grid lines 2.
The quantity of data wire 3 can be multiple, and multiple data wires 3 can be staggered with multiple grid lines 2, each pixel list
Unit can respectively be located at multiple data wires 3 and interlock in area defined with multiple grid lines 2；In the same pixel cell, respectively
The first end of individual first film transistor 112 may be connected to same data wire with the first end of each the second thin film transistor (TFT) 122
3；The thin film transistor (TFT) 122 of first film transistor 112 and second in i.e. same pixel cell can be separated by a data wire 3.
4th kind of implementation method of disclosure array base palte
Disclosure example embodiment provides a kind of array base palte, and such as Fig. 8, the array base palte of present embodiment can include
Grid line 2, data wire 3 and pixel cell.
In the present embodiment, the composition of pixel cell refers to the pixel list in the implementation method of above-mentioned pixel cell
Unit；Such as Fig. 8, the set-up mode of grid line 2 and data wire 3 refers to phase in the third implementation method of above-mentioned array base palte inside the Pass
Hold, this is not being repeated；Separately, such as Fig. 8, each first sub- sub-pix 11 can be divided into two rows and set with each second sub- sub-pix 12
Put, and the first sub- sub-pix 11 and the second sub- sub-pix 12 be distributed with any row, often go in the He of the first sub- sub-pix 11
Second sub- sub-pix 12 is apart from one another by setting.
The third above-mentioned implementation method and the 4th kind of array base palte of implementation method, operationally, can be by data wire 3
Simultaneously to the sending signal of 112 and second thin film transistor (TFT) of first film transistor 122 for being connected to the data wire 3；And by not
Same grid line 2 is respectively to the sending signal of 112 and second thin film transistor (TFT) of first film transistor 122, so as to pass through the first film
One of 112 and second thin film transistor (TFT) of transistor 122 control the first sub- sub-pixel unit 11 and the second sub- sub-pixel unit 12 are single
Solely work or work simultaneously；According to the operation principle of above-mentioned pixel cell, it is capable of achieving that there is different brightness and the display of power consumption
Effect, is easy to user to be carried out selecting brightness and power consumption according to actual conditions, expands the scope of application.
It should be noted that the first implementation method for above-mentioned array base palte, second implementation method, the third
For implementation method and the 4th kind of implementation method, the distribution mode of the first sub- sub-pix 11 and the second sub- sub-pix 12 is not limited to
Mode listed above, it can also use other manner, will not enumerate herein.
Disclosure example embodiment provides a kind of display device, and the display device of present embodiment can include above-mentioned
Array base palte described in one implementation method, and corresponding technical problem can be solved, corresponding technique effect is reached, no longer go to live in the household of one's in-laws on getting married herein
State.
Those skilled in the art will readily occur to its of the disclosure after considering specification and putting into practice invention disclosed herein
Its embodiment.The application is intended to any modification, purposes or the adaptations of the disclosure, these modifications, purposes or
Person's adaptations follow the general principle of the disclosure and including the undocumented common knowledge in the art of the disclosure
Or conventional techniques.Description and embodiments are considered only as exemplary, and the true scope of the disclosure and spirit are by appended
Claim is pointed out.
Claims (10)
1. a kind of pixel cell, including multiple sub-pixs, it is characterised in that each sub-pix include the first sub- sub-pix with
And the second sub- sub-pix；Wherein：
The first sub- sub-pix includes：
First pixel electrode, first pixel electrode has the slit of multiple first width and by each slit separation
Multiple first sub-electrodes；
First film transistor, the control end of the first film transistor is connected to the first grid line, first end and is connected to first
Data wire, the second end are connected to first pixel electrode；
The second sub- sub-pix includes：
Second pixel electrode, second pixel electrode has the slit of multiple second width and by each slit separation
Multiple second sub-electrodes, and second width is unequal with first width；
Second thin film transistor (TFT), the control end of second thin film transistor (TFT) is connected to the second grid line, first end and is connected to second
Data wire, the second end are connected to second pixel electrode.
2. pixel cell according to claim 1, it is characterised in that the control end of the first film transistor and described
The control end of the second thin film transistor (TFT) is connected to same grid line, and first grid line and second grid line are same grid line；
The first end of the first end of the first film transistor and second thin film transistor (TFT) is connected to different data wires,
First data wire and second data wire are different data wires.
3. pixel cell according to claim 1, it is characterised in that the control end of the first film transistor and described
The control end of the second thin film transistor (TFT) is connected to different grid lines, and first grid line and second grid line are different grid
Line；
The first end of the first end of the first film transistor and second thin film transistor (TFT) is connected to same data wire, institute
It is same data wire to state the first data wire and second data wire.
4. the pixel cell according to any one of claims 1 to 3, it is characterised in that first pixel electrode includes the
One region and second area, are distributed with multiple first sub-electrodes, and secondth area in the first area and second area
The first sub-electrode in domain is arranged and non-intersect with the first sub-electrode in the first area in the first angle, first folder
Angle is less than 180 °；
Second pixel electrode includes the 3rd region and the 4th region, is distributed with the 3rd region and the 4th region many
The second sub-electrode in individual second sub-electrode, and the 4th region is pressed from both sides with the second sub-electrode in the 3rd region in second
Angle is arranged and non-intersect, and second angle is less than 180 °.
5. the pixel cell according to any one of claims 1 to 3, it is characterised in that described in first width and
The width sum of the first sub-electrode is 7.35 μm；Second width and a width sum for second sub-electrode are 8.8 μ
m。
6. a kind of array base palte, it is characterised in that including：
Multiple is in the pixel cell described in any one of Claims 1 to 5 of array distribution；
Multiple grid lines, in the same pixel cell, the control end of each first film transistor and each described second thin
The control end of film transistor is connected to the same grid line；
Multiple data wires, are staggered with the multiple grid line, in the same pixel cell, each the first film crystal
The first end of the first end of pipe and each second thin film transistor (TFT) is connected to the different data wires.
7. array base palte according to claim 6, it is characterised in that described in the same a line in pixel cell described in same a line
In sub-pix, each first sub- sub-pix is divided to two rows to set with each second sub- sub-pix, wherein,
Each first sub- sub-pix is respectively positioned on same a line, and each second sub- sub-pix is respectively positioned on another row；Or
Each first sub- sub-pix is with each second sub- sub-pix apart from one another by setting.
8. a kind of array base palte, it is characterised in that including：
Multiple is in the pixel cell described in any one of Claims 1 to 5 of array distribution；
Multiple grid lines, in the same pixel cell, the control end of each first film transistor and each described second thin
The control end of film transistor is connected to the different grid lines；
Multiple data wires, are staggered with the multiple grid line, in the same pixel cell, each the first film crystal
The first end of pipe is connected to the same data wire with the first end of each second thin film transistor (TFT).
9. array base palte according to claim 8, it is characterised in that described in the same a line in pixel cell described in same a line
In sub-pix, each first sub- sub-pix is divided to two rows to set with each second sub- sub-pix, wherein,
Each first sub- sub-pix is respectively positioned on same a line, and each second sub- sub-pix is respectively positioned on another row；Or
Each first sub- sub-pix is with each second sub- sub-pix apart from one another by setting.
10. a kind of display device, it is characterised in that including：
Array base palte described in claim 6 or claim 7；Or
Array base palte described in claim 8 or claim 9.
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