CN106911623A - A kind of 16QAM modulators and modulator approach - Google Patents
A kind of 16QAM modulators and modulator approach Download PDFInfo
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- CN106911623A CN106911623A CN201710059296.8A CN201710059296A CN106911623A CN 106911623 A CN106911623 A CN 106911623A CN 201710059296 A CN201710059296 A CN 201710059296A CN 106911623 A CN106911623 A CN 106911623A
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- signal
- 16qam
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- quaternary psk
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
- H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
- H04L27/36—Modulator circuits; Transmitter circuits
Abstract
The invention discloses a kind of 16QAM modulators, including a logical calculation device, preceding four groups of bits to receiving carry out logical operation, generate the output of the first and second logics, first quaternary PSK qpsk modulator receives first and second groups of bits of data and generates first quaternary PSK signal, second quarter phase-shift-keying modulator receives the first and second logics and exports and generate second quaternary PSK signal, one combiner merges first and second quaternary PSK signal, generates a 16QAM signal.A high-order modulator is obtained using multiple low level modulators, it is not necessary to develop new high-order modulator integrated circuit, saved substantial amounts of development time and expense.
Description
Technical field
The present invention relates to communicate, and especially, it is related to a kind of method and apparatus of modulated signal.
Background technology
Digital communication is based on various different, but correlation, form of digital modulation, such as phase-shift keying (PSK) (PSK), binary system phase
Move keying (BPSK), quaternary PSK (QPSK or 4-PSK), and quadrature amplitude modulation (QAM).
Be described for reference picture 1 by binary phase shift keying.As illustrated, the amplitude of reference carrier is constant, and
In order to transmit one 0 or one 1, its phase must carry out " keying " or switching between 0 ° and 180 °.One receiver root again
Determine transmission according to the phase of the carrier wave for receiving is 0 or 1, and generates original data stream.By this simple mode, one
The information of individual bit is transmitted with a kind of state or symbol, so that the phase of carrier wave carries out keying according to message transmission rate.
Fig. 1 gives the planisphere of binary phase shift keying.As illustrated, the planisphere of binary phase shift keying is by I-Q coordinates
Two points composition, wherein I represents locking phase (for example, phase reference), and Q represents quadrature phase (for example, 90 ° of asynchronous phases
Position).Out of phase, dephasing incongruent with phase, out-of-phase is out of phase, on the binary phase shift keying planisphere of out-phase
Two representation signals in the position of " Time To Event ".Time To Event refers to the time of receiver solution read signal.
Signal can only at a time be in a position, but planisphere may be considered that it is all suitable so as to show with continuity
State.Planisphere 1 does not show the transient process between two states；Simultaneously, it should be noted that when the transition needs certain limited
Between.But for clarity, this transient process does not show, otherwise connecting two transition wires of state point will make figure miscellaneous
It is disorderly unclear.
One modulator of exploitation generally requires one application specific integrated circuit (ASIC) of manufacture.This development may be non-
Often costly and time-consuming.
The content of the invention
The purpose of the present invention is to disclose a kind of 16QAM modulators, and a high-order modulation is obtained using multiple low level modulators
Device, it is not necessary to develop new high-order modulator integrated circuit, saved substantial amounts of development time and expense.
To achieve the above object, the technical solution adopted by the present invention is：
On every piece of chip of application specific integrated circuit (ASIC) it is integrated multiple (such as 8) quarter phase-shift-keying modulator is
It has been applied through that can realize and in telecommunications industry.Feature of the invention, this existing science and technology can be used to generate
Application specific integrated circuit with 16QAM modulator of the 16QAM signals without exploitation high cost.It should be understood that of the invention should
With being not limited to this concrete case；And other more high-order modulators can be by several (such as two or more) low levels
Modulator is obtained.
In one embodiment of the invention, a digital signal processor (DSP) be used to compare four received
Special data carry out logical operation to be modulated.Logical operation produces two input signals, there is provided to special integrated mounted in one
Second in two quarter phase-shift-keying modulators on circuit.The first two bit of the data for receiving is used as input signal
It is supplied to first in the two quarter phase-shift-keying modulators.The two quaternary PSK signals merge generation
16QAM signals.
Herein, the first quaternary PSK signal for being generated by the first two bit data is for 16QAM signals are provided
One is oriented to instruction.That is, a constellation point for quaternary PSK signal of generation is in required 16QAM signals
Same quadrant.Second quaternary PSK signal carries out intense adjustment to first quaternary PSK signal.That is,
When merging with first quaternary PSK signal, second quaternary PSK signal believes first quaternary PSK
Number constellation point be displaced in four 16QAM constellation points the position of that constellation point for being in same quadrant.
Digital signal processor receive first of data and the 3rd bit are carried out with or computing, generation second
First input signal of individual quarter phase-shift-keying modulator, the second of data and the 4th bit to receiving are carried out together
Or computing generates second the second of quarter phase-shift-keying modulator input signal.In theory, third and fourth bit with
First and second bits are combined it can be pointed out that the direction of this displacement.
Brief description of the drawings
The planisphere of Fig. 1 displays reference carrier, keyed carrier and two-phase PSK；
Fig. 2 shows the planisphere of quaternary PSK；
Fig. 3 shows the planisphere of 16 quadrature amplitude modulations；
Fig. 4 shows that 16 quadrature amplitude modulators are based on a case study on implementation of the invention；
Fig. 5 is displayed in superposition quaternary PSK planisphere on 16QAM planispheres.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and detailed description.
Embodiment 1
Fig. 2 shows the planisphere of quaternary PSK.As illustrated, there is four kinds of differences on quaternary PSK planisphere
State, respectively 45 °, 135 °, 225 ° and 315 ° of corresponding phase.Further shown in figure, one representative of each state correspondence
Two symbols of bit.Because constituting a symbol needs two bits, the transmission rate of the symbol is Bit Transmission Rate
Half.Therefore, it is the half of binary phase shift keying in the bandwidth needed for quaternary PSK under same bits speed.
Fig. 3 shows the planisphere of 16QAM (quadrature amplitude modulation).Except being modulated to phase, the amplitude of signal
It is modulated, so as to produce four different constellation points being located at respectively in four quadrants of I-Q coordinate systems.As illustrated,
Four bits of a symbology in 16QAM.
Fig. 4 shows a 16 quadrature amplitude modulators case study on implementation of the invention.As illustrated, passing through Digital Signal Processing
The receiving sequence numerical data of deserializer 110 in device 100, is assembled four data bits b0, b1, b2 and b3.This
The Parallel Data of four bits is supplied to a logic unit 120.The logic unit is to first and the 3rd bit b0 and b2
Carry out same or computing and generate first logic output 12, then same or computing generation is carried out to second and the 4th bit b1 and b3
Second logic exports Q2.Following table 1 is a logical table, and show first to the 4th bit b0, b1, b2 and b3 can
Corresponding first and second 12 and Q2 of logic output can be combined.
Table 1
First and second bit b0 and b1 and first and second logic output are supplied to an application specific integrated circuit
(ASIC) 200, the application specific integrated circuit includes multiple (such as 8) quarter phase-shift-keying modulators.More specifically, the first He
Second bit b0 and b1 is supplied to first quarter phase-shift-keying modulator 210 respectively as I1 and Q1 input signals.Here
I refer to first same-phase input signal of quarter phase-shift-keying modulator 210, Q represents first quaternary PSK
The quadrature-phase input signals of modulator 210.First quarter phase-shift-keying modulator 210 according to receive input in a known way
First quaternary PSK signal of generation.In addition, in the implementation case, quarter phase-shift-keying modulator 210 is also by
The mode known is by channelization codes CchQuaternary PSK signal is applied to scrambler S^ to generate first quaternary PSK
Signal (I1+jQ1)CchSdt。
The first and second logics that second quarter phase-shift-keying modulator 220 in application specific integrated circuit will be received are defeated
Go out to be used separately as I and Q input signals.Second quarter phase-shift-keying modulator 220 is based on these input signals and passes through known formula
Formula generates second quaternary PSK signal.As shown in figure 4, first and second He of quarter phase-shift-keying modulator 210
220 setting caused when identical input signal is received, four phase phase shifts of first quarter phase-shift-keying modulator 210 generation
The amplitude of keying signal is second twice of quarter phase-shift-keying modulator 220.In the present embodiment, second four phase phase shift
Keying modulator 220 uses the channelization codes C same with first quarter phase-shift-keying modulator 210chApplied with scrambler S^
In quaternary PSK signal generating second quaternary PSK signal (I2+jQ2)CchSdt。
One adder 300, can be located internally or externally with respect to application specific integrated circuit 200, receive first and second four phase shifts
Phase keying signal, they is merged and obtains 16QAM signals.
Fig. 5 is displayed in superposition quaternary PSK planisphere on 16QAM planispheres.As illustrated, quaternary PSK star
Seat point is located at the centre of the 16QAM constellation points in the quadrant in each quadrant.During 16QAM signals are generated, the
One quarter phase-shift-keying modulator 210 is by first and second computings of bit b0 and b1, first QPSK of generation
Signal can show the apparent position of 16QAM signals.That is, first output letter of quarter phase-shift-keying modulator 210
Number, can show that quaternary PSK constellation point is four centers of possible 16QAM constellation points；So as to indicate that 16QAM believes
Number or its constellation point quadrant.
Third and fourth bit b3 and b4 provide the quaternary PSK provided from first and second bits b0 and b1
Constellation point is also not enough to comprising the institute for providing the direction of displacement to the displacement of in four 16QAM constellation points in same quadrant
There is information.As shown in Figures 3 and 5, for third and fourth bit b3 and b4,16QAM constellation point are on I axles and Q axial symmetry
's.Then, the logic unit 120 of digital signal processor 100 by logical operation by third and fourth bit b3 and b4 with
Directional information is added and obtains second I and Q input signal of quarter phase-shift-keying modulator 220.In this way, second
The second quaternary PSK signal of generation of quarter phase-shift-keying modulator 220 carries out micro- to first quaternary PSK signal
Adjust.That is, second quaternary PSK signal can show from first constellation point of quaternary PSK signal to
The displacement of one in four 16QAM constellation points.
Following table 2 is a logical table, gives the I values and Q values of the 16QAM constellation points shown in Fig. 5, these I values
Four bit b0, b1, b2 and b3 all of probable values when corresponding to amplitude B=0.4472 with Q values operation result.
Table 2
The invention provides a 16QAM modulator, the relatively existing quaternary PSK circuit of the modulator may have
Have great advantage.For example, on every piece of chip of application specific integrated circuit (ASIC) it is integrated multiple (such as 8) quaternary PSKs
Modulator can have been realized and has been applied in telecommunications industry.- feature of the invention, this existing science and technology can be with
For generating 16QAM signals without developing the application specific integrated circuit with 16QAM modulators of high cost.
Description of the invention mode shows that the description can be changed at many aspects.For example, the string in case study on implementation
And converter and/or logic unit can replace digital signal processor using hardware circuit, firmware etc..In addition, four phase phase shifts
Keying modulator can be only fitted on independent application specific integrated circuit or use not necessarily with identical application specific integrated circuit
It is first-class in digital signal processor.
Further, due to having been presented for developing a high position using two low level quarter phase-shift-keying modulators
The case of 16QAM modulators, can be clear from further by using multiple (such as 2 or more) quaternary PSKs or its
The modulator development of his more low level other more high-order modulators.These changes are not to be regarded as running counter to the present invention, and own
This kind of change all answer in scope incorporated herein.
Although being illustrated to embodiments of the present invention in specification, these implementation methods are intended only as prompting,
Should not limit protection scope of the present invention.It is equal that various omission, substitution, and alteration are carried out without departing from the spirit and scope of the present invention
Should be comprising within the scope of the present invention.
Claims (8)
1. a kind of 16QAM modulators, it is characterised in that：One logical calculation device pass through the data to receiving first to
Four bits carry out logical operation and generate first and second logic outputs；
First quaternary PSK qpsk modulator receives first and second groups of bits of data and generates first four phase shift
Phase keying signal；
Second quarter phase-shift-keying modulator receives the first and second logics and exports and generate second quaternary PSK letter
Number；And
One combiner merges first and second quaternary PSK signal, generates a 16QAM signal.
2. 16QAM modulators according to claim 1, it is characterised in that：To receive the first of data and the 3rd
Bit carries out exclusive NOR-operation, to generate the output of first logic, and to receive the second of data and the 4th
Bit carries out same or computing and generates second logic output.
3. 16QAM modulators according to claim 2, it is characterised in that：First and second quaternary PSK modulation
The setting of device caused when identical input signal is received, the quaternary PSK of first quarter phase-shift-keying modulator generation
Signal amplitude is second twice of quarter phase-shift-keying modulator.
4. 16QAM modulators according to claim 1, it is characterised in that：Logical calculation device is at a data signal
Reason device.
5. 16QAM modulators according to claim 1, it is characterised in that：First and second quaternary PSK modulation
Device is arranged on an application-specific integrated circuit ASIC.
6. 16QAM modulators according to claim 1, it is characterised in that：First and second quaternary PSK modulation
Device uses identical channelization codes and scrambler when first and second quaternary PSK signals are generated.
7. a kind of 16QAM modulator approaches, including：Logical operation is carried out by first to the 4th bit of the data to receiving
First and second logic outputs of generation；First and second bits based on the data for receiving generate first four phase phase shift
Keying signal；Based on the first and second logics output second quaternary PSK signal of generation；By first and second four
Phase phase-shift keyed signal merges, and generates a 16QAM signal.
8. 16QAM modulator approaches according to claim 7, it is characterised in that：Described calculation step includes：To receiving
First and the 3rd bit of data carry out exclusive NOR-operation, to generate the first logic output signal；And docking
The second of the data for receiving and the 4th bit carry out exclusive NOR-operation, to generate the second logic output signal.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7078981B2 (en) * | 2004-07-27 | 2006-07-18 | Lucent Technologies Inc. | 16 QAM modulator and method of 16 QAM modulation |
| CN104579344A (en) * | 2013-10-18 | 2015-04-29 | 亚德诺半导体集团 | Multi-stage noise shaping analog-to-digital converter |
-
2017
- 2017-01-24 CN CN201710059296.8A patent/CN106911623A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7078981B2 (en) * | 2004-07-27 | 2006-07-18 | Lucent Technologies Inc. | 16 QAM modulator and method of 16 QAM modulation |
| CN104579344A (en) * | 2013-10-18 | 2015-04-29 | 亚德诺半导体集团 | Multi-stage noise shaping analog-to-digital converter |
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Effective date of registration: 20200826 Address after: No.2101, building 5, xiangxieyuan, coastal Lishui Jiayuan, No.8 Daojiao Road, Daojiao Town, Dongguan City, Guangdong Province Applicant after: Zhong Xin Address before: 436070 Optics Valley joint development science and Technology City, Gedian Development Zone, Huarong District, Hubei, Ezhou C3-6 Applicant before: WISEHEALTH, Ltd. |
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