CN106899401B - Clock synchronization method of ten-gigabit synchronous Ethernet - Google Patents
Clock synchronization method of ten-gigabit synchronous Ethernet Download PDFInfo
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- CN106899401B CN106899401B CN201710072466.6A CN201710072466A CN106899401B CN 106899401 B CN106899401 B CN 106899401B CN 201710072466 A CN201710072466 A CN 201710072466A CN 106899401 B CN106899401 B CN 106899401B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0617—Systems characterised by the synchronising information used the synchronising signal being characterised by the frequency or phase
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0641—Change of the master or reference, e.g. take-over or failure of the master
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Abstract
The invention provides a clock synchronization method of a trillion synchronous Ethernet, which comprises an upstream unit and a downstream unit and is characterized in that: the upstream unit and the downstream unit respectively comprise an FPGA, a gigabit Ethernet PHY and a PLL frequency synthesizer, and are connected through network cables; 2-level PLL is integrated in the PLL frequency synthesizer, the 1 st-level PLL is used for clock jitter removal, and the 2 nd-level PLL is used for frequency multiplication; when the PLL frequency synthesizer has no reference clock input, clock output is kept; the gigabit Ethernet PHY supports synchronous Ethernet and recovers a clock from a network cable; the gigabit Ethernet PHY and FPGA support a 10G BASE-KR interface. The technical scheme of the invention can realize the reliable transmission of the gigabit Ethernet, is suitable for the current infrastructure construction of China, has the significance of popularization and use and has important market value.
Description
Technical Field
The invention relates to a clock synchronization method of a gigabit synchronous Ethernet, which is mainly used in the field of communication.
Background
Under the condition of high-bandwidth data transmission, the gigabit Ethernet can not meet the requirement, and the gigabit Ethernet is required to be used for transmission. Generally, a gigabit ethernet transmits 10Gbps of data through an optical fiber, which is long in transmission distance but high in cost. For short distance transmission within 100m, the super 6 type network cable (CAT 6 e) transmission is used, and the cost can be reduced remarkably. Because the requirement for signal quality is high when the gigabit ethernet is transmitted through the network cable, the clock is an important factor influencing the signal. The traditional Ethernet transmission is asynchronous transmission, the transmission link clock is asynchronous, the signal quality is not good enough, and error codes are easy to occur.
Disclosure of Invention
The invention aims to provide a clock synchronization method of a gigabit synchronous Ethernet, which realizes the reliable transmission of the gigabit Ethernet.
The invention provides a clock synchronization method of a gigabit synchronous Ethernet, wherein the gigabit synchronous Ethernet comprises an upstream unit and a downstream unit, the upstream unit and the downstream unit respectively comprise an FPGA, a gigabit Ethernet PHY and a PLL frequency synthesizer, and the upstream unit and the downstream unit are connected through a network cable;
2-level PLL is integrated in the PLL frequency synthesizer, the 1 st-level PLL is used for clock jitter removal, and the 2 nd-level PLL is used for frequency multiplication;
when the PLL frequency synthesizer has no reference clock input, clock output is kept; the gigabit Ethernet PHY supports synchronous Ethernet and recovers a clock from a network cable; the gigabit Ethernet PHY and FPGA support a 10G BASE-KR interface.
The gigabit ethernet PHY of the upstream unit is set to master, and the gigabit ethernet PHY of the downstream unit is set to slave; after the upstream unit and the downstream unit are connected through a network cable, the gigabit Ethernet PHY of the downstream unit recovers a clock of the upstream unit, the recovered clock is used as a reference clock source of a PLL frequency synthesizer, and the PLL frequency synthesizer provides a reference clock input pin of the PHY and a 10G BASE-KR interface of the FPGA as a reference clock; when the upstream unit and the downstream unit are disconnected, the PLL frequency synthesizer keeps the clock output and provides a reference clock for a reference clock input pin of the PHY and a 10G BASE-KR interface of the FPGA.
In the upstream unit, a PLL frequency synthesizer takes 25MHz TCXO as reference, frequency is multiplied to 156.25MHz to output two paths of reference clocks, one path of clock is used as reference for a 10G BASE-KR interface of the FPGA, and the other path of clock is used as reference for a ten-gigabit Ethernet PHY; wherein, the 25MHz TCXO clock is directly sent to the 2 nd level PLL of the PLL frequency synthesizer for frequency multiplication, the 1 st level PLL does not use; after the FPGA finishes digital signal processing, data are transmitted and received between the FPGA and the gigabit Ethernet PHY through a 10GBASE-KR interface, the gigabit Ethernet PHY transmits and receives data on a network cable through a 10G BASE-T interface, meanwhile, the PHY of an upstream unit is set as a master, and the PHY transmits and receives data on the network cable through a reference clock 156.25MHz of the PHY.
In the downstream unit, the gigabit ethernet PHY is set to slave, and receives and transmits data through a network cable; the gigabit Ethernet PHY recovers a clock from the network cable and outputs a SYNCEOUT clock of 25 MHz; the SYNCEOUT clock is used as a reference for a PLL frequency synthesizer, is subjected to debounce by a level 1 PLL, is subjected to frequency multiplication by a level 2 PLL, and outputs two paths of 156.25MHz clocks, one path of clock is used as a reference clock for a gigabit Ethernet PHY, and the other path of clock is used as a reference clock for a 10G BASE-KR interface of the FPGA.
The invention has the beneficial effects that: the invention relates to a clock synchronization method of a gigabit synchronous Ethernet, which synchronizes a transmission link clock by using the synchronous Ethernet, introduces a clock jitter removal function, and improves the clock quality, thereby improving the signal quality and ensuring that the gigabit Ethernet is more reliable in transmission through a network cable. The technical scheme of the invention can realize the reliable transmission of the gigabit Ethernet, is suitable for the current infrastructure construction of China, has the significance of popularization and use and has important market value.
Drawings
FIG. 1 is a diagram of a gigabit Ethernet system connected by a network cable according to an embodiment of the present invention;
FIG. 2 is a diagram of a clock delivery scheme for an upstream unit according to an embodiment of the present invention;
FIG. 3 is a diagram of a clock delivery scheme for downstream units of an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the accompanying drawings and detailed description, in order to facilitate the understanding and implementation of the invention by those skilled in the art.
In the embodiment, the upstream unit and the downstream unit are connected through a category 6 super network (CAT 6 e), and both the upstream unit and the downstream unit are provided with an FPGA (field programmable gate array) and a gigabit ethernet PHY (physical layer interface chip), and a PLL (phase locked loop) frequency synthesizer. The FPGA is used for digital signal processing; the Ethernet PHY is used as a gigabit Ethernet transceiving interface and supports the synchronous Ethernet function; the PLL frequency synthesizer provides a reference clock for the FPGA and the PHY, a 2-level PLL is integrated in the PLL, the 1 st-level PLL can remove jitter of the clock, and the 2 nd-level PLL can complete clock frequency multiplication. The FPGA and the Ethernet PHY are connected through a high-speed serial interface 10GBASE-KR (10 GBase-KR is an on-board Ethernet interface, and the serial data rate is 10.3125 Gbps).
As shown in fig. 2, the present invention is a clock synchronization method for trillion synchronous ethernet, which is composed of an upstream unit and a downstream unit. The upstream unit and the downstream unit are respectively provided with an FPGA, a gigabit Ethernet PHY and a PLL frequency synthesizer. The FPGA and the PHY support a 10G BASE-KR interface, the PHY supports a synchronous Ethernet function, a 2-level PLL is arranged in the PLL frequency synthesizer, the 1 st level PLL has a clock jitter removal function and improves the phase noise of an input clock, the 2 nd level PLL is used for frequency multiplication, and when the input clock does not exist, an output clock can be kept. The upstream and downstream ten-gigabit ethernet PHY is set to loop timing (loop clock: the clock for transceiving data on the network wire comes from the master) mode.
The clock synchronization method of the ten-gigabit synchronous Ethernet has the following working principle:
the upstream unit PLL frequency synthesizer takes 25MHz TCXO (temperature compensated oscillator) as a reference, frequency is multiplied to 156.25MHz to output two paths of reference clocks, one path of clock is used as a reference for a 10G BASE-KR interface of the FPGA, and the other path of clock is used as a reference clock for the gigabit Ethernet PHY. Because the phase noise of the TCXO is better, the 25MHz TCXO clock is directly sent to the 2 nd level PLL of the PLL frequency synthesizer for frequency multiplication, and the 1 st level PLL is not used. After the FPGA finishes digital signal processing, data is transmitted and received between the FPGA and the gigabit PHY through a 10GBASE-KR interface, the gigabit Ethernet PHY transmits and receives data on a network line through a 10G BASE-T (the 10GBASE-T is connected by using a copper cable twisted pair, the effective bandwidth of a data layer is 10 Gbit/s), meanwhile, the PHY of an upstream unit is set as a master, and the PHY transmits and receives the data on the network line through a reference clock 156.25 MHz.
The downstream unit, the gigabit ethernet PHY, is set to slave, and transmits and receives data through the network cable. The PHY supports synchronous ethernet functionality, recovers the clock from the network line, and outputs a 25MHz SYNCEOUT clock. The SYNCEOUT clock is used as a reference for a PLL frequency synthesizer, is subjected to debounce by a level 1 PLL, is subjected to frequency multiplication by a level 2 PLL, and outputs two paths of 156.25MHz clocks, one path of clock is used as a reference clock for a gigabit Ethernet PHY, and the other path of clock is used as a reference clock for a 10G BASE-KR interface of the FPGA. Data are transmitted and received between the FPGA and the tera PHY through a 10GBASE-KR interface, and the clocks for transmitting and receiving the 10GBASE-KR high-speed serial data are homologous due to the homologous reference clocks. When no network cable is connected between upstream and downstream, the PLL frequency synthesizer has a clock holding function and can output a stable 156.25MHz clock; after the connection between the upstream unit and the downstream unit is established through the network cable, the 156.25MHz clock source output by the downstream PLL frequency synthesizer comes from the upstream 25MHz TCXO. Because the gigabit ethernet PHY is set to the loop timing mode, the upstream and downstream transmit-receive clocks are completely synchronized.
The above clock frequencies are used as examples, and other frequencies may be used as needed in specific implementations.
Preferably, the PLL frequency synthesizer is of the type AD9524BCPZ-REEL7, and the gigabit ethernet PHY is of the type: BCM84851, FPGA model: XC7K160T-2FFG 676I. In particular implementations, a person skilled in the art can select a particular model.
The above is a preferred embodiment of the present invention, but the present invention is not limited to the above embodiment, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be construed as equivalents thereof, and they are included in the scope of the present invention.
Claims (2)
1. A clock synchronization method of a gigabit synchronous Ethernet, wherein the gigabit synchronous Ethernet comprises an upstream unit and a downstream unit, and the method is characterized in that: for short-distance transmission within 100m, ultra-6 type network CAT6e is used for transmission, an upstream unit and a downstream unit respectively comprise an FPGA, a gigabit Ethernet PHY and a PLL frequency synthesizer, and the upstream unit and the downstream unit are connected through network cables; 2-level PLL is integrated in the PLL frequency synthesizer, the 1 st-level PLL is used for clock jitter removal, and the 2 nd-level PLL is used for frequency multiplication; when the PLL frequency synthesizer has no reference clock input, clock output is kept; the gigabit Ethernet PHY supports synchronous Ethernet and recovers a clock from a network cable; the gigabit Ethernet PHY and the FPGA support a 10G BASE-KR interface;
in the upstream unit, a PLL frequency synthesizer takes 25MHz TCXO as a reference, frequency is multiplied to 156.25MHz to output two paths of reference clocks, one path of clock is used as a reference for a 10G BASE-KR interface of the FPGA, and the other path of clock is used as a reference clock for a ten-gigabit Ethernet PHY; wherein, the 25MHz TCXO clock is directly sent to the 2 nd level PLL of the PLL frequency synthesizer for frequency multiplication, the 1 st level PLL does not use; after the FPGA finishes digital signal processing, data are transmitted and received between the FPGA and the gigabit Ethernet PHY through a 10GBASE-KR interface, the gigabit Ethernet PHY transmits and receives data on a network cable through a 10G BASE-T interface, meanwhile, the PHY of an upstream unit is set as a master, and the PHY transmits and receives the data on the network cable through a reference clock 156.25MHz of the PHY;
in a downstream unit, a gigabit Ethernet PHY is set as slave, and receives and transmits data through a network cable; the gigabit Ethernet PHY recovers a clock from the network cable and outputs a SYNCEOUT clock of 25 MHz; the SYNCEOUT clock is used as a reference for a PLL frequency synthesizer, is subjected to debounce by a level 1 PLL, is subjected to frequency multiplication by a level 2 PLL, and outputs two paths of 156.25MHz clocks, one path of clock is used as a reference clock for a gigabit Ethernet PHY, and the other path of clock is used as a reference clock for a 10G BASE-KR interface of the FPGA.
2. The clock synchronization method of ten-gigabit synchronous ethernet according to claim 1, wherein: setting the gigabit Ethernet PHY of the upstream unit as a master, and setting the gigabit Ethernet PHY of the downstream unit as a slave; after the upstream unit and the downstream unit are connected through a network cable, the gigabit Ethernet PHY of the downstream unit recovers a clock of the upstream unit, the recovered clock is used as a reference clock source of a PLL frequency synthesizer, and the PLL frequency synthesizer provides a reference clock input pin of the PHY and a 10G BASE-KR interface of the FPGA as a reference clock; when the upstream unit and the downstream unit are disconnected, the PLL frequency synthesizer keeps clock output and provides a reference clock for a reference clock input pin of the PHY and a 10G BASE-KR interface of the FPGA;
the PLL frequency synthesizer is AD9524BCPZ-REEL7 in model, the gigabit Ethernet PHY is BCM84851 in model, and the FPGA is XC7K160T-2FFG676I in model.
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| CN105634637A (en) * | 2015-12-22 | 2016-06-01 | 大唐电信（成都）信息技术有限公司 | PTP and SYNC-E fused time-frequency synchronization method |
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| CN101005349B (en) * | 2007-01-09 | 2010-05-19 | 华为技术有限公司 | Clock synchronizing method and system |
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