CN106897106B - The concurrent DMA of multi-dummy machine sequential scheduling method and system under a kind of SR IOV environment - Google Patents
The concurrent DMA of multi-dummy machine sequential scheduling method and system under a kind of SR IOV environment Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
- G06F2009/45579—I/O management, e.g. providing access to device drivers or storage
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Abstract
The present invention relates to the sequential scheduling method and system of the concurrent DMA of multi-dummy machine under SR IOV environment a kind of, the dispatching method includes：Multiple virtual machines send DMA request order to PCle equipment；Design is lined up the mechanism of registration；Design the state machine of automatic cycle detection；Open the DMA read operations of different virtual machine；Reset；The DMA of the state machine testing virtual machine of automatic cycle detection.A kind of system is further related to, the system includes：Multiple virtual machines, a PCIe device；Include in the PCIe device：Multiple command register groups, the first register, the second register, multiple virtual-machine data memories, the state machine of automatic cycle detection.By the way that automatic order performs under the control of state machine the invention enables the DMA of multi-dummy machine, the burden of CPU in PCle equipment is not only alleviated, also substantially increases the concurrent DMA of multi-dummy machine data transmission bauds.
Description
Technical field
The present invention relates to the technical field of the data transfer of PCIe high-speed buses, more particularly under a kind of SR-IOV environment
The concurrent DMA of multi-dummy machine sequential scheduling method and system.
Background technology
Virtualization technology, multitask and Hyper-Threading are entirely different, and multitask refers in an operating system
In multiple programs simultaneously run together, be that can run multiple operating systems simultaneously in virtualization technology, and each operate
There are multiple programs to run in system, each operating system operates in a virtual CPU either on fictitious host computer, and
Hyper-Threading is that single CPU simulated duals CPU carrys out equilibrium code runnability, and it is to separate that the two, which simulate the CPU come,
, it can only cooperate.In addition, virtualization scheme mainly has two kinds, software virtualization and hardware virtualization, wherein, software is empty
Planization is the solution of former main flow, but major defect existing for the program be because data flow Delamination Transmission in software,
Greatly reduce actual data transmission efficiency, it is often more important that under current big data and the trend of cloud computing, can not meet
The demand of higher and faster message transmission rate, and cause data flow to need not move through the layering of software using hardware virtualization technology
Transmit, transparent transmission is carried out directly between internal memory and hardware peripherals, substantially increases the transmission speed of data flow.
Current hardware virtualization technology is single I/O virtualization (SR-IOV) technology, and SR-IOV is a kind of specification so that
Single quick peripheral assembly interconnecting (PCIe) physical equipment under single port is shown as management program or Client OS
Multiple single physical equipments.
The physical function (PF) and virtual functions (VF) that SR-IOV is used are the global function of SR-IOV equipment controles, and PF is
Complete PCIe functions, it includes the SR-IOV expanded functions for being used for configuring and manage SR-IOV functions, in addition, PF can be configured
With control PCIe device, and PF has and moves data into and remove the complete function of equipment, and VF is the PCIe functions of lightweight, its
Required all resources are moved comprising data, and with a set of configuration resource set by carefully simplifying.
Support SR-IOV PCIe device that its multiple example is supplied into Client OS example and management program, carry
The virtual functions quantity of confession depends on equipment, and for the PCIe device for having enabled SR-IOV to be run, journey is driven in client computer
In sequence or management program example, it is necessary to possess appropriate BIOS and hardware supported and SR-IOV is supported.
In current many high-speed data processing application scenarios, occupied an leading position for the read-write transaction of memory,
In the high speed data transfer application based on PCIe, PCIe endpoint 1590 (Endpoint) equipment will give play to the data transfer effect of maximum
Can, at the same be reduced as far as the occupancy of host CPU it is necessary to using dma mode, be exactly from PCIe endpoint 1590 equipment on one's own initiative to
Host memory initiates DMA read request, then receives the data that transmission is come in, or by PCIe endpoint 1590 equipment on one's own initiative in main frame
Initiation DMA write request is deposited, to complete data-transformation facility.According to SR-IOV specifications, can be realized inside a PCIe device
Multiple virtual unit VF, some virtual machine can that such operating system is supported are bound together with some specific VF,
Exclusively enjoy the access to this virtual unit VF.Generally, each equipment is to use DMA working methods, is virtually set when only one
During standby work, situation is very simple.But work as the virtual units different from PCIe device respectively of multiple virtual machines in operating system
After binding one by one, the concurrent DMA of multiple virtual machines situation there is.No matter how many virtual unit inside PCIe device, this
A little virtual units must all be carried out data transmission by the physical transmission channel of PCIe device, and this passage is only one
, therefore as the concurrent DMA of the virtual unit corresponding to multiple virtual machines in PCIe device, how to allow these concurrent DMA to divide
It is not orderly to carry out the problem of being one most important.
The content of the invention
The technical problems to be solved by the invention are：When the virtual unit corresponding to multiple virtual machines in PCIe bus apparatus
During concurrent DMA, prior art can not make above-mentioned concurrent DMA distinguish orderly progress.
In order to solve the above technical problems, the invention provides the order of the concurrent DMA of multi-dummy machine under SR-IOV environment a kind of
Dispatching method, the dispatching method comprise the following steps：
S1, multiple virtual machines send DMA request order to PCIe device respectively, and PCIe device orders described DMA request
Order is respectively stored into each command register group in PCIe device；
S2, design are lined up the mechanism of registration：Multiple virtual machines are ranked registration, generation virtual machine number, and will note
Virtual machine number after volume is stored in the first register in PCIe device；
S3, when the first register one virtual machine number of storage, then deposited accordingly in the second register in PCIe device
Storage mark is set to 1 by 0；
S4, the state machine of a set of automatic cycle detection is designed, state machine cyclically detects the second register in order, if inspection
The storage mark measured is 1, then PCIe device automatically turns on virtual machine corresponding to virtual machine number corresponding with storage mark
DMA read operations；
S5, after starting DMA read operations, PCIe device receives the data that are sent by the virtual machine, and by data storage
In to PCIe device in virtual machine memory corresponding with the virtual machine；
In S6, S5 after the data of the virtual machine are all stored in virtual machine memory, the second register and institute
State the corresponding storage mark clear 0 of virtual machine；
S7, the state machine of automatic cycle detection continue to monitor in order next storage mark, circulation in the second register
Detection.
Further, PCIe device parses DMA request order in the S1, is judged and the DMA request according to analysis result
Virtual machine corresponding to order, and the DMA request order is stored to command register corresponding with the virtual machine in PCIe device
In group.
Above-mentioned further beneficial effect：DMA command register group is designed, corresponds respectively to different virtual machines so that
The transmission of concurrent virtual machine DMA request order is independent of one another, does not interfere with each other.
Further, in the S2, being lined up login mechanism is ranked registration according to the sequencing of time, to multiple
It is that basis is suitable to the time order and function of the DMA request order arrival PCIe device of multiple virtual machines transmission that virtual machine, which is ranked and registered,
Sequence is ranked registration.
Further, in the S2, the number after registration is the first deposit being sequentially stored in sequence in PCIe device
In device.
Further, in the S3, the second register and the first register correspond, when the first register stores in order
One virtual machine number, then the second register correspondingly will store to mark is set to 1 by 0 in order.
Beneficial effects of the present invention：Devise DMA and be lined up login mechanism and virtual machine circulation automatic detection state machine, can
So as to obtain DMA automatic order execution under the control of state machine of multi-dummy machine, it is not necessary to the participation of the CPU in PCIe device,
The burden of CPU in PCIe device is not only alleviated, also substantially increases the concurrent DMA of multi-dummy machine data transmission bauds.
The invention further relates to the sequential scheduling system of the concurrent DMA of multi-dummy machine under SR-IOV environment a kind of, the scheduling system
Including:Multiple virtual machines, a PCIe device；Include in the PCIe device：Multiple command register groups, the first register,
Second register, multiple virtual machine memories, the state machine of automatic cycle detection；Described multiple virtual machines pass through PCIe buses
Contacted with the virtual unit in PCIe device；Multiple command register groups, the DMA request sent for storing multiple virtual machines
Order；First register, for storing the herd number after more virtual machines are registered；Second register, for being posted according to first
The herd number of storage storage correspondingly does storage mark；Multiple virtual machine memories, the number of coming is returned to for storage virtual machine DMA
According to；The state machine of automatic cycle detection, for detecting the second register.
Further, described multiple command register groups, the DMA request order sent for storing multiple virtual machines, institute
The DMA request order stated is parsed by PCIe device.
Further, the first described register and the second register correspond.
Further, the system also includes：The state machine of automatic cycle detection, for detecting the second register, when detecting
Storage when being labeled as 1, corresponding with result virtual machine automatically turns on DMA read operations, and virtual machine is sent to PCIe device
Data；If the storage of detection is labeled as 0, state machine continues to monitor next storage mark.
Further, the second described register is additionally operable to when the data for the virtual machine for opening DMA read operations are all deposited
After storing up in virtual machine memory, the second register storage mark clear 0 corresponding with the virtual machine.
Above-mentioned further beneficial effect：Devise DMA and be lined up login mechanism and virtual machine circulation automatic detection state
Machine, the DMA of the multi-dummy machine automatic order under the control of state machine can be caused to perform, it is not necessary to CPU's in PCIe device
Participate in, not only alleviate the burden of CPU in PCIe device, also substantially increase the concurrent DMA of multi-dummy machine data transmission bauds.
Brief description of the drawings
Fig. 1 is the sequential scheduling method flow diagram of the concurrent DMA of multi-dummy machine under a kind of SR-IOV environment of the invention；
Fig. 2 is the schematic diagram of the concurrent DMA of multi-dummy machine sequential scheduling method under a kind of SR-IOV environment of the present invention；
Fig. 3 is the schematic diagram of the concurrent DMA of multi-dummy machine sequential scheduling method under a kind of SR-IOV environment of the present invention.
Embodiment
The principle and feature of the present invention are described below in conjunction with accompanying drawing, the given examples are served only to explain the present invention, and
It is non-to be used to limit the scope of the present invention.
In the present invention it is described below it is multiple be at least two, such as：Multiple virtual machines are at least two virtual machine；Multiple lives
It is at least two command register group to make register group.
As shown in Figure 1, under a kind of SR-IOV environment of the invention the concurrent DMA of multi-dummy machine sequential scheduling method, the tune
Degree method comprises the following steps:
S1, multiple virtual machines send DMA request order, DMA request to virtual unit corresponding to PCIe device the inside respectively
Order passes through PCIe bus transfers to PCIe device, the described DMA request order of PCIe device parsing, if it is virtual to parse
Machine VF1 DMA request order, and the life that described DMA request order storage is arrived in PCIe device corresponding with the virtual machine
Make in register group；
S2, the mechanism that in chronological sequence decision queue registers of design one, by DMA request order according to arrival PCIe device
Time order and function order, registration that more virtual machines are ranked, and the virtual machine number after registration is stored successively in order
In the first register in PCIe device；
S3, the second register and the first register in PCIe device correspond, when the first register stores in order
One virtual machine number, then the second register is wanted to mark storage with answering is set to 1 by 0 in order；
S4, the state machine of a set of automatic cycle detection is designed, state machine cyclically detects the second register in order, if inspection
The storage mark measured is 1, and state machine reads virtual machine number corresponding with storage mark in the first register, PCIe device
Automatically turn on virtual machine DMA read operations corresponding with virtual machine number；
S5, after starting DMA read operations, PCIe device receives the DMA data that is sent by the virtual machine, and by DMA data
Store in PCIe device in virtual machine memory corresponding with the virtual machine；
S6, after the virtual machine DMA data is all stored in virtual machine memory in S5, the second register and the void
The corresponding storage mark clear 0 of plan machine；
S7, the state machine of automatic cycle detection continue to monitor in order next storage mark, circulation in the second register
Detection, until all storages are marked all by clear 0 in the second register.
The concurrent DMA of multi-dummy machine sequential scheduling system under a kind of SR-IOV environment, the scheduling system include:It is multiple virtual
Machine, a PCIe device；Include in the PCIe device：Multiple command register groups, the first register, the second register, from
The state machine of dynamic cycle detection；Described multiple virtual machines refer to multiple independent application programs in operating system, pass through
The virtual unit of PCIe buses and PCIe device connects；Multiple command register groups, multiple command register groups, for depositing
The DMA request order that multiple virtual machines are sent is stored up, described DMA request order is parsed by PCIe device；First deposit
Device, for storing the herd number after multiple virtual machines are registered；Second register, for the registration stored according to the first register
Number correspondingly does storage mark；Wherein, the first register and the second register are one-to-one；Multiple virtual machine memories,
The data returned for storage virtual machine DMA；The state machine of automatic cycle detection, for detecting the second register.
The system also includes：The state machine of automatic cycle detection, for detecting the second register, when the storage mark detected
When being designated as 1, virtual machine corresponding with the result automatically turns on DMA read operations, and virtual machine sends data to PCIe device；If inspection
When the storage of survey is labeled as 0, state machine continues to monitor next storage mark.
Second register is additionally operable to when the data for the virtual machine for opening DMA read operations are all stored in virtual machine storage
After in device, the second register storage mark clear 0 corresponding with the virtual machine.
Specific embodiment
As described in Figure 2, it can be seen that being configured with single order inside PCIe device for each virtual machine
Register group is to record the DMA request order transmitted from virtual machine；It is in addition, also independent virtual for each inside PCIe device
Machine is all configured with single virtual machine memory, to store the data come in from virtual machine upper layer transport.
As described in Figure 3, it can be seen that the DMA read commands that PCIe device is sent to different virtual machine are registered,
The virtual machine DMA request order of first arrival is registered to number one position in queue, while No.1 position is masked as
1 is set to from 0, shows the position with the presence of DMA reading tasks；The virtual machine DMA reading tasks subsequently to arrive are according to arrival time
Sequencing is lined up successively, and in corresponding mark position 1.
The program devises DMA command register group and virtual machine memory, wherein virtual machine memory, is for storing
Virtual machine DMA returns to the data of coming, and each virtual machine can be with the virtual machine memory of a virtual unit bound in it
Corresponding, after the virtual machine starts dma operation, the data that PCIe device returns are stored in the virtual machine corresponding to the virtual machine
In memory, the virtual machine memory of virtual unit is independent of each other., command register group and virtual machine memory are right respectively
Should be in different virtual machines, so, the transmission of concurrent virtual machine DMA order and the storage of virtual machine DMA returned datas are each other
It is independent, it does not interfere with each other.Devise DMA and be lined up login mechanism and virtual machine circulation automatic detection state machine, can cause more empty
The DMA of plan machine automatic orders under the control of state machine perform, it is not necessary to the participation of the CPU in PCIe device, not only alleviate
CPU burden in PCIe device, also substantially increase the concurrent DMA of multi-dummy machine data transmission bauds.
Supporting hardware virtualization SR-IOV PCIe device allows multiple different virtual machines are concurrent to be operated, this
One PCIe device can be invented multiple independent virtual unit VF, these different virtual units point on an operating system
Not with VF1, VF2 ..., VFn mark.
Embodiment
Step 1, concurrent virtual machine command dma is sent
When above-mentioned different virtual machine concurrent efforts, similar and different at the time of, each virtual machine is respectively to each right
Virtual unit VF1, VF2 for answering ..., VFn etc. send DMA request order, these different virtual machines self-corresponding are virtually set to each
The DMA request order that preparation is sent, by PCIe bus transfers to PCIe device, PCIe device parses the packet of these arrivals,
And the implication of these packets is parsed, and if the packet parsed is the command dma for virtual machine VF1, the life
Order is just stored in VF1 command register groups corresponding to virtual machine VF1 shown in Fig. 2.
Step 2, concurrent virtual machine DMA is lined up registration
A queuing mechanism is devised, the thought of the queuing mechanism is to reach PCIe according to the command dma of different virtual machine
The priority time sequencing of equipment is ranked registration, and what is reached at first comes foremost, and what is finally reached comes backmost, from figure
3 can see, and this queuing mechanism employs two registers.First register is virtual machine registration register, according to each
The sequencing that virtual machine command dma arrives, ranks, the virtual machine VFn1 reached at first comes the deposit to each virtual machine
The first place of device, and virtual machine number n1 corresponding to the virtual machine, it is recorded in this position, the virtual machine VFn2 of second arrival
Second is come, and virtual machine number n2 corresponding to the virtual machine is recorded in this position；The virtual machine subsequently reached is successively
Analogize queuing registration.
Second register is queue task flag register, and after the virtual machine VFn1 reached at first has been registered, troop appoints
The highest order of business flag register is set to 1 by 0, shows that present bit is equipped with DMA task；The virtual machine of second arrival VFn2 times
A high position is set to 1 by 0, and other subsequently reaching for tasks are handled like this successively.
Step 3, virtual machine dma operation is started
A set of automatic cycle detection state machine is devised, when the detection queue task flag that the state machine circulates from the beginning to the end
Register, when it is 0 to find a certain position in queue task flag position, then go to search follow-up queue flag bit, when discovery first
It is individual be 0 flag bit when, then read to should position virtual machine registration register, virtual machine number corresponding to reading
Code, then starts the dma operation of the virtual machine, once starting the dma operation of the virtual machine, it is virtual that this is corresponded in PCIe device
The DMA channel of machine just starts, and then PCIe device receives the virtual machine from the outside data being delivered to inside PCIe device, and will
These data storages are in virtual machine memory corresponding with the virtual machine.
Step 4, queue task flag register-bit clear 0, next virtual machine DMA tasks are started
Virtual machine DMA data are changeable, read for the big DMA of data volume, it is necessary to which the dma controller of virtual machine is sent
Multiple command dma can just obtain whole data.Therefore, automatic cycle detection state machine, must wait until current virtual machine
Command dma is all sent could be by queue task flag register-bit clear 0 corresponding to current virtual machine.Then sequence detection
Next flag bit being not zero, once finding there is the new not flag bit for 0, just start next virtual machine DMA tasks.
Step 5, the like, circulation performs
When not having pending processing virtual machine DMA or queue search to be ended up to queue in queue, queue is backed within
Initial ranging state, cycle detection.
In this manual, identical embodiment or example are necessarily directed to the schematic representation of above-mentioned term.
Moreover, specific features, structure, material or the feature of description can be in any one or more embodiments or example with suitable
Mode combines.In addition, in the case of not conflicting, those skilled in the art can be by the difference described in this specification
Embodiment or example and the feature of different embodiments or example are combined and combined.
The foregoing is only presently preferred embodiments of the present invention, be not intended to limit the invention, it is all the present invention spirit and
Within principle, any modification, equivalent substitution and improvements made etc., it should be included in the scope of the protection.
Claims (10)
1. a kind of concurrent DMA of multi-dummy machine sequential scheduling method under SR-IOV environment, it is characterised in that the dispatching method includes
Following steps：
S1, multiple virtual machines send DMA request order to PCIe device respectively, and PCIe device divides described DMA request order
Do not store in each command register group in PCIe device；
S2, design are lined up the mechanism of registration：Multiple virtual machines are ranked registration, generation virtual machine number, and will registration after
Virtual machine number be stored in the first register in PCIe device；
S3, when the first register stores a virtual machine number, then corresponding storage is marked in the second register in PCIe device
Note is set to 1 by 0；
S4, the state machine of a set of automatic cycle detection is designed, state machine cyclically detects the second register in order, if detecting
Storage mark be 1, then PCIe device automatically turns on virtual machine DMA readings corresponding to corresponding with storage mark virtual machine number
Extract operation；
S5, after starting DMA read operations, PCIe device receives the data sent by the virtual machine, and stores data into
In PCIe device in virtual machine memory corresponding with the virtual machine；
S6, after the data of the virtual machine are all stored in virtual machine memory, the second register and the virtual machine
Corresponding storage mark clear 0；
S7, the state machine of automatic cycle detection continue to monitor in order next storage mark, cycle detection in the second register.
2. the concurrent DMA of multi-dummy machine sequential scheduling method, its feature under a kind of SR-IOV environment according to claim 1
It is, in the S1, parses DMA request order using PCIe device, judged and the DMA request order pair according to analysis result
The virtual machine answered, and by DMA request order storage to PCIe device, in command register group corresponding with the virtual machine.
3. the concurrent DMA of multi-dummy machine sequential scheduling method under a kind of SR-IOV environment according to claim 1 or 2, its
It is characterised by, in the S2, being lined up login mechanism is ranked registration according to the sequencing of time, to multiple virtual machines
Registration of ranking is that the time order and function order that PCIe device is reached according to the DMA request order sent to multiple virtual machines is carried out
It is lined up registration.
4. the concurrent DMA of multi-dummy machine sequential scheduling method, its feature under a kind of SR-IOV environment according to claim 3
It is, in the S2, the number after registration is in the first register being sequentially stored in sequence in PCIe device.
5. the concurrent DMA of multi-dummy machine sequential scheduling method, its feature under a kind of SR-IOV environment according to claim 4
It is, in the S3, the second register and the first register correspond, when the first register stores a virtual machine in order
Number, then the second register correspondingly will store to mark is set to 1 by 0 in order.
A kind of 6. concurrent DMA of multi-dummy machine sequential scheduling system under SR-IOV environment, it is characterised in that the scheduling system bag
Include:Multiple virtual machines, a PCIe device；Include in the PCIe device：Multiple command register groups, the first register,
Two registers, multiple virtual machine memories, the state machine of automatic cycle detection；Described multiple virtual machines by PCIe buses with
The virtual unit of PCIe device connects；Multiple command register groups, the DMA request life sent for storing multiple virtual machines
Order；First register, for storing the herd number after more virtual machines are registered；Second register, for according to the first deposit
The herd number of device storage correspondingly does storage mark；The state machine of automatic cycle detection, for detecting the second register；Multiple void
Plan machine memory, the data returned for storage virtual machine DMA.
7. the concurrent DMA of multi-dummy machine sequential scheduling system, its feature under a kind of SR-IOV environment according to claim 6
It is, described multiple command register groups, the DMA request order sent for storing multiple virtual machines, described DMA request
Order is parsed by PCIe device.
8. the concurrent DMA of multi-dummy machine sequential scheduling system, its feature under a kind of SR-IOV environment according to claim 7
It is, the first described register and the second register are one-to-one.
9. the concurrent DMA of multi-dummy machine sequential scheduling system, its feature under a kind of SR-IOV environment according to claim 8
It is, the system also includes：The state machine of automatic cycle detection, for detecting the second register, when the storage mark detected
For 1 when, automatically turn on DMA read operations labeled as 1 corresponding virtual machine with the storage, virtual machine sends number to PCIe device
According to；If the storage of detection is labeled as 0, state machine continues to monitor next storage mark.
10. the concurrent DMA of multi-dummy machine sequential scheduling system under a kind of SR-IOV environment according to claim 8, it is special
Sign is that the second described register is additionally operable to when the data for the virtual machine for opening DMA read operations are all stored in virtually
After in machine memory, the second register storage mark clear 0 corresponding with the virtual machine.
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| JP4733399B2 (en) * | 2005-01-28 | 2011-07-27 | 株式会社日立製作所 | Computer system, computer, storage device and management terminal |
| CN104123252A (en) * | 2013-04-26 | 2014-10-29 | 韩国科亚电子股份有限公司 | Multi-channel direct memory access controller and control method thereof |
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