CN106887434A - Three-dimensional storage element - Google Patents
Three-dimensional storage element Download PDFInfo
- Publication number
- CN106887434A CN106887434A CN201510929883.9A CN201510929883A CN106887434A CN 106887434 A CN106887434 A CN 106887434A CN 201510929883 A CN201510929883 A CN 201510929883A CN 106887434 A CN106887434 A CN 106887434A
- Authority
- CN
- China
- Prior art keywords
- serial
- memory cell
- ground connection
- switch
- wiretap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Abstract
The invention discloses a kind of three-dimensional storage element, including multi-layer laminate structure, multi-layer laminate structure includes multiple conductive strips and a plurality of raceway groove, to define the carinate lamination of first, second, third and fourth；The first serial selection line switch on the first carinate lamination；The first ground connection selection wiretap on the second carinate lamination；First U-shaped memory cell is serial, and the first serial selection line of concatenation switch and first is grounded selection wiretap；The second serial selection line switch on the 3rd carinate lamination；The second ground connection selection wiretap on the 4th carinate lamination；Second U-shaped memory cell is serial, and the second serial selection line of concatenation switch and second is grounded selection wiretap.First word line contact structure is contacted with the conductive strips of the first carinate lamination.Second word line contact structure is contacted with the conductive strips of the second carinate lamination；3rd word line contact structure is contacted with the conductive strips of the third and fourth carinate lamination.
Description
Technical field
The invention relates to a kind of high-density storage element.Particularly a kind of three-dimensional (Three
Dimemsional, 3D) memory component.
Background technology
Non-volatile memory device, such as flash memory, are stored in also not lost when power supply is removed
The characteristic of the information in mnemon.It has been widely used in for portable music player, mobile electricity
The solid-state large-capacity storage application of words, digital camera etc..In order to reach with more high density storage capacity
Demand, had the three-dimensional storage element of various different structures at present, such as with single grid
(single-gate) memory cell, bigrid (double gate) memory cell, and circulating type grid
The three-dimensional flash memory element of (surrounding gate) memory cell, is suggested.
Typical three dimensional nonvolatile memory component is implemented in multi-layer laminate structure comprising multiple
Memory cell solid array with vertical channel among (multi-layer stacks).Deposited with U-shaped
Single gate vertical passage (Single-Gate Vertical Channel, SGVC) of storage unit serial structure
As a example by nand memory element, usually it is used as depositing using the lamination conductive strips of polysilicon material
The grid of storage unit.Because the resistance of polysilicon is larger, therefore when memory cell array is built, need
By conductive strips with being divided into multiple sections, and excessively stair-stepping word line contact block word contact structure,
The conductive bar of same stratum will be located to be electrically connected with the metal word lines being located above memory cell array.
Because word line contact structure occupies the sizable area of memory component, adds memory cell battle array
The wiring space that row top accommodates metal word lines is limited.With the expansion of memory component memory capacity,
So that the quantity relative increase of conductive strips stratum is, it is necessary to set more multi-word lines in multilayer laminated Rotating fields
With word line contact structure.By reducing the line footpath and spacing (pitch) of wordline, or can only increase at present
The area size of memory region come be subject in response to.
However, reduce wordline line footpath and spacing can cause process margin (process window) reduce,
Yield reduces and process costs is significantly increased, or even because causing oxide layer breakdown (oxide breakdown)
Phenomenon is produced.Increase the area size of memory region and do not meet the trend of current element micro.
Therefore, it is in need that a kind of advanced memory component is provided, to solve what above-mentioned technology was faced
Problem.
The content of the invention
One embodiment of this specification is to provide a kind of three-dimensional storage element.This three-dimensional storage element
Including：Multi-layer laminate structure (multi-layer stacks), the first serial selection line (String Select Line,
SSL) switch, the first ground connection selection line (Ground Selection Line, GSL) switch, second serial
Selection wiretap, the second ground connection selection wiretap, the first U-shaped memory cell are serial, the second U-shaped
Memory cell is serial, the first word line contact structure, the second word line contact structure and the 3rd word line contact
Structure.Multi-layer laminate structure includes the multiple conductive strips and a plurality of raceway groove (trench) that are isolated from each other,
At least to define the first carinate lamination (ridge stacks), the second carinate lamination, the 3rd carinate folded
Layer and the 4th carinate lamination.First serial selection line switch is located on the first carinate lamination.First
Ground connection selection wiretap is located on the second carinate lamination.First U-shaped memory cell serially concatenates first
Serial selection line is switched and the first ground connection selection wiretap.Second serial selection line switch is located at the 3rd ridge
On shape lamination.Second ground connection selection wiretap is located on the 4th carinate lamination.Second U-shaped is stored
Serially the second serial selection line of concatenation switch and second is grounded selection wiretap to unit.First word line contact
Structure is contacted with the conductive strips on the first carinate lamination.Second word line contact structure be located at the
Conductive strips contact on two carinate laminations；3rd word line contact structure be located at the 3rd carinate lamination and
Conductive strips contact on 4th carinate lamination.
According to above-described embodiment, this specification is to provide a kind of three-dimensional storage with multiple carinate laminations
Device element, the carinate lamination of each of which is included, respectively with a serial selection line positioned at top
Switch or a ground connection select wiretap and positioned at serial selection line switch or the ground connection selection line
Multiple memory cell below switch.The first serial selection by concatenation on two carinate laminations
Wiretap and the first ground connection selection wiretap, and positioned at the first serial selection line switch and the first ground connection
Memory cell below selection wiretap is serial to form the first U-shaped memory cell；Simultaneously by concatenation
The second serial selection line switch and the second ground connection selection line on two other different carinate lamination
Switch, and the storage list below the second serial selection line switch and the second ground connection selection wiretap
Unit is serial to form the second U-shaped memory cell.
Wherein, the storage below serial the first serial selection line switch of the first U-shaped memory cell
Unit is connected with the first word line contact structure；Positioned at the second serial choosing that the second U-shaped memory cell is serial
The memory cell below wiretap is selected to be connected with the second word line contact structure；And it is located at the storage of the first U-shaped
Unit it is serial first ground connection selection wiretap below memory cell and positioned at the second U-shaped storage
Memory cell below the second serial ground connection selection wiretap of unit, then be connected to the word of identical the 3rd
Contact structure.In other words, in three-dimensional storage element, for connecting positioned at ground connection selecting switch
The word line contact number of structures of the memory cell of lower section is less than and is used for connecting under serial selecting switch
The word line contact structure of the memory cell of side.If compared with the three-dimensional storage element in prior art,
On the premise of memory capacity is not changed, it is possible to reduce the setting of word line contact structure.
By the setting for reducing word line contact structure, it is possible to reduce the area size of memory component；More
Can be on the premise of process margin not be influenceed, the memory capacity of extended menory element is greatly reduced work
Skill cost, and prevent oxide punch from producing, the technique for increasing vertical channel memory component is good
Rate.
Brief description of the drawings
Other objects of the present invention, feature and advantage are found in following embodiments and right,
And coordinate institute's accompanying drawings, it is described in detail below：
Figure 1A to Fig. 1 D is a kind of single gate vertical passage NAND according to depicted in known technology
The partial structurtes perspective view of memory component；
Fig. 2 is the part of the single gate vertical passage nand memory element according to depicted in Fig. 1 D
Structure top view；
Fig. 3 is that single gate vertical passage NAND depicted according to another embodiment of the present invention is deposited
The partial structurtes top view of memory element；
Fig. 4 is to illustrate to carry out write-in behaviour with single gate vertical passage nand memory element of Fig. 1 C
Make equivalent circuit diagram when (program operation)；
Fig. 5 is to illustrate to be read out behaviour with single gate vertical passage nand memory element of Fig. 1 C
Make equivalent circuit diagram when (read operation)；And
Fig. 6 is to illustrate to carry out erasing behaviour with single gate vertical passage nand memory element of Fig. 1 C
Make equivalent circuit diagram when (erase operation).
【Symbol description】
100、300：Memory component
101：Base material
102：Conductive layer
103：Insulating barrier
104：Multi-layer laminate structure
104A、104B、104C、104D：Carinate lamination
104A1-104A6、104B1-104B6、104C1-104C6、104D1-104D6：Conductive bar
Band
105：Raceway groove
106：Memory material layer
107：Semiconductor channel layer
108、108P、108R：Memory cell
109A、109B：U-shaped memory cell is serial
110A、110B：Ground connection selection wiretap
111A、111B：Serial selecting switch
112：Dielectric material layer
113：The air gap
114：Contact plunger
115：Bit line
116：Contact plunger
117：Plain conductor
118：Common source line
119A、119B、119C、319C：Word line contact structure
120：Wordline
121、122：Engagement pad
IG 1A, IG 1B controlling switches
IG 0A、IG 0B：Auxiliary switch
Vpgm：Write-in voltage
Vpass：Grid passes through voltage
Vref：Grid read voltage floating：It is floating
GIDL：Gate Induced Drain leakage current
Specific embodiment
The present invention is to provide a kind of memory component, it is possible to resolve known as memory device component technology nargin is not enough
Problem, while save manufacturing cost improve process yields.It is to allow above and other of the invention
Objects, features and advantages can become apparent, several preferred embodiments cited below particularly, and coordinate appended
Schema, is described in detail below.
But these specific case study on implementation are must be noted that, the present invention is not limited to.This hair
It is bright to be still carried out using other features, element, method and parameter.The proposition of preferred embodiment,
Only it is to illustrate technical characteristic of the invention, is not limited to scope of the presently claimed invention.
Have usually intellectual in the technical field, this will not can departed from according to the description of description below
In the scope of invention, make impartial modification with change.Among different embodiments and schema, phase
Same element, will be represented with identical component symbol.
Figure 1A to Fig. 1 C is refer to, Figure 1A to Fig. 1 C is that an embodiment of the invention is painted
Show the process structure perspective view for making single gate vertical passage nand memory element 100.Make
The method of single gate vertical passage nand memory element 100, comprises the steps：Exist first
Multi-layer laminate structure 104 is formed on the surface of base material 101 (as depicted in Figure 1A).In the present embodiment,
Multi-layer laminate structure 104 includes along the Z-direction depicted in Figure 1A, on base material 101 each other
Multiple conductive layers 102 of cross laminates and multiple insulating barriers 103.
In some embodiments of the present invention, the material of conductive layer 102 can be included doped with phosphorus or arsenic
N-shaped polysilicon (or N-shaped epitaxial monocrystalline silicon), p-type (or the p-type extension list doped with boron
Crystal silicon), undoped polysilicon, metal silicide (silicides), such as titanium silicide (TiSi), silicon
Change cobalt (CoSi) or SiGe (SiGe), oxide semiconductor (oxide semiconductors), for example, aoxidize
Indium zinc (InZnO) or indium gallium zinc (InGaZnO), metal, such as aluminium (Al), copper (Cu), tungsten (W),
Titanium (Ti), cobalt (Co), nickel (Ni), titanium nitride (TiN), tantalum nitride (TaN) or tantalum nitride aluminium (TaAlN),
Or the composition of two or more above-mentioned materials is constituted.Insulating barrier 103 can be by dielectric material, example
Such as Si oxide (oxide), silicon nitride (nitride), silicon nitrogen oxides (oxynitride), silicate
(silicate) or other materials, constituted.
Then, a Patternized technique is carried out to multi-layer laminate structure 104, to form multiple carinate laminations
104A, 104B, 104C and 104D.In some embodiments of the invention, it is using anisotropic erosion
Carving technology (anisotropic etching process), such as reactive ion etching (Reactive Ion Etching,
RIE) technique, is etched to multi-layer laminate structure 104.Use among multi-layer laminate structure 104
Formation is extended laterally and along the raceway groove 105 of Z axis Longitudinal extending along X, by multi-layer laminate structure 104
It is divided into multiple carinate lamination 104A, 104B, 104C and 104D, and by the part of base material 101
Region is exposed to outer (as depicted in Figure 1B) via raceway groove 105.
Each carinate lamination 104A, 104B, 104C and 104D include the conduction of multiple strips
Band.For example in the present embodiment, carinate lamination 104A has along Z-direction to superimposed layer
Conductive strips 104A1,104A2,104A3,104A4,104A5 and 104A6；Carinate lamination 104B
With along Z-direction to the conductive strips 104B1 of superimposed layer, 104B2,104B3,104B4,
104B5 and 104B6；Carinate lamination 104C has the conductive strips to superimposed layer along Z-direction
104C1,104C2,104B3,104C4,104C5 and 104C6；And carinate lamination 104D tools
There are conductive strips 104D1,104D2,104D3,104D4,104D5 to superimposed layer along Z-direction
And 104D6.Wherein, positioned at the top planes of carinate lamination 104A, 104B, 104C and 104D
Conductive strips 104A6,104B6,104C6 and 104D6 have than positioned at identical carinate lamination 104A,
The conductive strips 104A1-104A5 of other planes of 104B, 104C and 104D, 104B1-104B5,
104C1-104C5 and 104D1-104D5 also big thickness.
Afterwards, in the side wall top of carinate lamination 104A, 104B, 104C and 104D and raceway groove
105 bottoms formed have charge trapping structure (charge trapping structure), memory material layer
106.And in forming the semiconductor channel layer 107 of patterning on memory material layer 106.And then carinate
The conductive strips 104A1-A6 of lamination 104A, 104B, 104C and 104D, 104B1-B6,
Position 104C1-C6 and 104D1-D6 Chong Die with memory material layer 106 and the three of channel layer 107
(cross point), defines multiple memory cell 108 respectively (as depicted in Fig. 1 C).
In some embodiments of the invention, the charge trapping structure of memory material layer 106 can be one
Plant and be combined many laminations, it is selected from by Si oxide-silicon nitride-Si oxide
(oxide-nitride-oxide, ONO) structure, one Si oxide-silicon nitride-Si oxide-silicon nitride-silicon
Oxide (oxide-nitride-oxide-nitride-oxide, ONONO) structure, one silicon-Si oxide-
Silicon nitride-Si oxide-silicon (silicon-oxide-nitride-oxide-silicon, SONOS) structure, one
Energy gap engineering silicon-Si oxide-silicon nitride-Si oxide-silicon (bandgap engineered
Silicon-oxide-nitride-oxide-silicon, BE-SONOS) structure, tantalum nitride-aluminum oxide-nitrogen
SiClx-Si oxide-silicon (tantalum nitride, aluminum oxide, silicon nitride, silicon
Oxide, silicon, TANOS) structure and a metal high-dielectric coefficient energy gap engineering silicon-Si oxide-
Silicon nitride-Si oxide-silicon (metal-high-k bandgap-engineered
Silicon-oxide-nitride-oxide-silicon, MA BE-SONOS) group that is constituted of structure.
Semiconductor channel layer 107 can be by the N-shaped polysilicon doped with phosphorus or arsenic, or N-shaped epitaxial monocrystalline silicon
Constituted.Additionally, semiconductor channel layer 107 can also be by the p-type doped with boron, or p
Type epitaxial monocrystalline silicon is constituted.
In the present embodiment, the semiconductor channel layer 107 of patterning is made up of N-shaped polysilicon,
And the semiconductor channel layer 107 of patterning at least includes two parts separated from one another.A portion
Semiconductor channel layer 107 be covered in adjacent carinate lamination 104A and 104B and for isolating
The bottom of the raceway groove 105 of carinate lamination 104A and 104B.Use respectively in carinate lamination 104A and
A U film is formed between 104B, carinate lamination 104A and 104B is formed at for concatenating
On multiple memory cell 108, and then formed the first serial 109A of U-shaped memory cell.Another portion
Point semiconductor channel layer 107 be covered in adjacent carinate lamination 104C and 104C and for isolating
The bottom of the raceway groove 105 of carinate lamination 104C and 104D.And in carinate lamination 104C and 104D
Between form another U film, be formed at carinate lamination 104C and 104D for concatenating
On multiple memory cell 108, and then formed the second serial 109B of U-shaped memory cell.
Wherein, positioned at the memory cell at the top of carinate lamination 104A, can be deposited as the first U-shaped
The first ground connection selection wiretap 110A of the serial 109A of storage unit；Positioned at the top of carinate lamination 104B
The memory cell in portion, can open as the first of the first serial 109A of U-shaped memory cell the serial selection
Close 111A.Positioned at the memory cell at the top of carinate lamination 104C, can be stored as the second U-shaped
The second ground connection selection wiretap 110B of the serial 109B of unit；Positioned at the top of carinate lamination 104D
Memory cell, can be as the second serial selecting switch of the second serial 109B of U-shaped memory cell
111B。
Although it is otherwise noted that Fig. 1 C only illustrate by four carinate laminations (carinate lamination 104A,
104B, 104C and 104D) serial (the first U-shaped memory cell of two U-shaped memory cell being formed
Serial 109A and the second serial 109B of U-shaped memory cell).But for the sake of it is merely to clearly describe
And illustrate, it is not limited to the present invention.Among some embodiments of the present invention, single gate vertical
Passage nand memory element 100 can include that more carinate laminations and more U-shapeds are deposited
Storage unit is serial, and then forms a solid storing cell array.
Afterwards, dielectric material layer 112 is filled in raceway groove 105.In some embodiments of the invention,
The material for forming dielectric material layer 112 can include silica, silicon nitride, silicon oxynitride, Gao Jie
Any combination of electrostrictive coefficient (high-k) material or above-mentioned material.In the present embodiment, preferably also it is included in
In raceway groove 105 formed the air gap (air gap) 113, for reduce positioned at different carinate lamination 104A,
The interference each other of memory cell 108 on the wall of 104B, 104C and 104D side.
Subsequently as depicted in Fig. 1 D, at the top of carinate lamination 104A, 104B, 104C and 104D
Contact plunger (contact plug) 114 is formed, the first serial selection line is switched 111A and second respectively
Serial selection line switch 111B is connected to a bit line 115；And forming contact plunger 116 makes first to connect
The ground ground connection selection wiretaps of selection wiretap 110A and second 110B passes through plain conductor 117 respectively
It is connected to a common source line 118.And form stair-stepping in the Zhou Bianqu of solid storing cell array
Multiple word line contact structures (for example, the 119B depicted in Fig. 1 D), make be located at carinate lamination 104A,
For the conductive strips of forming layer memory cell 108 in the identical stratum of 104B, 104C and 104D
104A1-D1,104A2-D2,104A3-D3,104A4-D4,104A5-D5 and 104A6-D6,
It is respectively connecting to different wordline 120.
Word line contact structure, such as word line contact structure 119A, 119B and 119C, detailed configuration
Fig. 2 is refer to, Fig. 2 is single gate vertical passage nand memory element according to depicted in 1D
100 partial structurtes top view.Word line contact structure 119A, 119B and 119C are to be arranged respectively at
The major axis both sides of carinate lamination 104A, 104B, 104C and 104D.In the present embodiment, wordline
Contact structures 119A comprising stepped lamination multiple contact layers, be respectively intended to positioned at carinate lamination
The conductive strips contact of different estate in 104B；Word line contact structure 119B includes stepped lamination
Multiple contact layers, are respectively intended to be contacted with the conductive strips of the different estate in carinate lamination 104D.
Multiple contact layers of the word line contact structure 119C comprising stepped lamination, are respectively intended to and carinate lamination
Conductive strips in 104A and 104C positioned at identical stratum are contacted.
In other words, the conductive strips of same level layer are located in carinate lamination 104A and 104C,
Share a word line contact structure 119C.In detail, the is located in carinate lamination 104A and 104C
The conductive strips 104A1 and 104C1 of one plane layer, with stepped word line contact structure 119C
One contact layer (not illustrating) is contacted；Positioned at the conductive strips 104A2 and 104C2 of the second plane layer, with
Stepped word line contact structure 119C obtains the second contact layer (not illustrating) contact；Positioned at the 3rd plane layer
Conductive strips 104A3 and 104C3, with the 3rd contact layer of stepped word line contact structure 119C (not
Illustrate) contact；Positioned at the conductive strips 104A4 and 104C4 of fourth plane layer, with stepped wordline
4th contact (not illustrating) layer contact of contact structures 119C；Positioned at the conductive strips of the 5th plane layer
104A5 and 104C5, the 5th contact layer (not illustrating) with stepped word line contact structure 119C is contacted；
And positioned at the conductive strips 104A6 and 104C6 of the 6th plane layer, with stepped word line contact structure
6th contact layer (not illustrating) contact of 119C.Because word line contact structure has been, it is known that therefore its is detailed
Construction do not repeated herein with preparation method.
But the configuration mode of word line contact structure is not limited thereto, in some embodiments of the invention,
Leading below the serial selection line switch during different U-shaped memory cell are serial more than more than two
Electric band, can respectively from different word line contact structures；Different U-shapeds are deposited more than this more than two
The conductive strips below ground connection selection wiretap during storage unit is serial can share a word line contact knot
Structure.
Among some embodiments of the present invention, single gate vertical passage nand memory element 100
Also include multiple serial selection line engagement pads 121 and 122 points shared of a ground connection selection line engagement pad
Yong Lai not be by serial selection line switch (for example, the first serial selection line switch 111A and second is serially selected
Select wiretap 111B) and selecting switch is grounded (for example, the first ground connection selection wiretap 110A and second
Ground connection selection wiretap 110B) it is connected to decoder (not illustrating).For example in the present embodiment, it is each
Individual serial selection line engagement pad 121 is located at respectively, and there is the first serial selection line to switch 111A and second
One end of the carinate lamination 104B and 104D of serial selection line switch 111B, adjacent word line contact knot
Structure 119A and 119B, and with for forming the first serial selection line switch 111A and second serial
Conductive strips 104B6 and the 104D6 contact of selection wiretap 111B.Shared ground connection selection line connects
Touch pad 122 is then located at has the first ground connection ground connection selection wiretaps of selection wiretap 110A and second
One end of the carinate lamination 104A and 104C of 110B, adjacent word line contact structure 119C, and with
For forming the conductive bar of the first ground connection ground connection selection wiretaps of selection wiretap 110A and second 110B
Band 104A6 and 104C6 is contacted.
The shape of the word line contact structure 119C being shared can be with single gate vertical passage NAND
The design of memory component and it is different.Fig. 3 is for example refer to, Fig. 3 is of the invention another
In the partial structurtes of the single gate vertical passage nand memory element 300 depicted in one embodiment
View.The structure of single gate vertical passage nand memory element 300 substantially with single gate vertical
Passage nand memory element 100 is identical, and difference is only that, adjacent ground connection selection line engagement pad
The shape of 122 word line contact structure 319C is different.Among the present embodiment, by positioned at carinate folded
The first ground connection ground connection selection wiretaps of selection wiretap 110A and second 110B of layer 104A and 104C
The word line contact structure 319C that the conductive strips 104A6 and 104C6 of lower section share, can configure
Into longitudinal hierarchic structure.Further save single gate vertical passage nand memory element 300
Transverse width.
In order to prevent the different serial 109A of U-shaped memory cell with shared word line contact structures 119C
Signal is produced to disturb in write operation, read operation and erasing operation with 109B, of the invention
Among some embodiments, single gate vertical passage nand memory element 100 can include one
Positioned at the first serial selection line ground connection choosings of switch 111A and first of the serial 109A of U-shaped memory cell
The first controlling switch IG_1A between wiretap 110A is selected, and one is located at U-shaped memory cell
Between the second serial selection line ground connection selection wiretaps of switch 111B and second 110B of serial 109B
The second controlling switch IG_1B.
Fig. 4 is for example refer to, Fig. 4 is to illustrate to be stored with single gate vertical passage NAND of Fig. 1 C
Device element 100 carries out equivalent circuit diagram during write operation.In the present embodiment, the first controlling switch
IG_1A can include a kind of complementary switching circuit (complementary switch circuit) 123 with
The bottom conductive band 104B1 connections of ridge folding layer 104B, are used to control to be located at ridge folding layer 104B
The keying of the memory cell 108 of bottom.Second controlling switch IG_1B be located at ridge folding layer 104D
Bottom conductive band 104D1 connections, be used to control be located at the storage list of ridge folding layer 104D bottoms
The keying of unit 108.Because the structure of the second controlling switch IG_1B can be with the first controlling switch
IG_1A is identical, therefore the structure of the second controlling switch IG_1B is no longer illustrated in Fig. 4.But at other
In embodiment, the structure of the second controlling switch IG_1B still can be with the first controlling switch 1G_1A not
Together.
In addition in some preferred embodiments, single gate vertical passage nand memory element 100
Can also include one be located at first ground connection selection wiretap 110A and the first controlling switch IG_1A it
Between the first auxiliary switch IG_0A, and one be located at the second ground connection selection wiretap 110B and the
The second auxiliary switch IG_0B between two controlling switch IG_1B.Likewise, the first auxiliary switch
The structure of IG_0A and the second auxiliary switch IG_0B can it is identical with the first controlling switch IG_1A or
It is different.
In the present embodiment, the first auxiliary switch IG_0A is the bottom conductive with ridge folding layer 104A
Band 104A1 is connected, and is used to control opening for the memory cell 108 for being located at ridge folding layer 104A bottoms
Close；Second auxiliary switch IG_0B is connected with the conductive strips 104C1 of ridge folding layer 104C bottoms,
It is used to control the keying of the memory cell 108 positioned at ridge folding layer 104C bottoms.
In the first serial 109A of U-shaped memory cell is selected with the first serial selecting switch 111A
When memory cell 108P carries out write operation, the first serial selection line switch 111A, first can be opened
Controlling switch IG_1A and the first auxiliary switch IG_0A；And close the first ground connection selection wiretap 110A.
The first serial selection line switch 111A and first is connect simultaneously with bit line 115 and common source line 118
Ground selection wiretap 110A applies 0 volt of voltage (0V)；Storage is selected by wordline 120 pairs again single
First 108P applies grid write-in voltage Vpgm；And to be pointed to the first U-shaped memory cell serial
Other memory cell 108 on 109A apply a grid and pass through voltage Vpass.Wherein, grid write-in
Voltage Vpgm, by voltage Vpass, uses initiation electronics e- and produces more than grid
Fowler-Nordheim tunneling effects, write data among memory cell 108P.
The non-selected serial 109B of second U-shaped memory cell makes to be located at when write operation is carried out
The grid of the second serial selection line switch 111B and memory cell below on carinate lamination 104D
Keep floating (floating).Because the conductive strips in carinate lamination 104A and 104C share a word
Contact structure 119C；And first ground connection selection wiretap 110A and second ground connection selection wiretap
110B also shares ground connection selection line engagement pad 122.Therefore, it is applied on carinate lamination 104C
Two ground connection selection wiretap 110B and memory cell below 108 (including memory cell 108P')
Grid voltage, meeting and the first ground connection selection wiretap 110A being applied on carinate lamination 104A
And the grid voltage of memory cell 108 (including memory cell 108P) below is identical.Close
The second controlling switch IG_1B is closed, the 104C shapes in the second serial 109B of U-shaped memory cell can be made
Into local self current potential lifting (local self-boosting) to maintain enough current potentials, prevent positioned at carinate
Memory cell 108P' on lamination 104C is influenceed and is written into by write-in voltage Vpgm.
Fig. 5 is refer to, Fig. 5 is illustrated with single gate vertical passage nand memory unit of Fig. 1 C
Equivalent circuit diagram when part 100 is read.In the present embodiment, when with the first serial selection
Memory cell 108R of the wiretap 111A selections on the first serial 109A of U-shaped memory cell enters
During row read operation, the first serial selection line switch 111A, the first ground connection selection wiretap can be opened
110A, the first controlling switch IG_1A and the first auxiliary switch IG_0A.Make bit line 115 and common
Source electrode line 118 switchs the ground connection selection wiretaps of 111A and first 110A to the first serial selection line simultaneously
Apply 1 volt (1V) and 0 volt of voltage (0V) respectively；The storage list being selected by wordline 120 pairs again
First 108R applies a grid read voltage Vref；And to be pointed to the first U-shaped memory cell serial
Other memory cell 108 on 109A apply a grid and pass through voltage Vpass.Can be by being selected
Data are read in memory cell 108R.
The non-selected serial 109B of second U-shaped memory cell when being read, positioned at ridge
The second serial selection line switch 111B and the grid of memory cell below 108 on shape lamination 104D
Keep floating.Because the conductive strips in carinate lamination 104A and 104C share a word line contact
Structure 119C；And the first ground connection ground connection selections of the selection wiretap 110A and second wiretap 110B
Shared ground connection selection line engagement pad 122.Therefore, it is applied to the second ground connection on carinate lamination 104C
The grid of selection wiretap 110B and memory cell below 108 (including memory cell 108R')
Voltage, meeting and be applied on carinate lamination 104A first ground connection selection wiretap 110A and its
The grid voltage of the memory cell 108 (including memory cell 108R) of lower section is identical.Close second
Controlling switch IG_1B, and make the second serial selection in the second serial 109B of U-shaped memory cell
The grid of wiretap 111B and memory cell below 108 keeps floating, can prevent unselected
The second serial 109B of U-shaped memory cell in memory cell 108R' by grid read voltage Vref
Read.
Fig. 6 is refer to, Fig. 6 is illustrated with single gate vertical passage nand memory unit of Fig. 1 C
Part 100 carries out equivalent circuit diagram during erasing operation.In the present embodiment, when the first U-shaped of selection is deposited
When the serial 109A of storage unit carries out erasing operation, can be to the first serial selection line switch 111A, first
The grid of controlling switch IG_1A and the first auxiliary switch IG_0A applies 7 volts of voltages (7V), uses
It is turned on；Apply 0 volt of voltage with 118 couples first ground connection selection wiretap 110A of common source line
(0V), selects the grid of wiretap 110A to keep floating first ground connection；First is pointed to U-shaped to deposit
The grid of all memory cell 108 on the serial 109A of storage unit applies 0 volt of voltage (0V)；Again with
115 couples of the first serial selection line switch 111A of bit line apply 20 volts of erasing voltages of (20V).By
So that the memory cell 108 on the first U-shaped serial 109A of memory cell produces gate induced leakage
Pole leakage current (Gated-Induce Drain Leakage, GIDL) GIDL.
The non-selected serial 109B of second U-shaped memory cell when erasing operation is carried out, positioned at ridge
On shape lamination 104D the second serial selection line switch 111B and memory cell below 108 and
The grid of the ground connection selecting switch of the second controlling switch IG_1B and second 110B all keeps floating.Due to
Conductive strips in carinate lamination 104A and 104C share a word line contact structure 119C；And the
The one ground connection ground connection selection wiretaps of selection wiretap 110A and second 110B also shares ground connection selection line and connects
Touch pad 122.Therefore, be applied on carinate lamination 104C second ground connection selection wiretap 110B with
And the grid voltage of memory cell 108 below, meeting and be applied on carinate lamination 104A
The grid voltage of one ground connection selection wiretap 110A and memory cell below 108 is identical.
Make the second serial selection line switch 111B and the memory cell below that are located on carinate lamination 104D
108 and second the grid of controlling switch IG_1B all keep floating, the erasing time can be postponed, prevent
Memory cell 108 in the second serial 109B of U-shaped memory cell is wiped free of within erasing time nanosecond.
According to above-described embodiment, this specification is to provide a kind of three-dimensional storage with multiple carinate laminations
Device element, the carinate lamination of each of which is included, respectively with a serial selection line positioned at top
Switch or a ground connection select wiretap and are switched positioned at serial selection line or ground connection selection wiretap
Multiple memory cell of lower section.Opened by first serial selection line of the concatenation on two carinate laminations
Close and the first ground connection selection wiretap, and positioned at the first serial selection line switch and the first ground connection selection
Memory cell below wiretap is serial to form the first U-shaped memory cell；It is located at by concatenation simultaneously
The second serial selection line switch and the second ground connection selection wiretap on two other different carinate lamination,
And the memory cell below the second serial selection line switch and the second ground connection selection wiretap is come
Form the second U-shaped memory cell serial.
Wherein, the storage below serial the first serial selection line switch of the first U-shaped memory cell
Unit is connected with the first word line contact structure；Positioned at the second serial choosing that the second U-shaped memory cell is serial
The memory cell below wiretap is selected to be connected with the second word line contact structure；And it is located at the storage of the first U-shaped
Unit it is serial first ground connection selection wiretap below memory cell and positioned at the second U-shaped storage
Memory cell below the second serial ground connection selection wiretap of unit, then be connected to the word of identical the 3rd
Contact structure.In other words, in three-dimensional storage element, for connecting positioned at ground connection selecting switch
The word line contact number of structures of the memory cell of lower section is less than and is used for connecting under serial selecting switch
The word line contact structure of the memory cell of side.If compared with the three-dimensional storage element in prior art,
On the premise of memory capacity is not changed, it is possible to reduce the setting of word line contact structure.
By the setting for reducing word line contact structure, it is possible to reduce the area size of memory component；More
Can be on the premise of process margin not be influenceed, the memory capacity of extended menory element is greatly reduced work
Skill cost, and prevent oxide punch from producing, the technique for increasing vertical channel memory component is good
Rate.
Claims (10)
1. a kind of three-dimensional (Three Dimemsional, 3D) memory component, including：
One multi-layer laminate structure (multi-layer stacks), including the multiple conductive strips being isolated from each other
(conductive strips) and a plurality of raceway groove (trench), at least to define one first carinate lamination
(ridge stacks), one second carinate lamination, one the 3rd carinate lamination and one the 4th carinate lamination；
One first serial selection line (String Selection Line, SSL) is switched, first carinate positioned at this
On lamination；
One first ground connection selection line (Ground Selection Line, GSL) switch, positioned at second ridge
On shape lamination；
One first U-shaped memory cell is serial (U-shaped cell string), concatenates the first serial selection
Wiretap and the first ground connection selection wiretap；
One second serial selection line is switched, on the 3rd carinate lamination；
One second ground connection selection wiretap, on the 4th carinate lamination；
One second U-shaped memory cell is serial, concatenates second serial selection line switch and second ground connection
Selection wiretap；
One first word line contact structure, contacts with these conductive strips on the first carinate lamination；
One second word line contact structure, contacts with these conductive strips on the second carinate lamination；
And
One the 3rd word line contact structure, and on the 3rd carinate lamination and the 4th carinate lamination
These conductive strips are contacted.
2. three-dimensional storage element according to claim 1, further includes
One first serial selection line engagement pad, with the top conductive band positioned at the first ridge folding layer
Contact；
One second serial selection line engagement pad, with the top conductive band positioned at the 3rd ridge folding layer
Contact；And
One ground connection selection line engagement pad, and positioned at the two of the second ridge folding layer and the four ridge foldings be somebody's turn to do layer
Top conductive ribbon contacts.
3. three-dimensional storage element according to claim 1, further includes：
One memory material layer, on multiple side walls of these raceway grooves；
One patterning channel membrane, is covered on multiple bottoms of memory material layer and these raceway grooves；
And
Multiple memory cell, are formed at memory material layer and the patterning channel membrane and these conductive bars
With multiple positions (cross point) that three overlaps.
4. three-dimensional storage element according to claim 3, wherein：
The first U-shaped memory cell be serially by a part of patterning channel membrane concatenate this first
Serial selection line switch, these storages on the first carinate lamination and the second carinate lamination are single
Unit and the first ground connection selection wiretap are formed；And
The second U-shaped memory cell be serially by another part patterning channel membrane concatenate this
Two serial selection lines switch, these storages on the 3rd carinate lamination and the 4th carinate lamination
Unit and the second ground connection selection wiretap are formed.
5. three-dimensional storage element according to claim 3, further includes：
One first controlling switch, opens positioned at first serial selection line switch and the first ground connection selection line
Between pass；And
One second controlling switch, opens positioned at second serial selection line switch and the second ground connection selection line
Between pass.
6. three-dimensional storage element according to claim 5, wherein：
First controlling switch is connected with a bottom conductive band of the first ridge folding layer；And
Second controlling switch is connected with a bottom conductive band of the 3rd ridge folding layer.
7. three-dimensional storage element according to claim 6, further includes：
One first auxiliary switch, between first controlling switch and the first ground connection selection wiretap；
And
One second auxiliary switch, between second controlling switch and the second ground connection selection wiretap.
8. three-dimensional storage element according to claim 7, wherein：
The one bottom conductive ribbon contacts of first auxiliary switch and the second ridge folding layer；And
The one bottom conductive ribbon contacts of second auxiliary switch and the 4th ridge folding layer.
9. three-dimensional storage element according to claim 5, wherein when selecting first U-shaped
When memory cell string row carries out a write operation (program operation), the write operation includes：
Open first serial selection line switch and first controlling switch；
Close the first ground connection selection wiretap, second ground connection selection wiretap and second controlling switch；
And
Be pointed to the first U-shaped memory cell it is serial on the one of these memory cell apply one to write
Enter voltage (Vpgm)；And
Be pointed to the first U-shaped memory cell it is serial on other these memory cell apply one to pass through
Voltage (Vpass), wherein the write-in voltage are more than the conducting voltage.
10. three-dimensional storage element according to claim 9, wherein carrying out the write operation
When, a grid of second serial selection line switch is to maintain floating (floating).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510929883.9A CN106887434B (en) | 2015-12-15 | 2015-12-15 | Three-dimensional storage element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510929883.9A CN106887434B (en) | 2015-12-15 | 2015-12-15 | Three-dimensional storage element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106887434A true CN106887434A (en) | 2017-06-23 |
| CN106887434B CN106887434B (en) | 2019-07-05 |
Family
ID=59173465
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510929883.9A Active CN106887434B (en) | 2015-12-15 | 2015-12-15 | Three-dimensional storage element |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106887434B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110911410A (en) * | 2018-09-17 | 2020-03-24 | 旺宏电子股份有限公司 | Memory device and method of manufacturing the same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194821A (en) * | 2010-01-25 | 2011-09-21 | 旺宏电子股份有限公司 | Three-dimensional storing array with improved serial selection line and bit line contact distribution |
| CN102800361A (en) * | 2011-05-24 | 2012-11-28 | 爱思开海力士有限公司 | 3-dimensional non-volatile memory device and method of manufacturing the same |
| US20150069499A1 (en) * | 2013-09-10 | 2015-03-12 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method for manufacturing same |
| CN105097817A (en) * | 2014-05-23 | 2015-11-25 | 爱思开海力士有限公司 | Three-dimensional nonvolatile memory device, semiconductor system including the same, and method of manufacturing the same |
-
2015
- 2015-12-15 CN CN201510929883.9A patent/CN106887434B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194821A (en) * | 2010-01-25 | 2011-09-21 | 旺宏电子股份有限公司 | Three-dimensional storing array with improved serial selection line and bit line contact distribution |
| CN102800361A (en) * | 2011-05-24 | 2012-11-28 | 爱思开海力士有限公司 | 3-dimensional non-volatile memory device and method of manufacturing the same |
| US20150069499A1 (en) * | 2013-09-10 | 2015-03-12 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method for manufacturing same |
| CN105097817A (en) * | 2014-05-23 | 2015-11-25 | 爱思开海力士有限公司 | Three-dimensional nonvolatile memory device, semiconductor system including the same, and method of manufacturing the same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110911410A (en) * | 2018-09-17 | 2020-03-24 | 旺宏电子股份有限公司 | Memory device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106887434B (en) | 2019-07-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI611607B (en) | Three dimensional memory device | |
| KR101982383B1 (en) | 3d non-volatile storage with wide band gap transistor decoder | |
| US9214471B2 (en) | Memory architecture of 3D array with diode in memory string | |
| US8503213B2 (en) | Memory architecture of 3D array with alternating memory string orientation and string select structures | |
| TWI582964B (en) | A memory device and method for fabricating the same | |
| US9524980B2 (en) | U-shaped vertical thin-channel memory | |
| CN101826545B (en) | Integrated circuit self aligned 3d memory array and manufacturing method | |
| US9190157B2 (en) | Semiconductor device including memory cell having charge accumulation layer | |
| EP3262690B1 (en) | Memory cell with high-k charge trapping layer | |
| KR101961982B1 (en) | Thin film transistor | |
| US7781807B2 (en) | Non-volatile semiconductor storage device | |
| JP5977003B2 (en) | Three-dimensional array memory architecture with diodes in memory string | |
| CN103035650B (en) | Semiconductor device and manufacturing method of semiconductor device | |
| CN100334734C (en) | Semiconductor storage unit and semiconductor memory | |
| US9443910B1 (en) | Silicided bit line for reversible-resistivity memory | |
| US9698154B2 (en) | Semiconductor device | |
| CN103915117A (en) | P-channel 3d memory array | |
| US9368510B1 (en) | Method of forming memory cell with high-k charge trapping layer | |
| TWI462116B (en) | 3d memory array with improved ssl and bl contact layout | |
| JP2013016781A (en) | Memory architecture of 3d array with diode in memory string | |
| TW201608567A (en) | 3D NAND nonvolatile memory with staggered vertical gates | |
| US20160111517A1 (en) | Dual gate structure | |
| TW201639130A (en) | Non-volatile semiconductor memory device | |
| CN107039443A (en) | Memory component and preparation method thereof | |
| CN110323227A (en) | Low resistance vertical channel three-dimensional storage element |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |