CN106887253A

CN106887253A - A kind of method that use testing needle card carries out DRAM wafer sorts

Info

Publication number: CN106887253A
Application number: CN201710018478.0A
Authority: CN
Inventors: 王帆; 黄华
Original assignee: Xian Unilc Semiconductors Co Ltd
Current assignee: Xian Unilc Semiconductors Co Ltd
Priority date: 2017-01-10
Filing date: 2017-01-10
Publication date: 2017-06-23
Anticipated expiration: 2037-01-10
Also published as: CN106887253B

Abstract

The present invention proposes a kind of method that use testing needle card carries out DRAM wafer sorts, it is to avoid due to the volume production lag issues that testing needle card is caused extremely, and reduce the cost of volume production simultaneously.Testing scheme of the invention is comprised the following steps：1) wafer rises and surveys；2) determine to need crucial probe to be protected in testing needle card, the test item about the crucial probe is individually carried out successively；If a certain test item does not pass through, corresponding chip failing power supply is turned off, next test item then is proceeded to other chips, until completing all of test item；3) functional test, that is, perform the various functions test item of DRAM；4) test terminates.

Description

A kind of method that use testing needle card carries out DRAM wafer sorts

Technical field

The present invention relates to a kind of method that use testing needle card carries out DRAM wafer sorts.

Background technology

DRAM have in test process reduce testing cost demand, therefore testing needle card same survey number more and more higher, with And the manufacturing cost of testing needle card and maintenance cost that cause also accordingly increase.By taking the testing needle card of 256 chip simultaneous tests as an example, One price of pin card is 200,000 U.S. dollars, and a maintenance cost for test probe is 1000 U.S. dollars.

Traditional DRAM crystal round test approach is as shown in figure 1, three steps of test point are performed：

Step 1：Wafer rises to be surveyed；

Step 2：Functional test, that is, perform the various functions test item of DRAM；

Step 3：Test terminates.

The protection of testing needle card probe is not accounted in traditional DRAM wafer sorts.According to above testing process, when When test exception occurs, easily cause to test the damage of probe, the damage of probe will further result in the delayed and core of volume production The lifting of piece cost.

The content of the invention

The present invention is improved the flow that traditional use testing needle card carries out DRAM wafer sorts, is proposed a kind of new Method of testing, can as far as possible avoid chip volume production delayed at the same reduce chip cost.

Testing scheme of the invention is as follows：

Step 1：Wafer rises to be surveyed；

Step 2：Determine to need crucial probe to be protected in testing needle card, the relevant crucial probe is individually carried out successively Test item；If a certain test item does not pass through, corresponding chip failing power supply is turned off, then other chips are proceeded next Test item, until completing all of test item；

Step 3：Functional test, that is, perform the various functions test item of DRAM；

Step 4：Test terminates.

At present, the crucial probe of DRAM volume productions testing needle card mainly has two classes, i.e. power probe (VDD and GND) and control The probe of coremaking piece characteristic voltage (VPP, VNWLL etc.), because this two classes probe is in test process, has high voltage or big electricity That flows flows through, therefore can not be shared between this two classes probe chip, protects this two classes probe critically important.

So, it usually needs the crucial probe of protection includes the probe of power probe and control chip characteristic voltage；It is relevant The test item of crucial probe includes successively：IDD1 tests under VDD and GND short-circuit tests, VDD current-clamps, characteristic voltage are high DC tests under voltage.

Beneficial effects of the present invention are as follows：

It is effectively protected the crucial probe of DRAM testing needle cards, it is to avoid because the volume production that testing needle card is caused extremely is stagnant Problem afterwards, and the cost of volume production is reduced simultaneously.

Brief description of the drawings

Fig. 1 is the flow chart of traditional DRAM wafer sorts.

Fig. 2 is the testing needle card and chip connection diagram of 4 chip simultaneous tests.

Fig. 3 is the flow chart of the DRAM wafer sorts of the present embodiment.

Specific embodiment

As shown in figure 3, the DRAM wafer sorts of the present embodiment are divided into six steps：

Step 1：Wafer rises to be surveyed；

Step 2-4：Three groups of test items, protect the crucial probe of testing needle card；

Step 5：Functional test, that is, perform the various functions test item of DRAM；

Step 6：Test terminates.

Compared with traditional DRAM wafer sort flow charts, step 2-4 is newly-increased testing process, i.e., wafer rise survey with Between functional test, three groups of test items are added, and after each group of test item is finished, test result can be carried out Judge, only testing the chip for passing through could enter ensuing testing process, and the chip of failure can turn off tester table to surveying The power supply of test point card, to reach the purpose of protection testing needle card key probe.This three groups of test items are：

First group：VDD and GND short-circuit tests；

Second group：IDD1 tests under VDD current-clamps；

3rd group：DC tests under characteristic voltage high voltage.

Below, the new three groups of test items for adding and control method are described in detail respectively.

First group of test item is VDD and GND short-circuit tests, it is therefore an objective to protect the power probe VDD and GND of pin card.

Power supply (VDD and GND) probe of pin card is responsible for the power supply and ground of connecting test board and DRAM, is to ensure DRAM works The most basic probe made.Wafer acts first test item after surveying during VDD and GND short-circuit tests, in the test item, we Will be exploratory plus VDD, i.e., can not by chip normal work when required VDD be applied directly on the VDD probes of pin card, in case Once only chip has the short circuit of VDD and GND, then high current is directly flowed on GND by VDD, VDD and GND probes are damaged Bad risk.By taking DDR3 chips as an example, the VDD of normal work is 1.5V, then detecting VDD whether short circuit test item in, We will add the voltage of 0.3V on VDD, and measure the electric current on VDD probes, if VDD and GND are without short circuit phenomenon, then Current value on VDD probes in ten microamperes of magnitudes, if VDD and GND have short circuit phenomenon, then the current value meeting on VDD probes In hundred microamperes of magnitudes.For hundred microamperes of chips of measured value, we will turn off tester table to pin in whole testing process The power supply of the VDD of card, to reach the purpose of protection VDD and GND.

Second group of test item is the IDD1 tests under VDD current-clamps, and the test item can be visited with further protection VDD Pin.IDD1 is the electric current under dram chip normal operating conditions, by taking DDR3 chips as an example, it is generally the case that the electric current of IDD1 exists 30mA or so.For the test item, we can carry out double control to protect pin card.First controls again, for the actual measurement of IDD1 Value is judged that if, when IDD1 is more than 50mA, the function of usual chip or follow-up reliability also can be abnormal, this part core Piece need not be encapsulated.Therefore when IDD1 is more than 50mA, by shut-off tester table to the power supply on chip VDD, it is ensured that chip exists Abnormal operation is not in ensuing functional test, VDD or even the institute being connected with the chip is further ensured that There is probe；Second is controlled again, and current-clamp is carried out for VDD.IDD1 abnormal chip, although measuring value may only have 50mA, But the transient state IDD1 at some time points there is a possibility that hundred microamperes of magnitudes, and it is have that testing needle card VDD in itself bears electric current The upper limit, if it exceeds the upper limit, will not find the exception of VDD probes in the short time, but with the increase of wafer sort amount, Cumulative effect on VDD gradually substantially can finally influence volume production, therefore, when IDD1 is measured, must be according to the design of pin card Specification carries out current-clamp.For example, the upper current limit on the design specification requirement VDD probes of pin card is 300mA, then, surveying During amount IDD1, we can give the current-clamp of +/- 250mA, be further ensured that the safety of VDD probes.

3rd group of test item is the DC tests under characteristic voltage high voltage, it is therefore an objective to protect the characteristic voltage of testing needle card to visit Pin.

In DRAM wafer-level tests, the characteristic voltage of chip can be connected by probe with tester table, reach flexibly control The purpose of test condition processed.When in certain functional test, when the characteristic voltage of such as fruit chip has the demand that high voltage is input into, then The protection of probe must be carried out.Assuming that in One function test item, certain characteristic voltage needs high voltage to be input into, then can be at this Before functional test is performed, introduce testing time very short DC test items, the DC test items using and functional test phase Same control source condition, under this condition, measures the current value on characteristic voltage probe, if the current value mistake of some chips Greatly, then these chip operation exceptions, not only by the functional test of same condition, and also can not have the characteristic that damage is attached thereto The risk of probe, it is therefore necessary to cut off the power supply of these chips, in the prolonged functional test of ensuing same condition Xiang Zhong, these chips are not worked, and the characteristic probe being connected with these chips can just be protected.For example, in On-Wafer Measurement, meeting There is the burn-in test of wafer scale, these test items need prolonged high voltage VPP, and (DDR3 chips VPP is 2.85V, always Changing test item VPP need to add 4V, and the burn-in test time is in the magnitude of minute), then can be held in these burn-in tests Before row, a DC test item (testing time of DC test items is a millisecond magnitude) for 4V vpp voltages input is introduced, measure VPP and visit Electric current on pin, within 20mA, the risk that VPP probes are not damaged, these chips can proceed for a long time current value Burn-in test；Chip of the current value more than 20mA, if carrying out prolonged burn-in test, the VPP probe quilts of these chips The dangerous of damage, it is therefore necessary to these chips are carried out with power down process, and then reaches the mesh of protection these chips VPP probes 's.

Claims

1. a kind of method that use testing needle card carries out DRAM wafer sorts, including

Step 1：Wafer rises to be surveyed；

Step 2：Determine to need crucial probe to be protected in testing needle card, the test about the crucial probe is individually carried out successively ；If a certain test item does not pass through, corresponding chip failing power supply is turned off, next test then is proceeded to other chips , until completing all of test item；

Step 4：Test terminates.

2. the method that use testing needle card according to claim 1 carries out DRAM wafer sorts, it is characterised in that：The need Crucial probe to be protected includes the probe of power probe and control chip characteristic voltage；About crucial probe test item successively Including：The DC tests under IDD1 tests, characteristic voltage high voltage under VDD and GND short-circuit tests, VDD current-clamps.