CN106877636A - A kind of phase shift suppresses harmonic circuit - Google Patents
A kind of phase shift suppresses harmonic circuit Download PDFInfo
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- CN106877636A CN106877636A CN201710193215.3A CN201710193215A CN106877636A CN 106877636 A CN106877636 A CN 106877636A CN 201710193215 A CN201710193215 A CN 201710193215A CN 106877636 A CN106877636 A CN 106877636A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/12—Arrangements for reducing harmonics from ac input or output
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
- Y02E40/40—Arrangements for reducing harmonics
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Abstract
Suppress harmonic circuit the present invention relates to circuit design field, more particularly to a kind of phase shift, including：Carrier signal input, the first signal output part, secondary signal output end, the first integrated chip, the second integrated chip, the 3rd integrated chip, the first NAND gate circuit, the second NAND gate circuit, the 3rd NAND gate circuit, electric capacity, resistance and power supply；Using circuit of the present invention come phase shift, phase shifting angle is unrelated with circuit components value, therefore, it is readily available high-precision phase shifting angle.The phase shift that the present invention is provided suppresses the primary condition that harmonic circuit meets phase shift harmonic carcellation.Signal feeding excitation amplifying circuit drives the left and right bridge arm of H bridge power amplifiers respectively after amplifying, complete phase shift harmonic carcellation.Through actual test, output harmonic wave suppresses about to improve 7dB, and the harmonic emissions of whole machine reach the requirement of GJB151A, it was demonstrated that can effectively improve the harmonics restraint ratio of radio frequency output.
Description
Technical field
Suppress harmonic circuit the present invention relates to circuit design field, more particularly to a kind of phase shift.
Background technology
It is widely used in modern radio communication equipment to switch amplifying technique to improve the efficiency of whole machine, due to amplifying circuit
In switch magnifying state, its output is a powerful radio frequency square-wave signal, contains abundant harmonic component, usual nothing
Line electricity emitter is all to filter harmonic wave by exporting network to reach whole machine harmonics restraint index request.
The application of present each class of electronic devices so that electromagnetic environment becomes very complicated, in order to control electromagnetic environment, each national capital
Corresponding EMC Standard is worked out, the electromagnetic radiation index of each electronic product has been made that and is distinctly claimed.Wireless
To make harmonic wave and spurious reduction reach electromagnetic compatibility standard requirement in electric emitter just to propose the filtering characteristic of output network
Requirements at the higher level, it is well known that the filtering performance of output network is higher, and its efficiency of transmission is poorer.
Whether there can be method to obtain harmonic wave high rather than output network filtering performance is improved by the improvement to circuit
Rejection ratio, so that radio transmitter reaches requirement of all kinds of electromagnetic compatibility standards to electromagnetic radiation index.
The content of the invention
The technical problems to be solved by the invention are：There is provided a kind of harmonics restraint that can improve radio transmitter than
Phase shift suppresses harmonic circuit.
In order to solve the above-mentioned technical problem, the technical solution adopted by the present invention is：
A kind of phase shift suppresses harmonic circuit, including：Carrier signal input, the first signal output part, secondary signal output
End, the first integrated chip, the second integrated chip, the 3rd integrated chip, the first NAND gate circuit, the second NAND gate circuit, the 3rd
NAND gate circuit, electric capacity, resistance and power supply；
Carrier signal input output end respectively with radio transmitter, the first integrated chip and the first NAND gate
Circuit is electrically connected；
First integrated chip respectively with the first NAND gate circuit, the second integrated chip, the 3rd integrated chip, electric capacity
One end electrical connection of one end and resistance；
First NAND gate circuit is electrically connected with the second integrated chip and the 3rd NAND gate circuit respectively；
Second integrated chip respectively with the first signal output part, secondary signal output end, the second NAND gate circuit and
3rd integrated chip is electrically connected；
Second NAND gate circuit is electrically connected with the 3rd integrated chip；3rd NAND gate circuit and the 3rd integrated core
Piece is electrically connected；
3rd integrated chip is electrically connected with secondary signal output end；
The other end ground connection of the electric capacity；Another termination power of the resistance.
The beneficial effects of the present invention are：The phase shift that the present invention is provided suppresses harmonic circuit and meets phase shift harmonic carcellation
Primary condition.Signal feeding excitation amplifying circuit drives the left and right bridge arm of H bridge power amplifiers respectively after amplifying, complete to move
Phase harmonic carcellation.Through actual test, output harmonic wave suppresses about to improve 7dB, and the harmonic emissions of whole machine reach wanting for GJB151A
Ask, it was demonstrated that the harmonics restraint ratio of radio frequency output can be effectively improved.
Brief description of the drawings
Fig. 1 is the circuit connection diagram that a kind of phase shift of the invention suppresses harmonic circuit；
Fig. 2 is each leg signal oscillogram of circuit that a kind of phase shift of the invention suppresses harmonic circuit.
Specific embodiment
It is to describe technology contents of the invention, the objects and the effects in detail, below in conjunction with implementation method and coordinates attached
Figure is explained.
Fig. 1 is refer to, a kind of phase shift that the present invention is provided suppresses harmonic circuit, including：Carrier signal input, the first letter
Number output end, secondary signal output end, the first integrated chip, the second integrated chip, the 3rd integrated chip, the first NAND gate electricity
Road, the second NAND gate circuit, the 3rd NAND gate circuit, electric capacity, resistance and power supply；
Carrier signal input output end respectively with radio transmitter, the first integrated chip and the first NAND gate
Circuit is electrically connected；
First integrated chip respectively with the first NAND gate circuit, the second integrated chip, the 3rd integrated chip, electric capacity
One end electrical connection of one end and resistance；
First NAND gate circuit is electrically connected with the second integrated chip and the 3rd NAND gate circuit respectively；
Second integrated chip respectively with the first signal output part, secondary signal output end, the second NAND gate circuit and
3rd integrated chip is electrically connected；
Second NAND gate circuit is electrically connected with the 3rd integrated chip；3rd NAND gate circuit and the 3rd integrated core
Piece is electrically connected；
3rd integrated chip is electrically connected with secondary signal output end；
The other end ground connection of the electric capacity；Another termination power of the resistance.
General phase-shift circuit is realized using RC or lc circuit, and phase shifting angle is determined by selected component values
It is fixed, want to obtain accurate phase shifting angle in the application, the required precision to component values is very high, actual to realize difficulty, in addition electricity
The easy institute's such environmental effects of component values on road and cause circuit easily produce phase drift in actual use.
Knowable to foregoing description, the beneficial effects of the present invention are：Using circuit of the present invention come phase shift, phase shifting angle and circuit
Component values are unrelated, therefore, it is readily available high-precision phase shifting angle.The phase shift that the present invention is provided suppresses harmonic circuit and meets shifting
The primary condition of phase harmonic carcellation.Signal feeding excitation amplifying circuit drives the left and right of H bridge power amplifiers respectively after amplifying
Bridge arm, completes phase shift harmonic carcellation.Through actual test, output harmonic wave suppresses about to improve 7dB, and the harmonic emissions of whole machine reach
The requirement of GJB151A, it was demonstrated that the harmonics restraint ratio of radio frequency output can be effectively improved.
Further, first integrated chip includes the first pin, second pin, the 3rd pin, the 4th pin, the 5th
Pin and the 6th pin；
The suspension of first pin of first integrated chip, the 3rd pin and the 5th pin；
The second pin of first integrated chip is electrically connected with carrier signal input；
4th pin of first integrated chip is electrically connected with the second integrated chip；
6th pin of first integrated chip is electrically connected with the first NAND gate circuit.
Further, first NAND gate circuit includes first input end, the second input and the first output end；
The first input end of first NAND gate circuit is electrically connected with carrier signal input；
Second input of first NAND gate circuit is electrically connected with the 6th pin of first integrated chip；
First output end of first NAND gate circuit is electrically connected with the second integrated chip and the 3rd NAND gate circuit respectively
Connect.
Further, second integrated chip includes the first pin, second pin, the 3rd pin, the 4th pin, the 5th
Pin and the 6th pin；
First pin of second integrated chip and the 5th pin are suspended；
The second pin of second integrated chip is electrically connected with the first output end of first NAND gate circuit；
3rd pin of second integrated chip is electrically connected with secondary signal output end；
4th pin of second integrated chip respectively with the 4th pin, the 3rd integrated core of first integrated chip
One end electrical connection of piece, one end of electric capacity and resistance；
6th pin of second integrated chip collects with the first signal output part, the second NAND gate circuit and the 3rd respectively
Into chip electrical connection.
Further, second NAND gate circuit includes the 3rd input, the 4th input and the second output end；
3rd input and the 4th input of second NAND gate circuit are respectively with the of second integrated chip
Six pins are electrically connected；
Second output end of second NAND gate circuit is electrically connected with the 3rd integrated chip.
Further, the 3rd NAND gate circuit includes the 5th input, the 6th input and the 3rd output end；
5th input and the 6th input of the 3rd NAND gate circuit are respectively with the first of the first NAND gate circuit
Output end is electrically connected；
3rd output end of the 3rd NAND gate circuit is electrically connected with the 3rd integrated chip.
Further, the 3rd integrated chip includes the first pin, second pin, the 3rd pin, the 4th pin, the 5th
Pin and the 6th pin；
The 6th pin suspension of the 3rd integrated chip；
First pin of the 3rd integrated chip is electrically connected with the second output end of second NAND gate circuit；
The second pin of the 3rd integrated chip is electrically connected with the 3rd output end of the 3rd NAND gate circuit；
3rd pin of the 3rd integrated chip is electrically connected with the 6th pin of second integrated chip；
4th pin of the 3rd integrated chip is electrically connected with the 4th pin of second integrated chip；
5th pin of the 3rd integrated chip respectively with the 3rd pin and secondary signal of second integrated chip
Output end is electrically connected.
It should be noted that：
First signal output part is the P1 in Fig. 1；Secondary signal output end is the P2 in Fig. 1；
First integrated chip is the D2A in Fig. 1；Second integrated chip is the D2B in Fig. 1；3rd integrated chip is in Fig. 1
D3A；Integrated chip is using the integrated chip of model 54LS107；
First NAND gate circuit is the D1A in Fig. 1；Second NAND gate circuit is the D1C in Fig. 1；3rd NAND gate circuit
It is the D1B in Fig. 1；NAND gate circuit uses the integrated chip of model 54LS00；
Electric capacity is the μ F of C1 47；Resistance is R1 10K Ω；Power supply is+5V；
The cardinal principle that phase shift of the invention suppresses harmonic circuit is：4 are improved by the reference frequency of frequency synthesizer
Times so that the carrier wave exciting signal frequency of frequency synthesizer output improves 4 times, the carrier wave pumping signal is sent into of the invention
Phase shift suppresses that harmonic circuit just can obtain that two-way carrier operation frequency is identical and phase differs 45 ° of drive signal, then this two
Road signal feeding excitation amplifying circuit is connected respectively to the left and right bridge arm for driving H bridge power amplifiers after amplifying, so that it may in power
The output end of amplifier obtains the rf power signal of required harmonic carcellation.
For the ease of analysis circuit operation principle, the waveform of circuit groundwork point is drawn as shown in Figure 2.Wherein D2
(12) the 12nd pin of integrated circuit D2 is meant that, other pins are by that analogy；
Electric clear circuit on R1 and C1 compositions, just during upper electricity, due to the effect of clear circuit, 3 pin of D2 export low level,
6 pin of D2 and 9 pin output high level, 3 pin and 12 pin of D3 are low level；When first pulse falling edge of input signal arrives
When, the 3 pin output high level of D2,2 pin of D1 are changed into high level, and now 1 pin of D1 is low level, so 3 pin of D1 are still defeated
Go out high level, the circuit state of rear class keeps constant；When second rising edge of a pulse arrives, the 3 pin output low level of D1, D3
12 pin be changed into high level, now 11 pin of D2 be low level, 8 pin be high level, then D2 6 pin output low level, become by this
The influence of change, 4 pin of D3 are changed into low level, and 1 pin is changed into high level, because 12 pin of D3 are high level, so 3 pin of D3 are still
Keep low level；When second pulse falling edge arrives, 3 pin of D1 are changed into high level, and 12 pin of D3 are changed into low level, by it
Influence, 3 pin of D3 are changed into high level, and 11 pin of D2 also become high level.By that analogy, 6 pin and D3 from D2 can be analyzed
3 pin output signals be dutycycle be 50%, frequency be input signal 1/4 square-wave signal, as can be seen from Figure 2 two letter
Number frequency is identical and phase differs 45 °.
The method that phase shift suppresses harmonic wave is realized present applicant proposes being divided after carrier signal elder generation frequency multiplication, a job is first exported
The carrier signal of frequency even-multiple, the signal after the frequency dividing circuit that J-K flip flop and NAND gate are constituted by exporting two-way frequency
Identical and phase one fixed angle of difference is the high-frequency square-wave signal of φ, is so obtained after H bridges power amplifier amplifies
Output pulse width is the high-frequency pulse signal of θ=180 °-φ, so as to reach the effect of suppression or harmonic carcellation, improves radio hair
Penetrate the output harmonic wave rejection ratio of machine.
The principle that phase shift suppresses harmonic wave is wrong with right side pumping signal by the left side pumping signal H bridge power amplifiers
Open an angle phi so that the pulsewidth θ of the output voltage of H bridge power amplifiers changes, be no longer 180 °, and become θ
=180 ° of-φ, the fourier series expression formula of such H bridges power amplifier output voltage is：
So, the amplitude U of nth harmonicabm(n)For：
Can be drawn from formula (2), when φ=60 °, θ=180 °-φ=120 °, then, for 3 subharmonic, its amplitudeThat is, when angle of phase displacement φ=60 °, the nothing 3 in output voltage
Subharmonic content, so as to just reach the purpose for eliminating 3 subharmonic.Therefore, appropriate angle of phase displacement φ is selected, it is possible to regulation output
The content of each harmonic in voltage, reaches the effect of suppression or harmonic carcellation.
In medium wave navigation product, the angle of phase displacement φ selected in side circuit is 45 °.First theoretically calculate in nothing below
3 times in the case of two kinds of phase shift (i.e. angle of phase displacement φ=0 °) and angle of phase displacement φ=45 °, the harmonics restraint amount of 5 times is (with fundamental wave ratio
Compared with).
When angle of phase displacement φ=0 °, can be obtained by formula (2), fundamental wave, 3 subharmonic, the amplitude of 5 subharmonic are respectively：
If fundamental wave, 3 subharmonic, the power level of 5 subharmonic are respectively P1, P3, P5,3 subharmonic, 5 subharmonic amount of suppression
It is A3, harmonics restraint amount is A5, then have：
A can similarly be obtained5≈14dB。
When angle of phase displacement φ=45 °, can be obtained by formula (2), fundamental wave, 3 subharmonic, the amplitude of 5 subharmonic are respectively：
A can similarly be obtained3≈ 17.2dB, A5≈21.6dB。
As seen from the above, when angle of phase displacement φ=45 °, 3 times, 5 subharmonic amount of suppression are than traditional H bridges power amplifier
Output has been respectively increased 7.7dB and 7.6dB, and harmonics restraint improvement amount disclosure satisfy that index request.
It is that the carrier wave exciting signal frequency that frequency synthesizer is exported improves 4 times in physical circuit design, then by J-K
4 frequency dividing circuits of trigger composition divide carrier wave pumping signal, so as to obtain that two-way carrier operation frequency is identical and phase
The drive signal of 45 ° of position difference.
Such as Fig. 1-2, P1 with P2 two-way output signal frequencies are identical and phase differs 45 °, and it meets phase shift harmonic carcellation
Primary condition.Signal feeding excitation amplifying circuit drives the left and right bridge arm of H bridge power amplifiers respectively after amplifying, complete
Phase shift harmonic carcellation.
Embodiments of the invention are the foregoing is only, the scope of the claims of the invention is not thereby limited, it is every to utilize this hair
The equivalents that bright specification and accompanying drawing content are made, or the technical field of correlation is directly or indirectly used in, similarly include
In scope of patent protection of the invention.
Claims (7)
1. a kind of phase shift suppresses harmonic circuit, it is characterised in that including：Carrier signal input, the first signal output part, second
Signal output part, the first integrated chip, the second integrated chip, the 3rd integrated chip, the first NAND gate circuit, the second NAND gate electricity
Road, the 3rd NAND gate circuit, electric capacity, resistance and power supply；
Carrier signal input output end respectively with radio transmitter, the first integrated chip and the first NAND gate circuit
Electrical connection；
First integrated chip respectively with the first NAND gate circuit, the second integrated chip, the 3rd integrated chip, electric capacity one end
One end with resistance electrically connects；
First NAND gate circuit is electrically connected with the second integrated chip and the 3rd NAND gate circuit respectively；
Second integrated chip respectively with the first signal output part, secondary signal output end, the second NAND gate circuit and the 3rd
Integrated chip is electrically connected；
Second NAND gate circuit is electrically connected with the 3rd integrated chip；3rd NAND gate circuit and the 3rd integrated chip electricity
Connection；
3rd integrated chip is electrically connected with secondary signal output end；
The other end ground connection of the electric capacity；Another termination power of the resistance.
2. phase shift according to claim 1 suppresses harmonic circuit, it is characterised in that first integrated chip includes first
Pin, second pin, the 3rd pin, the 4th pin, the 5th pin and the 6th pin；
The suspension of first pin of first integrated chip, the 3rd pin and the 5th pin；
The second pin of first integrated chip is electrically connected with carrier signal input；
4th pin of first integrated chip is electrically connected with the second integrated chip；
6th pin of first integrated chip is electrically connected with the first NAND gate circuit.
3. phase shift according to claim 2 suppresses harmonic circuit, it is characterised in that first NAND gate circuit includes the
One input, the second input and the first output end；
The first input end of first NAND gate circuit is electrically connected with carrier signal input；
Second input of first NAND gate circuit is electrically connected with the 6th pin of first integrated chip；
First output end of first NAND gate circuit is electrically connected with the second integrated chip and the 3rd NAND gate circuit respectively.
4. phase shift according to claim 3 suppresses harmonic circuit, it is characterised in that second integrated chip includes first
Pin, second pin, the 3rd pin, the 4th pin, the 5th pin and the 6th pin；
First pin of second integrated chip and the 5th pin are suspended；
The second pin of second integrated chip is electrically connected with the first output end of first NAND gate circuit；
3rd pin of second integrated chip is electrically connected with secondary signal output end；
4th pin of second integrated chip the 4th pin respectively with first integrated chip, the 3rd integrated chip,
One end electrical connection of one end and resistance of electric capacity；
6th pin of second integrated chip respectively with the first signal output part, the second NAND gate circuit and the 3rd integrated core
Piece is electrically connected.
5. phase shift according to claim 4 suppresses harmonic circuit, it is characterised in that second NAND gate circuit includes the
Three inputs, the 4th input and the second output end；
3rd input and the 4th input of second NAND gate circuit the 6th drawing respectively with second integrated chip
Pin is electrically connected；
Second output end of second NAND gate circuit is electrically connected with the 3rd integrated chip.
6. phase shift according to claim 5 suppresses harmonic circuit, it is characterised in that the 3rd NAND gate circuit includes the
Five inputs, the 6th input and the 3rd output end；
5th input and the 6th input of the 3rd NAND gate circuit respectively with the first of the first NAND gate circuit the output
End electrical connection；
3rd output end of the 3rd NAND gate circuit is electrically connected with the 3rd integrated chip.
7. phase shift according to claim 6 suppresses harmonic circuit, it is characterised in that the 3rd integrated chip includes first
Pin, second pin, the 3rd pin, the 4th pin, the 5th pin and the 6th pin；
The 6th pin suspension of the 3rd integrated chip；
First pin of the 3rd integrated chip is electrically connected with the second output end of second NAND gate circuit；
The second pin of the 3rd integrated chip is electrically connected with the 3rd output end of the 3rd NAND gate circuit；
3rd pin of the 3rd integrated chip is electrically connected with the 6th pin of second integrated chip；
4th pin of the 3rd integrated chip is electrically connected with the 4th pin of second integrated chip；
5th pin of the 3rd integrated chip is exported with the 3rd pin and secondary signal of second integrated chip respectively
End electrical connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710193215.3A CN106877636B (en) | 2017-03-28 | 2017-03-28 | Phase-shifting harmonic suppression circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710193215.3A CN106877636B (en) | 2017-03-28 | 2017-03-28 | Phase-shifting harmonic suppression circuit |
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| Publication Number | Publication Date |
|---|---|
| CN106877636A true CN106877636A (en) | 2017-06-20 |
| CN106877636B CN106877636B (en) | 2023-03-10 |
Family
ID=59159317
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710193215.3A Active CN106877636B (en) | 2017-03-28 | 2017-03-28 | Phase-shifting harmonic suppression circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108023607A (en) * | 2017-11-30 | 2018-05-11 | 广东欧珀移动通信有限公司 | Antenna module and terminal device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3935387A (en) * | 1970-03-14 | 1976-01-27 | U.S. Philips Corporation | Pulse generator for television for generating at least one pulse series having pulses of different duration and repetition period |
| US4423382A (en) * | 1981-08-10 | 1983-12-27 | Reliance Electric Company | Circuit for generating two periodic signals having a controllable phase relationship therebetween |
| JPS61104644U (en) * | 1984-12-15 | 1986-07-03 | ||
| CN2216306Y (en) * | 1994-12-24 | 1995-12-27 | 王雁翔 | Silicon controlled DC speed regulator |
| CN101414155A (en) * | 2008-11-20 | 2009-04-22 | 无锡汉神电气有限公司 | Circuit structure of electric welding machine panel code dialing machine |
-
2017
- 2017-03-28 CN CN201710193215.3A patent/CN106877636B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3935387A (en) * | 1970-03-14 | 1976-01-27 | U.S. Philips Corporation | Pulse generator for television for generating at least one pulse series having pulses of different duration and repetition period |
| US4423382A (en) * | 1981-08-10 | 1983-12-27 | Reliance Electric Company | Circuit for generating two periodic signals having a controllable phase relationship therebetween |
| JPS61104644U (en) * | 1984-12-15 | 1986-07-03 | ||
| CN2216306Y (en) * | 1994-12-24 | 1995-12-27 | 王雁翔 | Silicon controlled DC speed regulator |
| CN101414155A (en) * | 2008-11-20 | 2009-04-22 | 无锡汉神电气有限公司 | Circuit structure of electric welding machine panel code dialing machine |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108023607A (en) * | 2017-11-30 | 2018-05-11 | 广东欧珀移动通信有限公司 | Antenna module and terminal device |
| CN108023607B (en) * | 2017-11-30 | 2019-07-19 | Oppo广东移动通信有限公司 | Antenna module and terminal device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106877636B (en) | 2023-03-10 |
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