CN106874799A - A kind of physics unclonable function generation method based on clock distributing network - Google Patents

Abstract

The present invention provides a kind of physics unclonable function generation method based on clock distributing network, clock distributing network is divided into several spatially adjacent Clock grids by the invention, is chosen neighbouring clock leaf node or register in adjacent mesh respectively and is connected to the phase comparator PC being distributed in net boundary.Postponed by adjusting interconnection, the phase difference that clock leaf node reaches phase comparator PC is suppressed in the range of very little.Secondly, phase bit comparison comparator PC intension phase aliasing device PI and phase comparator PD, output phase sequencing is exported as the PUF of single bit after processing output source signal.

Description

A kind of physics unclonable function generation method based on clock distributing network

Technical field

The present invention relates to information security field, more particularly, to a kind of physics based on clock distributing network can not gram Grand function generation method.

Background technology

PUF letters are physics unclonable function (Physical Unclonable Function), can from definition To know, PUF first must be realized as hardware, secondly can be realized as function performance.The definition of function is segmented into three Individual aspect：

1) input (being defined as excitation, challenge) x ∈ X, output (being defined as response, response) y ∈ Y, wherein x It is the binary sequence of n-bit, y is the binary sequence of m-bit.Single excitation and response can use one group of excitation response pair CRP (x, y) is represented；Regardless of internal working mechanism, PUF is digitized input and output for this definition explanation, without It is the signal of emulation mode.

2) PUF is responsible for the mapping from x to y, is defined as Γ:X→Y:Γ (x)=y；For single PUF equipment, one is being allowed It is unique to export y on the premise of determining error rate, after the corresponding mappings of input stimulus x；This definition determines the unique of mapping Property.

3) CRP (x, y) realizes that difference is determined by the hardware between PUF equipment.For different PUF equipment, input stimulus x Response y is exported after corresponding mapping also different.Hardware realizes that difference is very delicate, especially in integrated circuit fabrication, refers to In the case of being delivered to the domain mask data of chip manufacturer and being identical, the very small hardware of degree is still there is Realize difference.To do is to find and utilize these differences needed for PUF, it is amplified, arranges, is digitized, make to produce Set of hardware response collection Y have sufficiently large diversity factor.

Preferable PUF should have following features：

1) uniqueness Uniqueness.Firstly, for different PUF equipment, y is also different for its output response, this feature It is most important, play conclusive effect for applications of the PUF in terms of certification and signature；Mapping representated by PUF equipment i Γ_i:X→Y:Γ_iThe physical message of particular device i is contained in (x)=y；Hardware differences between PUF equipment are to CRP (x, y) Influence can be tested with the Hamming distance (being defined as HDinter) responded between distinct device to CRP (x, y).

Assuming that there are two different PUF hardware devices, it is assumed here that it is i and j, and is had (i ≠ j), for excitation C, have The response R of m-bit_iAnd R_j, then the k average HD of equipment_interCan be calculated as follows：

2) reliability Reliability.Correctness Correctness is also referred to as in some documents.For single PUF, With sufficiently strong stability Stability.For firstly, for same equipment, same excitation x is in identical work bar It is consistent that y is responded under part, and this is the essential distinction of PUF and pseudorandom number generator PRNG.Secondly, under various operating conditions The response for obtaining should also be consistent, it is possible to be weighed with HDintra.It is defined as follows, firstly for general work bar For excitation C under part, obtain with reference to mapping R.For same excitation C, PUF is allowed repeatedly to map it, then just to have phase The m-bit response outputs R ' for answering_i,t, sampling n times after, average HD_intraIt is calculated as follows：

Reliability=1 | HD_intra,avg

3) uniformity Uniformity.In output drive y in sufficiently large sample space, the probability shared by 0 and 1 is equal 0.5 is equal to Deng, preferable average；If not so, it was demonstrated that the output probability randomness of the equipment has some problems.Define first r_i,lL-th in being responded for the m-bit outputs of equipment i binary system bit, then the Hamming weight of m-bit output responses Hamming Weight are calculated as follows：

For the output response uniformity in whole sample space, its calculation is essentially identical：

4) prevent obscuring Bit-aliasing.For different PUF equipment i and j, there is identical response R_iAnd R_jCan Energy property, is serious threat for safety applications, accordingly, it would be desirable to calculate the probability of its appearance.If confusion probabilities are very high, then Illustrate that the PUF availabilities are not high.Define r_i,lL-th in being responded for the m-bit outputs of equipment i binary system bit；K equipment Confusion probabilities are calculated as follows：

Discussion to PUF generation techniques has focused largely on integrated circuit fields.The reason for having two aspects：First, no matter It is in security fields, key generation, authentication, or the problems such as hardware unique mark, intellectual property protection, to being integrated in core PUF generation techniques on piece have strong demand；Compared with disposable mask OTP technologies, PUF on mask and manufacturing cost compared with Low, the sequence number of OTP write-ins is specified by manufacturer when mask is made, and without real randomness, security is relatively low. NVM technologies are similar with OTP.

Secondly, the PUF in integrated circuit fields has intrinsic attribute：Non-reproduction, this attribute can be divided into physics Non-reproduction and mathematics non-reproduction.Most PUF meet physics non-reproduction：For specific Γ_i:X→ Y:Γ_iX ()=y, it is difficult to replicate reappear another PUF equipment with physical form, makes it meet Γ_j:X→Y:Γ_j(x)=y with The mapping being replicated is of equal value, and has identical response collection Y_j。

It is worth noting that, the mathematics non-reproduction of PUF is not strict, there are many mode attacks for PUF, And achieve notable achievement.Certain specific PUF can be directed to, its CRP be learnt and is set up right within a small number of times Model is answered, its error rate is less than acceptable threshold value.Study on Mathematic Model to PUF shows, meets mathematics non-reproduction PUF is little.

The integrated circuit form of the composition of PUF has many kinds, is as follows than more typical digital circuit PUF structures：

PUF based on sequential propagation contention Propagation Racing.Manufacture address controlled some is completely first Symmetrical digital circuit propagation delay path.It is actuated to the two propagation path addresses for randomly selecting.By same to two paths When apply pulse input, while terminal using moderator judge successively reach order come obtain response collection Y.

Based on the PUF technologies that ring shakes, typically there are hundreds of ring oscillator RO, because technique realizes difference, every RO's Output frequency has delicate difference, and being changed by frequency-phase and compared can obtain digitized response.RO-PUF be compared with The early PUF forms for occurring, study it also more.Security performance for RO-PUF shows that the response modes of RO-PUF are easy It is modeled attack.

Based on the PUF of SRAM initial values, before not completing initialization after electricity on SRAM, bistable logic unit such as Phase inverter to mutually pushing away must be oscillated into bistable state since metastable state, spontaneously form a unknown initial value.Based on reading This initial value in SRAM can build a kind of PUF.

The PUF of other forms has and realizes capacitance difference that difference, metal band manufacturing variation brings based on CMOS sizes, is less than Connected probability table that standard-sized via-hole array brings etc..When present patent application, not yet have based on clock distributing network PUF documents or patent.

The content of the invention

The present invention provides a kind of physics unclonable function generation method based on clock distributing network of stronger practicality.

In order to reach above-mentioned technique effect, technical scheme is as follows：

A kind of physics unclonable function generation method based on clock distributing network, comprises the following steps：

S1：Clock distributing network is divided into several spatially adjacent Clock grids；

S2：Neighbouring clock leaf node or register is chosen in adjacent mesh respectively, and is connected to and is distributed in Grid Edge Phase comparator in boundary；

S3：The interconnection that adjustment clock leaf node or register reach phase comparator postpones, and phase comparator is to pending Signal carries out the treatment corresponding physics unclonable function of output.

Further, the detailed process of the step S1 is：

Whole clock distributing network is divided into M × N number of homogeneous grid, each independent grid G_xyInside there are some clock leaves Node or register, while each independent grid G_xyNeed to other independent grids be adjacent with four.

Further, each independent grid G_xyBorder on set a phase comparator, the adjacent grid of each two lead to Border and phase comparator between crossing form physical connection, each grid G_xyThere are four physics with four other grids around Connection, only has inwardly connection in the grid of outermost.

Further, described each independent grid G_xyIt is interior including at least 4 clock leaf nodes or register.

Further, the detailed process of the step S3 is as follows：

S31：Any two adjacent register or clock leaf node Reg1 and Reg2 are chosen, its clock signal is respectively Φ 1 and Φ 2, phase difference between the two meets relation：

|φ₁₂=Φ 2- Φ 1 | ＜ S+J

Wherein, Reg1 and Reg2 are connected to phase comparator PC_xynm, φ₁₂It is positive number or negative, S is clock distributing network Global clock deflection, the clock jitter of J clock distributing networks；

S32：Using RC equivalent models respectively to Reg1 and Reg2 to PC_xynmPropagation delay be described：

TD₁=kR₁C₁

TD₂=kR₂C₂

The clock signal of Reg1 and Reg2 reaches phase comparator PC_xynmPhase difference be：

φ '=φ₁₂+(TD₁-TD₂)=φ₁₂+k(R₁C₁-R₂C₂)

By adjusting R₁C₁And R₂C₂Ratio, φ ' is limited in very small scope, phase comparator PC_xynmCompare The phase of both Φ 1 and Φ 2, and export comparative result；

S33：Phase comparator PC_xynmIn aliasing device PI clock signal Φ 1 and Φ 2 are entered into line aliasing, as phase ratio Compared with reference signal Φ_ref=α Φ 1+ (1- α) Φ 2, phase comparator PC_xynmIn phase discriminator PD differentiate Φ_refAnd Φ 2 between Phase difference ", the output O of phase discriminator PD_PDFor：

Wherein, T_suIt is the setup time of phase discriminator PD；

S34：If the phase discriminator output result in pair all phase comparators being laid out to M × N Clock grids is returned One changes, and it is the laterally vector of M-1 that can obtain N number of length：H₁=(PD₁₁₁₂,PD₁₂₁₃), H₁=(PD₂₁₂₂, PD₂₂₂₃), H_N-1=(PD_N1N2,PD_N2N3) and M length be the longitudinal direction vector of N-1：V₁, V₂, V_M-1Obtain the physics unclonable function of each grid.

Compared with prior art, the beneficial effect of technical solution of the present invention is：

Clock distributing network is divided into several spatially adjacent Clock grids by the present invention, respectively in adjacent mesh Choose neighbouring clock leaf node or register and be connected to the phase comparator PC being distributed in net boundary.It is mutual by adjustment Connection postpones, and the phase difference that clock leaf node reaches phase comparator PC is suppressed in the range of very little.Secondly, phase bit comparison ratio Compared with device PC intension phase aliasing device PI and phase comparator PD, output phase sequencing is made after processing output source signal For the PUF of single bit is exported.

Brief description of the drawings

Fig. 1 is that integral grid of the invention divides schematic diagram；

Fig. 2 is adjacent mesh physical connection figure；

Fig. 3 is PI aliasing clock phase graphs of a relation；

Fig. 4 is PD output signals probability and timing diagram.

Specific embodiment

Accompanying drawing being for illustration only property explanation, it is impossible to be interpreted as the limitation to this patent；

In order to more preferably illustrate the present embodiment, accompanying drawing some parts have omission, zoom in or out, and do not represent actual product Size；

To those skilled in the art, it can be to understand that some known features and its explanation may be omitted in accompanying drawing 's.

Technical scheme is described further with reference to the accompanying drawings and examples.

Embodiment 1

The global clock deflection of clock distributing network G is S, be defined as in whole clock zone any two clock node it Between phase difference maximum：

MAX(|φ_i-φ_j|)≤S

The clock jitter of clock distributing network G is defined as J, is defined as clock any two week on any one clock node The maximum of the phase deviation degree on the phase：

MAX(|φ_k-φ_k'|)≤J

Assuming that clock jitter is derived only from clock source, and propagated along whole clock zone, therefore the clock on whole clock zone Shake is homogeneous.In the range of clock uncertainty φ so between any two clock leaf node can be limited to.

φ ＜ S+J

After setting the scope of S+J, clock tree synthesis CTS is carried out to digital circuit, when can obtain the physics of stringent synchronization Clock signal.To illustrate as follows how to produce physics unclonable function PUF using clock distributing network.

As shown in figure 1, whole clock distributing network to be divided into the present invention grid of M × N layouts.

First, this network G_xyBorder be used only as logicality mark, it is actual simultaneously need not be by whole clock distribution of net Network is divided into homogeneous grid, each independent grid G_xyPosition depend on actual need depending on, but must assure that each independent grid G_xyInside there are minimum more than 4 clock leaf nodes or register terminal, while each independent grid G_xyNeed to be with four other independences Grid is adjacent.

Secondly, this network G_xyBorder and clock distribution grid Clock Mesh do not demarcate clearly, both can be with It is multiplexed existing clock distribution grid, it would however also be possible to employ different sizing grids are split to clock network.This network G_xyIt is that the latter often uses metal rail or multiple large-sized buffers to clock signal with the difference of Clock grid Mesh Carry out indifference driving.

Again, a phase comparator PC can be placed on the border of this network.That is, the adjacent grid of each two all can Border and phase comparator PC between form physical connection.In general, each grid G_xyWith around four other Grid has four physical connections.Only have inwardly connection in the grid of outermost, but this have no effect on PUF realize result.

The mode of physical connection between following elaboration grid.

First, with symmetrical or other feasibility principles, adjacent mesh G is determined_xyWith grid G_nmBoundary position, and herein Boundary position sets phase comparator PCxynm；

Secondly, as shown in Fig. 2 using neighbouring preferential principle chosen in two adjacent mesh respectively two registers or Clock leaf node Reg1 and Reg2, clock signal are designated as Φ 1 and Φ 2.Obviously phase difference between the two meets relation | φ₁₂= Φ 2- Φ 1 | ＜ S+J.And φ₁₂Can just can bear.

Again, clock leaf node Reg1 and Reg2 is each connected to PCxynm using symmetrical mode, due to Reg1 and The distribution of Reg2 typically have locality, the physical distance for being connected to PCxynm can't be oversize, without centre again insertable into Buffer structure, is described to the propagation delay of Reg1 and Reg2 to PCxynm respectively using RC equivalent models：

TD₁=kR₁C₁

TD₂=kR₂C₂

So, the phase difference of the clock signal arrival PCxynm of Reg1 and Reg2 is：

φ '=φ₁₂+(TD₁-TD₂)=φ₁₂+k(R₁C₁-R₂C₂)

By adjusting R₁C₁And R₂C₂Ratio, φ ' can be limited in very small scope, only several ps amounts Level, it is even lower；PCxynm compares the phase of both Φ 1 and Φ 2, and exports comparative result.

The structure of PC includes aliasing device Phase Interpolator, phase discriminator Phase Detector.

As shown in figure 3, aliasing device PI enters line aliasing to the two phase clock Φ 1 and Φ 2 that are compared, as the ginseng of phase bit comparison Examine signal Phi_ref=α Φ 1+ (1- α) Φ 2.Wherein aliased coefficient α is the constant between 0 and 1, with aliasing device circuit output The transistor size of unit is than related.Reference clock signal Φ is exported after aliasing_refIn sequential between Φ 1 and Φ 2.By adjusting Section α, it is possible to achieve the uniform aliasing of two phase clock.

Phase discriminator PD is used for differentiating Φ_refAnd the phase difference between Φ 2 ".The present invention uses the phase discriminator of digital form PD.This phase discriminator has certain setup time T_su, and T_suWith φ " relatively.Therefore, the output O of PD_PDWith T_suWith φ " between Phase relation it is relevant, with certain randomness.Its output probability is distributed as shown in figure 4, due to " being subject to process variations influence May fall in different time ordered intervals, different chip outputs may difference, its probability and T_suWith φ " length it is relevant.This hair Bright is weak PUF.

To phase discriminator output result carry out it is sampled, digitized after, can learn that each phase discriminator PD will have 1bit Output.Excitation C is the address of PD arrays, and response R is the output signal of PD arrays.If to the PD knots of M × N Clock grids layout Fruit is normalized, and it is the laterally vector of M-1 that can obtain N number of length：H₁=(PD₁₁₁₂,PD₁₂₁₃), H₁= (PD₂₁₂₂,PD₂₂₂₃), H_N-1=(PD_N1N2,PD_N2N3) and M length for N-1 longitudinal direction to Amount：V₁, V₂, V_M-1.Vector can be post-processed and exported with obtaining quality PUF higher to more than.

In sum, the PUF based on clock distribution grid meets following requirement：Uniqueness, the output of each PUF with work as Preceding hard-wired otherness is relevant, and with physics non-reproduction；Stability, gives under different PVT conditions of work Identical encourages C, and its output response R has consistency；Low cost of implementation, it is only necessary to which a little change is done to clock distribution grid, Increase phase comparison unit simultaneously.

The same or analogous part of same or analogous label correspondence；

Position relationship for the explanation of being for illustration only property described in accompanying drawing, it is impossible to be interpreted as the limitation to this patent；

Obviously, the above embodiment of the present invention is only intended to clearly illustrate example of the present invention, and is not right The restriction of embodiments of the present invention.For those of ordinary skill in the field, may be used also on the basis of the above description To make other changes in different forms.There is no need and unable to be exhaustive to all of implementation method.It is all this Any modification, equivalent and improvement made within the spirit and principle of invention etc., should be included in the claims in the present invention Protection domain within.

Claims (5)

1. a kind of physics unclonable function generation method based on clock distributing network, it is characterised in that comprise the following steps：

S1：Clock distributing network is divided into several spatially adjacent Clock grids；

S2：Neighbouring clock leaf node or register is chosen in adjacent mesh respectively, and is connected to and is distributed in net boundary Phase comparator；

S3：The interconnection that adjustment clock leaf node or register reach phase comparator postpones, and phase comparator treats process signal Carry out the treatment corresponding physics unclonable function of output.

2. the physics unclonable function generation method based on clock distributing network according to claim 1, its feature exists In the detailed process of the step S1 is：

Whole clock distributing network is divided into M × N number of homogeneous grid, each independent grid G_xyInside there are some clock leaf nodes Or register, while each independent grid G_xyNeed to other independent grids be adjacent with four.

3. the physics unclonable function generation method based on clock distributing network according to claim 2, its feature exists In each independent grid G_xyBorder on set a phase comparator, the adjacent grid of each two pass through between border with And phase comparator forms physical connection, each grid G_xyThere are four physical connections with four other grids around, in outermost Grid only have inwardly connection.

4. the physics unclonable function generation method based on clock distributing network according to claim 2, its feature exists In described each independent grid G_xyIt is interior including at least 4 clock leaf nodes or register.

5. the physics unclonable function generation method based on clock distributing network according to claim 2, its feature exists In the detailed process of the step S3 is as follows：

S31：Any two adjacent register or clock leaf node Reg1 and Reg2 are chosen, its clock signal is respectively the Hes of Φ 1 Φ 2, phase difference between the two meets relation：

|φ₁₂=Φ 2- Φ 1 | ＜ S+J

Wherein, Reg1 and Reg2 are connected to phase comparator PC_xynm, φ₁₂It is positive number or negative, S is complete for clock distributing network Office clock deflection, the clock jitter of J clock distributing networks；

S32：Using RC equivalent models respectively to Reg1 and Reg2 to PC_xynmPropagation delay be described：

TD₁=kR₁C₁

TD₂=kR₂C₂

The clock signal of Reg1 and Reg2 reaches phase comparator PC_xynmPhase difference be：

φ '=φ₁₂+(TD₁-TD₂)=φ₁₂+k(R₁C₁-R₂C₂)

By adjusting R₁C₁And R₂C₂Ratio, φ ' is limited in very small scope, phase comparator PC_xynmCompare the Hes of Φ 1 The phase of both Φ 2, and export comparative result；

S33：Phase comparator PC_xynmIn aliasing device PI clock signal Φ 1 and Φ 2 are entered into line aliasing, as the ginseng of phase bit comparison Examine signal Phi_ref=α Φ 1+ (1- α) Φ 2, phase comparator PC_xynmIn phase discriminator PD differentiate Φ_refAnd the phase between Φ 2 Difference φ ", the output O of phase discriminator PD_PDFor：

$O_{PD}=\left\{\begin{array}{cc}1,& \left|{\mathrm{\&phi;}}^{\&prime;\&prime;}\right|>T_{su}\\ 0,& \left|{\mathrm{\&phi;}}^{\&prime;\&prime;}\right|<T_{su}\end{array}\right.$

Wherein, T_suIt is the setup time of phase discriminator PD；

S34：If the phase discriminator output result in pair all phase comparators being laid out to M × N Clock grids is normalized, It is the laterally vector of M-1 that N number of length can be obtained：H₁=(PD₁₁₁₂,PD₁₂₁₃), H₁=(PD₂₁₂₂, PD₂₂₂₃), H_N-1=(PD_N1N2,PD_N2N3) and M length be the longitudinal direction vector of N-1：V₁, V₂, V_M-1Obtain the physics unclonable function of each grid.