CN106874158A - A kind of heterogeneous system Whole Process power consumption metering method - Google Patents

A kind of heterogeneous system Whole Process power consumption metering method Download PDF

Info

Publication number
CN106874158A
CN106874158A CN201710020074.5A CN201710020074A CN106874158A CN 106874158 A CN106874158 A CN 106874158A CN 201710020074 A CN201710020074 A CN 201710020074A CN 106874158 A CN106874158 A CN 106874158A
Authority
CN
China
Prior art keywords
power consumption
section
processor
heterogeneous
isomorphism
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710020074.5A
Other languages
Chinese (zh)
Inventor
王卓薇
程良伦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Guangdong University of Technology
Original Assignee
Guangdong University of Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Guangdong University of Technology filed Critical Guangdong University of Technology
Priority to CN201710020074.5A priority Critical patent/CN106874158A/en
Publication of CN106874158A publication Critical patent/CN106874158A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/3003Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3006Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system is distributed, e.g. networked systems, clusters, multiprocessor systems
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/3058Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/3058Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
    • G06F11/3062Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations where the monitored property is the power consumption
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3447Performance evaluation by modeling
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3452Performance evaluation by statistical analysis
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computing Systems (AREA)
  • Computer Hardware Design (AREA)
  • Evolutionary Biology (AREA)
  • Bioinformatics & Computational Biology (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Bioinformatics & Cheminformatics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Mathematical Physics (AREA)
  • Power Sources (AREA)

Abstract

The invention discloses a kind of heterogeneous system Whole Process power consumption metering method, including step:Set up and calculate program execution time and dynamic power consumption relation that section is divided more multiprocessor;Data transfer is obtained to be influenced each other with quiescent dissipation with chip temperature management in real time under the communication power consumption formalized description method and analysis thermal model of multitask dynamically distributes.Compared with prior art, implementation procedure of the present invention analysis concurrent program on heterogeneous system, the power consumption modeling of the multiple parallel sections of concern, the communication overhead that primary processor brings with OverDrive Processor ODP task communication is considered simultaneously, and the influence of leakage current that chip temperature elevated band is come, from Whole Process angle, accurate count Heterogeneous parallel system power consumption calculation.

Description

A kind of heterogeneous system Whole Process power consumption metering method
Technical field
The present invention relates to heterogeneous system field, more particularly to a kind of heterogeneous system Whole Process power consumption metering method.
Background technology
Power consumption accurate measurement is the basis that optimised power consumption is carried out towards particular architecture.At present on heterogeneous system power consumption The research of metering method is simultaneously insufficient, is obtained based on the modification of isomorphism system power dissipation metering method.However, heterogeneous system by In various different types of processors (being broadly divided into primary processor and OverDrive Processor ODP) are integrated with, each processor not only has not Same architecture;Primary processor is mostly linked with OverDrive Processor ODP by system bus simultaneously, is performed in scheduling acceleration components and added Speed necessarily introduces extra traffic operation during calculating;Other OverDrive Processor ODP dense process unit cause chip temperature compared with General processor is high, and temperature can produce certain influence on quiescent dissipation, causes quiescent dissipation ratio gradually increasing, therefore face Can be more complicated compared to isomorphism system to the power consumption metering object of heterogeneous system.
The object of traditional power consumption metering is essentially all to be modeled individually for processor part or whole processor, The system power dissipation of consideration is unrelated with the implementation procedure of application program, is only determined by processor.But in heterogeneous system, due to compiling Limitation on journey model or architecture, concurrent application is mostly performed not successively using general purpose microprocessor and acceleration components Whole application is completed with the mode for calculating section, and with heterogeneous parallel processing technology and its constantly improve of back-up environment, By the way of increasing concurrent program will process single parallel computation section using heterogeneous multi-processor the parallel combined, fully to open The advantage of hair system in parallel treatment.Simultaneously as mostly being passed by pci interface between primary processor and acceleration components in heterogeneous system Delivery data, its individual event peak bandwidth is only 8GB/s, and the OverDrive Processor ODP video memory capacity particularly with GPU as representative has been difficult Meet the demand of scientific algorithm application, further increase the pressure of data communication bandwidth, for mass data intensive applications, Data communication expense between processor causes not small influence on heterogeneous system high power consumption.As integrated circuit enters nanometer work Skill, leakage current quiescent dissipation has exceeded dynamic power consumption, becomes the main source of chip power-consumption.
The content of the invention
To overcome the deficiencies in the prior art, heterogeneous system power consumption metering method is set up from Whole Process angle, effectively reduce system System energy consumption, highly efficient exploitation heterogeneous system performance advantages, the present invention proposes a kind of heterogeneous system Whole Process power consumption metering method.
The technical proposal of the invention is realized in this way:
A kind of heterogeneous system Whole Process power consumption metering method, including step
S1:For heterogeneous multi-processor parallel processing single parallel computation section, according to same type processor or it is various not Same type processor completes to calculate the different modes of section, and analysis isomorphism calculates section program execution time to calculating section dynamic power consumption Influence, set up isomorphism calculate section power consumption with perform time relationship, obtain based on isomorphism procedure division the dynamic power consumption side of expression Method;
S2:It is single under analysis time constraints to calculate the condition that section reaches power consumption optimum, set up Heterogeneous Computing section power consumption With execution time relationship, the dynamic power consumption method for expressing based on isomery procedure division is obtained;
S3:In isomorphism calculates section program, with parallel data scale as object, analysis primary processor and OverDrive Processor ODP it Between influence of the data transfer to communication energy consumption, obtain isomorphism calculate section communication energy consumption method for expressing;
S4:Heterogeneous Computing section program in, with executing tasks parallelly as object, using the actual efficiency of heterogeneous processor with times The direct relation of feature of being engaged in, analyzes the single multiple parallel tasks for having data dependence relation in section that calculate and divides to communication energy consumption Influence, obtain Heterogeneous Computing section communication energy consumption method for expressing;
S5:With multi-core processor chip as object, using the thermal conduction characteristic of processor cores, using equivalent RC circuit side Method sets up real-time system thermal model, solves chip operating temperature;
S6:Analysis chip leakage current and the correlation of quiescent dissipation, carry out curve fitting, and obtain leakage current and chip temperature Degree, the functional relation of voltage;
S7:Two operating reference temperatures are introduced, the quadratic function of leakage current and temperature is set up, quiescent dissipation and chip is obtained The functional relation of temperature, sets up the quiescent dissipation metering method for expressing based on real time temperature management.
Further, carried out curve fitting described in step S6 and completed using HISPICE softwares.
The beneficial effects of the present invention are compared with prior art, present invention analysis concurrent program is on heterogeneous system Implementation procedure, pays close attention to the power consumption modeling of multiple parallel sections, while considering what primary processor and OverDrive Processor ODP task communication brought Communication overhead, and the influence of leakage current that chip temperature elevated band is come, from Whole Process angle, accurate count Heterogeneous parallel system work( Consumption is calculated.
Brief description of the drawings
Fig. 1 is a kind of heterogeneous system Whole Process power consumption metering method flow chart of the invention;
Fig. 2 is a kind of heterogeneous system Whole Process power consumption metering method general frame schematic diagram of the invention;
Fig. 3 is a kind of isomerism parallel class of procedures figure of heterogeneous system Whole Process power consumption metering method of the invention.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made Embodiment, belongs to the scope of protection of the invention.
Refer to Fig. 1 and Fig. 2, a kind of heterogeneous system Whole Process power consumption metering method of the invention, including three parts:
(1) set up and calculate program execution time and dynamic power consumption relation that section is divided more multiprocessor, including step:
S1:For heterogeneous multi-processor parallel processing single parallel computation section, according to same type processor or it is various not Same type processor completes to calculate the different modes of section, and analysis isomorphism calculates section program execution time to calculating section dynamic power consumption Influence, set up isomorphism calculate section power consumption with perform time relationship, obtain based on isomorphism procedure division the dynamic power consumption side of expression Method;
S2:It is single under analysis time constraints to calculate the condition that section reaches power consumption optimum, set up Heterogeneous Computing section power consumption With execution time relationship, the dynamic power consumption method for expressing based on isomery procedure division is obtained;
(2) the communication power consumption formalized description method of data transfer and multitask dynamically distributes, including step are obtained:
S3:In isomorphism calculates section program, with parallel data scale as object, analysis primary processor and OverDrive Processor ODP it Between influence of the data transfer to communication energy consumption, obtain isomorphism calculate section communication energy consumption method for expressing;
S4:Heterogeneous Computing section program in, with executing tasks parallelly as object, using the actual efficiency of heterogeneous processor with times The direct relation of feature of being engaged in, analyzes the single multiple parallel tasks for having data dependence relation in section that calculate and divides to communication energy consumption Influence, obtain Heterogeneous Computing section communication energy consumption method for expressing;
(3) chip temperature management in real time influences each other with quiescent dissipation under analysis thermal model, including step:
S5:With multi-core processor chip as object, using the thermal conduction characteristic of processor cores, using equivalent RC circuit side Method sets up real-time system thermal model, solves chip operating temperature;
S6:Analysis chip leakage current and the correlation of quiescent dissipation, carry out curve fitting, and obtain leakage current and chip temperature Degree, the functional relation of voltage;
S7:Two operating reference temperatures are introduced, the quadratic function of leakage current and temperature is set up, quiescent dissipation and chip is obtained The functional relation of temperature, sets up the quiescent dissipation metering method for expressing based on real time temperature management.
Implementation procedure of the present invention first to concurrent program on heterogeneous system carries out abstract.Wherein S represents serial computing Section, S={ s0,…,sn-1, program is divided into by n sections, s according to the concurrency for calculating sectioniRepresent i-th task amount of calculating section;C Represent communication section;R={ r0,…,rm-1, represent Heterogeneous parallel system by m classes processor group into;NjRepresent jth (0≤j≤m-1) Class processor rjQuantity;vjRepresent the speed (task amount is completed in the processor unit interval) under highest frequency;P represents parallel Calculate section (first parallel computation section is completed by primary processor, second parallel computation section by primary processor and acceleration components simultaneously Row is completed, and the 3rd parallel computation section is by acceleration components complete independently).Will be parallel by primary processor/acceleration components complete independently Calculate section and be referred to as isomorphism calculating section program, primary processor and acceleration components complete parallel computation section and are referred to as Heterogeneous Computing Duan Cheng jointly Sequence.Then concurrent program execution feature is carried out into symbol definition, as shown in Figure 3.
(1) heterogeneous system dynamic power consumption metering
In isomorphism calculates section program, if siIt is serial section, then by riThe single processor of type is completed;If siFor Parallel section, then by riAll processors of type are completed.Dynamic electric voltage can be approximate with the relation of processor frequencies be described as f =KVγ-1, wherein K and γ is the parameter related to technique.NoteTherefore dynamic power consumption PdThe α with frequency f can be regarded as The relation that power is directly proportional, i.e. Pd=Kfα.The execution time of i-th calculating section of note is ti,NiRepresent i-th and calculate section riAt class Reason device number, fiR when representing i-th calculating sectioniProcessor running frequency, isomorphism program segment program total power consumption can be expressed as
The procedural model that section is constituted is calculated for by multiple, solve makes Whole Process total under the constraint of given execution time T Power consumption reaches minimum, wherein calculating section S to anyiTime-constrain tiBe analyzed as follows:If i-th calculates section SiFor serial Section, then calculating section is only by a processor completion, now execution time satisfactionIf i-th calculates section SiFor parallel Section, then calculating section is by riAll processors of type are completed parallel, now perform time tiMeetTherefore, it is based on The calculating power consumption metering of isomorphism program can be expressed as:
In Heterogeneous Computing program, if SiIt is serial section, then by riThe single processor of type is completed;If SiFor simultaneously Row section, then completed jointly by all types of processors in system.This project is carried out mainly for CPU-GPU Heterogeneous parallel systems Research, therefore processor type only includes CPU with the classes of GPU two (assuming that the model of CPU is consistent;The model of GPU is consistent).
The execution time of i-th calculating section of note is ti, NCRepresent i-th number of calculating section CPU processor, NGRepresent i-th The individual number for calculating section GPU processors, kCAnd kGCPU and GPU processor dependent constants are represented respectively.fCAnd fGI-th is represented respectively The individual running frequency for calculating section CPU and GPU processor.Represent that jth class processor is calculated at i-th complete in the unit interval in section Into task amount.Therefore isomery program segment program total power consumption can be expressed as
Heterogeneous Computing section program power consumption optimum problem can be divided into two subproblems and be studied in principle, that is, calculate office in section Portion's power consumption optimum and Whole Process overall power are optimal.The key of first subproblem be set up calculate the optimal power consumption of section processor with The relation of execution time, second subproblem is when the execution for distributing different calculating sections in section on the basis of power consumption optimum is calculated Between.Therefore Heterogeneous Computing section program optimised power consumption problem can be summarized as general Multivariate Extreme Value problem, the calculating based on isomery program Power consumption can be expressed as:
(2) expansibility power consumption metering
In Heterogeneous parallel system, CPU and GPU is attached by PCI-E buses, and PCI-E buses do not support dynamic electric The execution speed of pressure/frequency regulation technology, i.e. Data communication operation is certain with power dissipation overhead.PCI-E buses are designated as a class special Different functional unit, the power dissipation overhead in its running is pm,0, the power dissipation overhead under idle condition is pm,1.Assume simultaneously logical Letter operation can not be interrupted, i.e., multiple Data communication operations need order to perform, because system bus is made by single traffic operation is exclusive With, therefore communication overhead is proportional with data scale;And data scale depends on two with data dependence relation simultaneously The partition strategy of row task.
1. isomorphism program segment communication power consumption metering
In isomorphism calculates section program, communication power consumption is mainly input data and passes to GPU memory spaces by CPU, exports number Restored to the introduced communication overhead of CPU memory spaces according to by GPU.Remember the execution time of traffic operationRepresent CPU and GPU it Between data communication expense, tm,0The time overhead under PCI-E bus idle states is represented, then the communication power consumption of isomorphism program can be with It is expressed as,
2. isomery program segment communication power consumption metering
In Heterogeneous Computing section program, communication power consumption is mainly in single calculating section, with many of data dependence relation Individual parallel task divides produced communication overhead.Because the actual efficiency of heterogeneous processor is directly related with task feature, because This easily produces different partition strategy between multiple tasks, and thus introduces larger communication overhead.NoteRepresent Communication overheads of the task v under dividing mode z with task v' under dividing mode z', then the communication power consumption of isomery program can be with table It is shown as,
(3) heterogeneous system quiescent dissipation metering
In order to study the thermal conduction characteristic of processor cores, heat analysis modeling is carried out using equivalent RC circuit method, the mould Type is operated the solution of temperature using equation below:
T and TambThe temperature and environment temperature of chip are represented respectively, the power consumption of chip, R when P represents time tth、CthRespectively It is equivalent thermal resistance and equivalent thermal capacitance.The system mode of processor can be divided into working condition and resting state.Only in work shape Processor just performs task under state;Otherwise, processor will be into resting state reducing power consumption and reduce own temperature.Work shape Quiescent dissipation under state can be expressed as,
Pstatic=NgateIleakageVdd (10)
Carried out curve fitting by HSPICE softwares, the leakage current related to temperature, voltage can be written as
Wherein, A, B, α, beta, gamma, δ, μ, η are empirical parameters, are determined by production technology, when work temperature 300k- Change in the normal range (NR) of 380k,Fluctuating change very little.When given VddAfterwards, by introduce two reference temperature TH and Leakage current is further reduced to TL the quadratic function of temperature.Then the quiescent dissipation related to leakage current can be with formalization representation For
Wherein,
Specific embodiment of the invention is described above.It is to be appreciated that the invention is not limited in above-mentioned Particular implementation, those skilled in the art can within the scope of the claims make various deformations or amendments, this not shadow Sound substance of the invention.
The above is the preferred embodiment of the present invention, it is noted that for those skilled in the art For, under the premise without departing from the principles of the invention, some improvements and modifications can also be made, these improvements and modifications are also considered as Protection scope of the present invention.

Claims (2)

1. a kind of heterogeneous system Whole Process power consumption metering method, it is characterised in that including step
S1:For the single parallel computation section of heterogeneous multi-processor parallel processing, according to same type processor or various inhomogeneities Type processor completes to calculate the different modes of section, and analysis isomorphism calculates shadow of the section program execution time to calculating section dynamic power consumption Ring, set up isomorphism and calculate section power consumption and perform time relationship, obtain the dynamic power consumption method for expressing based on isomorphism procedure division;
S2:It is single under analysis time constraints to calculate the condition that section reaches power consumption optimum, set up Heterogeneous Computing section power consumption and hold Row time relationship, obtains the dynamic power consumption method for expressing based on isomery procedure division;
S3:In isomorphism calculates section program, with parallel data scale as object, number between analysis primary processor and OverDrive Processor ODP Influence according to transmission to communication energy consumption, obtains isomorphism and calculates section communication energy consumption method for expressing;
S4:It is special using the actual efficiency of heterogeneous processor and task with executing tasks parallelly as object in Heterogeneous Computing section program The direct relation levied, has multiple parallel tasks division of data dependence relation to the shadow of communication energy consumption in the single calculating section of analysis Ring, obtain Heterogeneous Computing section communication energy consumption method for expressing;
S5:With multi-core processor chip as object, using the thermal conduction characteristic of processor cores, built using equivalent RC circuit method Vertical real-time system thermal model, solves chip operating temperature;
S6:The correlation of analysis chip leakage current and quiescent dissipation, carries out curve fitting, obtain leakage current and chip temperature, The functional relation of voltage;
S7:Two operating reference temperatures are introduced, the quadratic function of leakage current and temperature is set up, quiescent dissipation and chip temperature is obtained Functional relation, set up based on real time temperature management quiescent dissipation metering method for expressing.
2. heterogeneous system Whole Process power consumption metering method as claimed in claim 1, it is characterised in that carried out described in step S6 Curve matching is completed using HISPICE softwares.
CN201710020074.5A 2017-01-11 2017-01-11 A kind of heterogeneous system Whole Process power consumption metering method Pending CN106874158A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710020074.5A CN106874158A (en) 2017-01-11 2017-01-11 A kind of heterogeneous system Whole Process power consumption metering method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710020074.5A CN106874158A (en) 2017-01-11 2017-01-11 A kind of heterogeneous system Whole Process power consumption metering method

Publications (1)

Publication Number Publication Date
CN106874158A true CN106874158A (en) 2017-06-20

Family

ID=59159228

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710020074.5A Pending CN106874158A (en) 2017-01-11 2017-01-11 A kind of heterogeneous system Whole Process power consumption metering method

Country Status (1)

Country Link
CN (1) CN106874158A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107818040B (en) * 2017-09-28 2021-09-21 华南师范大学 Analysis method, system and device suitable for guiding parallelization of correlation algorithm
WO2021227418A1 (en) * 2020-05-11 2021-11-18 深圳先进技术研究院 Task deployment method and device based on multi-board fpga heterogeneous system
CN114546666A (en) * 2022-04-25 2022-05-27 沐曦科技(北京)有限公司 Power consumption distribution method based on multiple computing devices
CN117349029A (en) * 2023-12-04 2024-01-05 浪潮电子信息产业股份有限公司 Heterogeneous computing system, energy consumption determining method and device, electronic equipment and medium

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106293003A (en) * 2016-08-05 2017-01-04 广东工业大学 A kind of heterogeneous system dynamic power consumption optimization method based on AOV gateway key path query

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106293003A (en) * 2016-08-05 2017-01-04 广东工业大学 A kind of heterogeneous system dynamic power consumption optimization method based on AOV gateway key path query

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ZHUOWEI WANG: ""An architecture-level graphics processing unit energy model"", 《WILEY ONLINE LIBRARY》 *
王桂彬: ""大规模异构并行系统软件低功耗优化关键技术研究"", 《中国博士学位论文全文数据库 信息科技辑》 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107818040B (en) * 2017-09-28 2021-09-21 华南师范大学 Analysis method, system and device suitable for guiding parallelization of correlation algorithm
WO2021227418A1 (en) * 2020-05-11 2021-11-18 深圳先进技术研究院 Task deployment method and device based on multi-board fpga heterogeneous system
CN114546666A (en) * 2022-04-25 2022-05-27 沐曦科技(北京)有限公司 Power consumption distribution method based on multiple computing devices
CN114546666B (en) * 2022-04-25 2022-07-19 沐曦科技(北京)有限公司 Power consumption distribution method based on multiple computing devices
CN117349029A (en) * 2023-12-04 2024-01-05 浪潮电子信息产业股份有限公司 Heterogeneous computing system, energy consumption determining method and device, electronic equipment and medium

Similar Documents

Publication Publication Date Title
CN106874158A (en) A kind of heterogeneous system Whole Process power consumption metering method
CN103226487B (en) Towards Data distribution8 and the locality optimizing methods of isomery many core dynamic data attemper structure
CN103164190B (en) A kind of fast parallelization method of full distributed river basin ecological hydrology model
Murali et al. An application-specific design methodology for on-chip crossbar generation
Tang et al. CPU–GPU utilization aware energy-efficient scheduling algorithm on heterogeneous computing systems
CN111274016A (en) Application partitioning and scheduling method of dynamic partial reconfigurable system based on module fusion
Moulik et al. SEAMERS: A semi-partitioned energy-aware scheduler for heterogeneous multicore real-time systems
Gurumani et al. High-level synthesis of multiple dependent CUDA kernels on FPGA
CN105426163A (en) Single data stream quantile processing method based on MIC coprocessor
CN103116526B (en) The maximum power dissipation control method of high-performance heterogeneous Computing machine
Chen et al. Clustering scheduling for hardware tasks in reconfigurable computing systems
Rodríguez et al. Execution modeling in self-aware FPGA-based architectures for efficient resource management
Rodríguez et al. Lightweight asynchronous scheduling in heterogeneous reconfigurable systems
Prabhaker et al. Real-time task schedulers for a high-performance multi-core system
Du et al. Feature-aware task scheduling on CPU-FPGA heterogeneous platforms
CN108009121B (en) Dynamic multi-core configuration method for application
CN116303219A (en) Grid file acquisition method and device and electronic equipment
Marowka Energy-aware modeling of scaled heterogeneous systems
McLaughlin et al. A power characterization and management of gpu graph traversal
Silberstein et al. An exact algorithm for energy-efficient acceleration of task trees on CPU/GPU architectures
Mariyappan et al. An Efficient Implementation of Divergence State Estimation with Biogeography-Based Optimization (DSEBBO) Framework in FPGA-Based Multiprocessor System
Qureshi et al. Genome sequence alignment-design space exploration for optimal performance and energy architectures
Valentin et al. Response time schedulability analysis for hard real-time systems accounting dvfs latency on heterogeneous cluster-based platform
Li et al. HeteroYARN: a heterogeneous FPGA-accelerated architecture based on YARN
Bingham et al. Modeling energy-time trade-offs in VLSI computation

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20170620