CN106850189A - The method and device of operand in a kind of reduction SM3 cryptographic Hash algorithms - Google Patents

The method and device of operand in a kind of reduction SM3 cryptographic Hash algorithms Download PDF

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Publication number
CN106850189A
CN106850189A CN201710073997.7A CN201710073997A CN106850189A CN 106850189 A CN106850189 A CN 106850189A CN 201710073997 A CN201710073997 A CN 201710073997A CN 106850189 A CN106850189 A CN 106850189A
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value
formula
iterative
cryptographic hash
bit
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徐�明
熊晓明
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Guangdong University of Technology
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Guangdong University of Technology
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry
    • H04L2209/125—Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations

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  • Computer Networks & Wireless Communication (AREA)
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Abstract

The embodiment of the invention discloses a kind of method and device of operand in reduction SM3 cryptographic Hash algorithms, more serial addition computing is substituted using parallel addition operations, serial addition number of calculations is reduced, so as to reduce computing time delay, SM3 cryptographic Hash algorithm arithmetic speeds is improved.

Description

The method and device of operand in a kind of reduction SM3 cryptographic Hash algorithms
Technical field
The present invention relates to internet of things intelligent household safety chip application field, more particularly to a kind of reduction SM3 cryptographic Hash The method and device of operand in algorithm.
Background technology
Smart home is in a kind of early stage of explosive growth, Internet of product be today's society most main flow product it One, live closely bound up with human world.Internet of product be also safely we need now consider it is most important because One of element.Core technology-the cryptographic technique of protection Internet of Things safety also highlights all the more its importance.Cryptographic technique one from ancient times to the present Directly all used widely, with the fast development of the cyber-net communication technology, increasing information needs to be subject to Strict secrecy, cryptography has also gradually come into the daily life of the public.Later 1970s, hash function is drawn Enter cryptography, it is indispensable at the aspect such as data integrity, construction digital signature and certificate scheme.
SM3 cryptographic Hash algorithms are the cryptographic Hash standards for business that State Commercial Cryptography Administration of China announces for 2010.Should By message filling, extension, Iteration Contraction and the several parts of Hash Value, wherein Iteration Contraction is cryptographic Hash algorithm to cryptographic algorithm In core the most part.The following is the partial routine of cipher algorithm iteration compression：
SS1j←((Aj-1＜ ＜ ＜ 12)+Ej-1+(Tj＜ ＜ ＜ j)) ＜ ＜ ＜ 7
TT1j←FFj(Aj-1, Bj-1, Cj-1)+Dj-1+SS2j+W0
TT2j←GGj(Ej-1, Fj-1Gj-1)+Hj-1+SS1j+Wj
Dj←Cj-1
Cj←Bj-1＜ ＜ ＜ 9
Bj←Aj-1
Aj←TT1j
Hj←Gj-1
Gj←Fj-1＜ ＜ ＜ 19
Fj←Ej-1
Ej←P0(TT2j)
FFj(Aj-1, Bj-1, Cj-1) and GGj(Ej-1, Fj-1, Gj-1) Boolean function is, its function expression is respectively：
P0And P (X)1(X) permutation function
X in above formula is word.
WjWith W 'jFor message expands word
Wherein, ＜ ＜ ＜ 12, ＜ ＜ ＜ j, ＜ ＜ ＜ 7, ＜ ＜ ＜ 15, ＜ ＜ ＜ 9, ＜ ＜ ＜ 19 are respectively ring shift left 12nd, the bit arithmetic of j, 7,15,9,19,It is 32 bit XORs, ∧ is 32 bits and computing, ∨ is 32 bits or computing,It is 32 bit inverses.
Used as the core of algorithm, the operation efficiency of the part of cipher algorithm iteration compression seems particularly heavy in the algorithm Will.Circuit as shown in Figure 1 is the close algorithm circuit diagram of existing state, often calculates an iterative process of A and E, is required for using 5 strings Row add operation.Each pair V carries out an iteration computing, is required for this 8 variable words to ABCDEFGH to carry out 64 interative computations, So the total time delay for producing is very big, the arithmetic speed of cryptographic algorithm is also had a strong impact on.
The content of the invention
A kind of method and device of operand in reduction SM3 cryptographic Hash algorithms is the embodiment of the invention provides, using simultaneously Row add operation substitutes more serial addition computing, reduces serial addition number of calculations, so as to reduce computing time delay, improves SM3 cryptographic Hash algorithm arithmetic speeds.
The method that the embodiment of the invention provides operand in a kind of reduction SM3 cryptographic Hash algorithms, including：
S1, B is grouped according to preset message(i), the first formula and the second formula determine the extension of message word of 32 bit lengths W0-W67, W '0-W′63, first formula isIt is described Second formula isWherein i is the first iterations,It is permutation function；
S2, respectively by the initial value of variable word A, B, C, D, E, F, G, H, X, Y, Z be initialized as A-1, B-1, C-1, D-1, Secondary iteration number of times j is simultaneously initialized as 0 by E-1, F-1, G-1, H-1, X-1, Y-1, Z-1；
S3, according to the 3rd preset formulaDetermine the constant Tj of 32 bit lengths；
S4, first interative computation is carried out according to preset iterative formula, determine intermediate variable word SS1, SS2, TT1, TT2, Iteration j value SS1j, SS2j of X, Y, Z and each variable word A, B, C, D, E, F, G, H, TT1j, TT2j, Xj, Yj, Zj, Aj, Bj、Cj、Dj、Ej、Fj、Gj、Hj；
The iterative formula is specifically included
SS1j←((Aj-1＜ ＜ ＜ 12)+Xj-1) ＜ ＜ ＜ 7,
TT1j←FFj(Aj-1, Bj-1, Cj-1)+SS2j+Pj-1,
TT2j←GGj(Ej-1, Fj-1, Gj-1)+SS1j+Qj-1,
Dj←Cj-1,
Cj←Bj-1＜ ＜ ＜ 9,
Bj←Aj-1,
Aj←TT1j,
Hj←Gj-1,
Gj←Fj-1＜ ＜ ＜ 19,
Fj←Ej-1,
Ej←P0(TT2j),
Xj←Ej-1+(Tj+1＜ ＜ ＜ (j+1)),
Yj←Cj-1+W′j+1,
Zj←Gj-1+Wj+1,
Wherein, X-1=E-1+(T0＜ ＜ ＜ j), Y-1=D-1+W′0、Z-1=H-1+W0, Aj-1, Bj-1, Cj-1, Dj-1, Ej- 1st, Fj-1, Gj-1, Hj-1 are -1 iterative value of jth of relevant variable word；Xj-1, Yj-1, Z j-1 be respectively the jth of X, Y and Z- 1 iterative value, FFj(Aj-1, Bj-1, Cj-1) and GGj(Ej-1, Fj-1, Gj-1) Boolean function is,
P0(TT2j) be Permutation function,＜ ＜ ＜ 12, ＜ ＜ ＜ j, ＜ ＜ ＜ 7, ＜ ＜ ＜ 15, ＜ ＜ ＜ 9, ＜ ＜ ＜ 19 are respectively ring shift left 12, j, 7,15,9,19 bit arithmeticsIt is 32 ratios Special XOR, ∧ be 32 bits and computing, ∨ be 32 bits or computing,It is 32 bit inverses；
S5, judges whether j is equal to 63；
If j is equal to 63, export iteration j value SS1j, SS2j of each variable word A, B, C, D, E, F, G, H, TT1j, TT2j、Xj、Yj、Zj、Aj、Bj、Cj、Dj、Ej、Fj、Gj、Hj；
If values of the j less than 63, j increases by 1 and then performs step S3.
Preferably, also included before step S1：
S0, is initialized as the initial value of the first iterations i 0 and initializes and first iterations i pairs The 0th iterative value V (0) of the compression function V for answering.
Preferably, step S1 also includes：
B is grouped according to preset message(i)Determine parameter N.
Preferably, also include after step s 5：
S6, the group that puts in order using the sequencing of Aj, Bj, Cj, Dj, Ej, Fj, Gj, Hj as bit from high to low The variable that conjunction is obtained carries out XOR with the ith iteration value of the compression function V, obtains the i+1 of the compression function V Secondary iterative value V(i+1)；
S7, judges whether i is equal to N-1；
If i is equal to N-1, V is exported(N)；
If i is less than N-1, the value of i is added 1 and step S1 is performed.
A kind of device of operand in reduction SM3 cryptographic Hash algorithms is the embodiment of the invention provides, including：
First determining unit, for being grouped B according to preset message(i), the first formula and the second formula determine 32 bit longs The extension of message word W of degree0-W67, W '0-W′63, first formula is Second formula isWherein i is the first iterations,It is displacement Function；
First initialization unit, for being respectively initialized as the initial value of variable word A, B, C, D, E, F, G, H, X, Y, Z Secondary iteration number of times j is simultaneously initialized as 0 by A-1, B-1, C-1, D-1, E-1, F-1, G-1, H-1, X-1, Y-1, Z-1；
Second determining unit, for according to the 3rd preset formulaDetermine 32 bits The constant Tj of length；
3rd determining unit, for carrying out first interative computation according to preset iterative formula, determines intermediate variable word Iteration j value SS1j, SS2j of SS1, SS2, TT1, TT2, X, Y, Z and each variable word A, B, C, D, E, F, G, H, TT1j, TT2j、Xj、Yj、Zj、Aj、Bj、Cj、Dj、Ej、Fj、Gj、Hj；
The iterative formula is specifically included
SS1j←((Aj-1＜ ＜ ＜ 12)+Xj-1) ＜ ＜ ＜ 7,
TT1j←FFj(Aj-1, Bj-1, Cj-1)+SS2j+Pj-1,
TT2j←GGj(Ej-1, Fj-1, Gj-1)+SS1j+Qj-1,
Dj←Cj-1,
Cj←Bj-1＜ ＜ ＜ 9,
Bj←Aj-1,
Aj←TT1j,
Hj←Gj-1,
Gj←Fj-1＜ ＜ ＜ 19,
Fj←Ej-1,
Ej←P0(TT2j),
Xj←Ej-1+(Tj+1＜ ＜ ＜ (j+1)),
Yj←Cj-1+W′j+1,
Zj←Gj-1+Wj+1,
Wherein, X-1=E-1+(T0＜ ＜ ＜ j), Y-1=D-1+W′0、Z-1=H-1+W0, Aj-1, Bj-1, Cj-1, Dj-1, Ej- 1st, Fj-1, Gj-1, Hj-1 are -1 iterative value of jth of relevant variable word；Xj-1, Yj-1, Z j-1 be respectively the jth of X, Y and Z- 1 iterative value, FFj(Aj-1, Bj-1, Cj-1) and GGj(Ej-1, Fj-1, Gj-1) Boolean function is,
P0(TT2j) be Permutation function,＜ ＜ ＜ 12, ＜ ＜ ＜ j, ＜ ＜ ＜ 7, ＜ ＜ ＜ 15, ＜ ＜ ＜ 9, ＜ ＜ ＜ 19 are respectively ring shift left 12, j, 7,15,9,19 bit arithmeticsIt is 32 ratios Special XOR, ∧ be 32 bits and computing, ∨ be 32 bits or computing,It is 32 bit inverses；
Judging unit, for judging whether j is equal to 63；
If j is equal to 63, export iteration j value SS1j, SS2j of each variable word A, B, C, D, E, F, G, H, TT1j, TT2j、Xj、Yj、Zj、Aj、Bj、Cj、Dj、Ej、Fj、Gj、Hj；
If values of the j less than 63, j increases by 1 and then performs step S3.
Preferably,
The device of operand also includes in the reduction SM3 cryptographic Hash algorithms：
Second initialization unit, for by the initial value of the first iterations i be initialized as 0 and initialize with it is described The 0th iterative value V (0) of the corresponding compression function V of the first iterations i.
Preferably,
First determining unit also includes：
4th determination subelement, for being grouped B according to preset message(i)Determine parameter N.
Preferably,
The device of operand also includes in the reduction SM3 cryptographic Hash algorithms：
Computing unit, for using the sequencing of Aj, Bj, Cj, Dj, Ej, Fj, Gj, Hj as bit from high to low The variable that the combination that puts in order is obtained carries out XOR with the ith iteration value of the compression function V, obtains the compression letter The i+1 time iterative value V of number V(i+1)；
Second judging unit, for judging whether i is equal to N-1；
If i is equal to N-1, V is exported(N)；
If i is less than N-1, the value of i is added 1 and step S1 is performed.
As can be seen from the above technical solutions, the embodiment of the present invention has advantages below：
A kind of method and device of operand in reduction SM3 cryptographic Hash algorithms is the embodiment of the invention provides, using simultaneously Row add operation substitutes more serial addition computing, reduces serial addition number of calculations, so as to reduce computing time delay, improves SM3 cryptographic Hash algorithm arithmetic speeds.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing The accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this Some embodiments of invention, for those of ordinary skill in the art, without having to pay creative labor, may be used also Other accompanying drawings are obtained with according to these accompanying drawings.
Fig. 1 is existing SM3 cryptographic Hash algorithm iteration Process circuitry figure；
Fig. 2 is the first reality of the method for operand in a kind of reduction SM3 cryptographic Hash algorithms provided in an embodiment of the present invention Apply the schematic flow sheet of example；
Fig. 3 is the second reality of the method for operand in a kind of reduction SM3 cryptographic Hash algorithms provided in an embodiment of the present invention Apply the schematic flow sheet of example；
Fig. 4 is the second reality of the method for operand in a kind of reduction SM3 cryptographic Hash algorithms provided in an embodiment of the present invention Apply the corresponding iterative process circuit diagram of example；
Fig. 5 is the first reality of the device of operand in a kind of reduction SM3 cryptographic Hash algorithms provided in an embodiment of the present invention Apply the structural representation of example；
Fig. 6 is the second reality of the device of operand in a kind of reduction SM3 cryptographic Hash algorithms provided in an embodiment of the present invention Apply the structural representation of example.
Specific embodiment
A kind of method and device of operand in reduction SM3 cryptographic Hash algorithms is the embodiment of the invention provides, using simultaneously Row add operation substitutes more serial addition computing, reduces serial addition number of calculations, so as to reduce computing time delay, improves SM3 cryptographic Hash algorithm arithmetic speeds.
To enable that goal of the invention of the invention, feature, advantage are more obvious and understandable, below in conjunction with the present invention Accompanying drawing in embodiment, is clearly and completely described, it is clear that disclosed below to the technical scheme in the embodiment of the present invention Embodiment be only a part of embodiment of the invention, and not all embodiment.Based on the embodiment in the present invention, this area All other embodiment that those of ordinary skill is obtained under the premise of creative work is not made, belongs to protection of the present invention Scope.
Fig. 2 is referred to, a kind of method first of operand in reduction SM3 cryptographic Hash algorithms is the embodiment of the invention provides Embodiment, including：
S1, B is grouped according to preset message(i), the first formula and the second formula determine the extension of message word of 32 bit lengths W0-W67, W '0-W′63, the first formula isSecond formula ForWherein i is the first iterations,It is permutation function；
In embodiments of the present invention, it is necessary first to which B is grouped according to preset message(i), the first formula and the second formula determine The extension of message word W of 32 bit lengths0-W67, W '0-W′63, the first formula isSecond formula isWherein i is the One iterations,It is permutation function, W0-W67, W '0-W′63Refer to W0To W67, W '0-W′63 Refer to W '0To W '63。
S2, respectively by the initial value of variable word A, B, C, D, E, F, G, H, X, Y, Z be initialized as A-1, B-1, C-1, D-1, Secondary iteration number of times j is simultaneously initialized as 0 by E-1, F-1, G-1, H-1, X-1, Y-1, Z-1；
In embodiments of the present invention, B is being grouped according to preset message(i), the first formula and the second formula determine 32 bits The extension of message word W of length0-W67, W '0-W′63Afterwards, in addition it is also necessary to respectively by the first of variable word A, B, C, D, E, F, G, H, X, Y, Z Initial value is initialized as A-1, B-1, C-1, D-1, E-1, F-1, G-1, H-1, X-1, Y-1, Z-1 and secondary iteration number of times j is initial Turn to 0.
S3, according to the 3rd preset formulaDetermine the constant Tj of 32 bit lengths；
In embodiments of the present invention, the initial value of variable word A, B, C, D, E, F, G, H, X, Y, Z is being initialized as respectively Simultaneously be initialized as secondary iteration number of times j after 0 by A-1, B-1, C-1, D-1, E-1, F-1, G-1, H-1, X-1, Y-1, Z-1, also Need according to the 3rd preset formulaDetermine the constant Tj of 32 bit lengths.
S4, first interative computation is carried out according to preset iterative formula, determine intermediate variable word SS1, SS2, TT1, TT2, Iteration j value SS1j, SS2j of X, Y, Z and each variable word A, B, C, D, E, F, G, H, TT1j, TT2j, Xj, Yj, Zj, Aj, Bj、Cj、Dj、Ej、Fj、Gj、Hj；
Iterative formula is specifically included
SS1j←((Aj-1＜ ＜ ＜ 12)+Xj-1) ＜ ＜ ＜ 7,
TT1j←FFj(Aj-1, Bj-1, Cj-1)+SS2j+Pj-1,
TT2j←GGj(Ej-1, Fj-1, Gj-1)+SS1j+Qj-1,
Dj←Cj-1,
Cj←Bj-1＜ ＜ ＜ 9,
Bj←Aj-1,
Aj←TT1j,
Hj←Gj-1,
Gj←Fj-1＜ ＜ ＜ 19,
Fj←Ej-1,
Ej←P0(TT2j),
Xj←Ej-1+(Tj+1＜ ＜ ＜ (j+1)),
Yj←Cj-1+W′j+1,
Zj←Gj-1+Wj+1,
Wherein, X-1=E-1+(T0＜ ＜ ＜ j), Y-1=D-1+W′0、Z-1=H-1+W0, Aj-1, Bj-1, Cj-1, Dj-1, Ej- 1st, Fj-1, Gj-1, Hj-1 are -1 iterative value of jth of relevant variable word；Xj-1, Yj-1, Z j-1 be respectively the jth of X, Y and Z- 1 iterative value, FFj(Aj-1, Bj-1, Cj-1) and GGj(Ej-1, Fj-1, Gj-1) Boolean function is,
P0（TT2j) be Permutation function,＜ ＜ ＜ 12, ＜ ＜ ＜ j, ＜ ＜ ＜ 7, ＜ ＜ ＜ 15, ＜ ＜ ＜ 9, ＜ ＜ ＜ 19 are respectively ring shift left 12, j, 7,15,9,19 bit arithmeticsIt is 32 ratios Special XOR, ∧ be 32 bits and computing, V be 32 bits or computing,It is 32 bit inverses；
In embodiments of the present invention, according to the 3rd preset formulaDetermine 32 ratios After the constant Tj of bit length, in addition it is also necessary to carry out first interative computation according to preset iterative formula, intermediate variable word is determined Iteration j value SS1j, SS2j of SS1, SS2, TT1, TT2, X, Y, Z and each variable word A, B, C, D, E, F, G, H, TT1j, TT2j、Xj、Yj、Zj、Aj、Bj、Cj、Dj、Ej、Fj、Gj、Hj。
S5, judges whether j is equal to 63；
If j is equal to 63, export iteration j value SS1j, SS2j of each variable word A, B, C, D, E, F, G, H, TT1j, TT2j、Xj、Yj、Zj、Aj、Bj、Cj、Dj、Ej、Fj、Gj、Hj；
If values of the j less than 63, j increases by 1 and then performs step S3；
In embodiments of the present invention, first interative computation is being carried out according to preset iterative formula, is determining intermediate variable word Iteration j value SS1j, SS2j of SS1, SS2, TT1, TT2, X, Y, Z and each variable word A, B, C, D, E, F, G, H, TT1j, After TT2j, Xj, Yj, Zj, Aj, Bj, Cj, Dj, Ej, Fj, Gj, Hj, in addition it is also necessary to judge whether j is equal to 63；
If j is equal to 63, export iteration j value SS1j, SS2j of each variable word A, B, C, D, E, F, G, H, TT1j, TT2j、Xj、Yj、Zj、Aj、Bj、Cj、Dj、Ej、Fj、Gj、Hj；
If values of the j less than 63, j increases by 1 and then performs step S3；
It should be noted that used as loop iteration procedure body part, step S1 to step S5 needs iteration 64 times.Every In secondary iterative process, intermediate variable word SS1, SS2, TT1, TT2, X, Y, Z and extension of message word W must be first calculated0-W67, W '0- W′63, intermediate variable word X, Y and the Z used required for the iteration j value Aj and Ej that determine variable word A and E be before once change Iterative value Xj-1, Yj-1, Zj-1 produced by generation, and determine iterative value Xj, Yj, Zj for calculating Aj+1 and Ej+1.Can see Iteration need to carry out an add operation each time to go out X, Y and Z.
The value that variable word A, B, C, D, E, F, G, H carry out j during 64 iteration is 63, and now Yj←Cj-1+W′j+1, now Y63 occurs overflow error can be stopped calculating, and obtain the iteration result A63 of each variable word, B63, C63, D63, E63, F63, G63、H63。
Fig. 3 and Fig. 4 is referred to, a kind of side of operand in reduction SM3 cryptographic Hash algorithms is the embodiment of the invention provides Method second embodiment, including：
101, the initial value of the first iterations i is initialized as 0 and compression corresponding with the first iterations i is initialized The 0th iterative value V (0) of function V；
In embodiments of the present invention, it is necessary first to the initial value of the first iterations i is initialized as 0 and is initialized and the The 0th iterative value V (0) of the corresponding compression function V of one iterations i, V(0)It is the 7380166f represented with 16 systems 4914b2b9 172442d7da8a0600a96f30bc 163138aa e38dee4d b0fb0e4e。
102, B is grouped according to preset message(i), the first formula and the second formula determine the extension of message word of 32 bit lengths W0-W67, W '0-W′63With parameter N, the first formula is Second formula isWherein i is the first iterations,It is permutation function；
In embodiments of the present invention, the initial value of the first iterations i is being initialized as 0 and is being initialized and the first iteration After the 0th iterative value V (0) of the corresponding compression function V of number of times i, in addition it is also necessary to be grouped B according to preset message(i), it is first public Formula and the second formula determine the extension of message word W of 32 bit lengths0-W67, W '0-W′63With parameter N, the first formula isSecond formula isWherein i is the One iterations,It is permutation function.
103, respectively by the initial value of variable word A, B, C, D, E, F, G, H, X, Y, Z be initialized as A-1, B-1, C-1, D-1, Secondary iteration number of times j is simultaneously initialized as 0 by E-1, F-1, G-1, H-1, X-1, Y-1, Z-1；
In embodiments of the present invention, B is being grouped according to preset message(i), the first formula and the second formula determine 32 bits The extension of message word W of length0-W67, W '0-W′63Afterwards, in addition it is also necessary to respectively by the first of variable word A, B, C, D, E, F, G, H, X, Y, Z Initial value is initialized as A-1, B-1, C-1, D-1, E-1, F-1, G-1, H-1, X-1, Y-1, Z-1 and secondary iteration number of times j is initial Turn to 0.
104, according to the 3rd preset formulaDetermine the constant Tj of 32 bit lengths；
In embodiments of the present invention, the initial value of variable word A, B, C, D, E, F, G, H, X, Y, Z is being initialized as respectively Simultaneously be initialized as secondary iteration number of times j after 0 by A-1, B-1, C-1, D-1, E-1, F-1, G-1, H-1, X-1, Y-1, Z-1, also Need according to the 3rd preset formulaDetermine the constant Tj of 32 bit lengths.
105, first interative computation is carried out according to preset iterative formula, determine intermediate variable word SS1, SS2, TT1, TT2, Iteration j value SS1j, SS2j of X, Y, Z and each variable word A, B, C, D, E, F, G, H, TT1j, TT2j, Xj, Yj, Zj, Aj, Bj、Cj、Dj、Ej、Fj、Gj、Hj；
Iterative formula is specifically included
SS1j←((Aj-1＜ ＜ ＜ 12)+Xj-1) ＜ ＜ ＜ 7,
TT1j←FFj(Aj-1, Bj-1, Cj-1)+SS2j+Pj-1,
TT2j←GGj(Ej-1, Fj-1, Gj-1)+SS1j+Qj-1,
Dj←Cj-1,
Cj←Bj-1＜ ＜ ＜ 9,
Bj←Aj-1,
Aj←TT1j,
Hj←Gj-1,
Gj←Fj-1＜ ＜ ＜ 19,
Fj←Ej-1,
Ej←P0(TT2j),
Xj←Ej-1+(Tj+1＜ ＜ ＜ (j+1)),
Yj←Cj-1+W′j+1,
Zj←Gj-1+Wj+1,
Wherein, X-1=E-1+(T0＜ ＜ ＜ j), Y-1=D-1+W′0、Z-1=H-1+W0, Aj-1, Bj-1, Cj-1, Dj-1, Ej- 1st, Fj-1, Gj-1, Hj-1 are -1 iterative value of jth of relevant variable word；Xj-1, Yj-1, Z j-1 be respectively the jth of X, Y and Z- 1 iterative value, FFj(Aj-1, Bj-1, Cj-1) and GGj(Ej-1, Fj-1, Gj-1) Boolean function is,
P0(TT2j) be Permutation function,＜ ＜ ＜ 12, ＜ ＜ ＜ j, ＜ ＜ ＜ 7, ＜ ＜ ＜ 15, ＜ ＜ ＜ 9, ＜ ＜ ＜ 19 are respectively ring shift left 12, j, 7,15,9,19 bit arithmeticsIt is 32 ratios Special XOR, ∧ be 32 bits and computing, ∨ be 32 bits or computing,It is 32 bit inverses；
In embodiments of the present invention, according to the 3rd preset formulaDetermine 32 ratios After the constant Tj of bit length, in addition it is also necessary to carry out first interative computation according to preset iterative formula, intermediate variable word is determined Iteration j value SS1j, SS2j of SS1, SS2, TT1, TT2, X, Y, Z and each variable word A, B, C, D, E, F, G, H, TT1j, TT2j、Xj、Yj、Zj、Aj、Bj、Cj、Dj、Ej、Fj、Gj、Hj。
106, judge whether j is equal to 63；
If j is equal to 63, export iteration j value SS1j, SS2j of each variable word A, B, C, D, E, F, G, H, TT1j, TT2j、Xj、Yj、Zj、Aj、Bj、Cj、Dj、Ej、Fj、Gj、Hj；
If values of the j less than 63, j increases by 1 and then performs step 104.
In embodiments of the present invention, first interative computation is being carried out according to preset iterative formula, is determining intermediate variable word Iteration j value SS1j, SS2j of SS1, SS2, TT1, TT2, X, Y, Z and each variable word A, B, C, D, E, F, G, H, TT1j, After TT2j, Xj, Yj, Zj, Aj, Bj, Cj, Dj, Ej, Fj, Gj, Hj, in addition it is also necessary to judge whether j is equal to 63；
If j is equal to 63, export iteration j value SS1j, SS2j of each variable word A, B, C, D, E, F, G, H, TT1j, TT2j、Xj、Yj、Zj、Aj、Bj、Cj、Dj、Ej、Fj、Gj、Hj；
If values of the j less than 63, j increases by 1 and then performs step 104.
107, the group that puts in order using the sequencing of Aj, Bj, Cj, Dj, Ej, Fj, Gj, Hj as bit from high to low The variable that conjunction is obtained carries out XOR with the ith iteration value of compression function V, obtains the i+1 time iterative value of compression function V V(i+1)；
In embodiments of the present invention, judge j whether be equal to 63 after, in addition it is also necessary to by Aj, Bj, Cj, Dj, Ej, Fj, Gj, Variable and the ith iteration of compression function V that put in order combination of the sequencing of Hj as bit from high to low is obtained Value carries out XOR, obtains the i+1 time iterative value V of compression function V(i+1)。
108, judge whether i is equal to N-1；
If i is equal to N-1, V is exported(N)；
If i is less than N-1, the value of i is added 1 and step 102 is performed；
In embodiments of the present invention, using the sequencing of Aj, Bj, Cj, Dj, Ej, Fj, Gj, Hj as bit by height The variable obtained to the low combination that puts in order carries out XOR with the ith iteration value of compression function V, obtains compression function The i+1 time iterative value V of V(i+1)Afterwards, in addition it is also necessary to judge whether i is equal to N-1；
If i is equal to N-1, V is exported(N)；
If i is less than N-1, the value of i is added 1 and step 102 is performed.
In embodiments of the present invention, as shown in figure 4, Fig. 4 is a kind of reduction SM3 cryptographic Hash provided in an embodiment of the present invention The corresponding iterative process circuit diagram of the second embodiment of the method for operand in algorithm, comparison diagram 4 and Fig. 1 can be seen that this hair Bright not changed in adder quantity, present invention optimization is circuit structure, from 2 of path A and E common circuit Serial adder becomes parallel adder, respective original 3 serial adders is all become into parallel mode, by original key 5 serial adders on path have been reduced to 3 serial adders, greatly reduce serial addition computing in critical path Quantity, improve the efficiency of algorithm.
Fig. 5 is referred to, the of the device of operand in a kind of reduction SM3 cryptographic Hash algorithms is the embodiment of the invention provides One embodiment, including：
First determining unit 501, for being grouped B according to preset message(i), the first formula and the second formula determine 32 bit longs The extension of message word W of degree0-W67, W '0-W′63, the first formula is Second formula isWherein i is the first iterations,It is permutation function；
First initialization unit 502, for respectively initializing the initial value of variable word A, B, C, D, E, F, G, H, X, Y, Z 0 is initialized as A-1, B-1, C-1, D-1, E-1, F-1, G-1, H-1, X-1, Y-1, Z-1 and by secondary iteration number of times j；
Second determining unit 503, for according to the 3rd preset formulaDetermine 32 The constant Tj of bit length；
3rd determining unit 504, for carrying out first interative computation according to preset iterative formula, determines intermediate variable word Iteration j value SS1j, SS2j of SS1, SS2, TT1, TT2, X, Y, Z and each variable word A, B, C, D, E, F, G, H, TT1j, TT2j、Xj、Yj、Zj、Aj、Bj、Cj、Dj、Ej、Fj、Gj、Hj；
Iterative formula is specifically included
SS1j←((Aj-1＜ ＜ ＜ 12)+Xj-1) ＜ ＜ ＜ 7,
TT1j←FFj(Aj-1, Bj-1, Cj-1)+SS2j+Pj-1,
TT2j←GGj(Ej-1, Ej-1, Gj-1)+SS1j+Qj-1,
Dj←Cj-1,
Cj←Bj-1＜ ＜ ＜ 9,
Bj←Aj-1,
Aj←TT1j,
Hj←Gj-1,
Gj←Fj-1＜ ＜ ＜ 19,
Fj←Ej-1,
Ej←P0(TT2j),
Xj←Ej-1+(Tj+1＜ ＜ ＜ (j+1)),
Yj←Cj-1+W′j+1,
Zj←Gj-1+Wj+1,
Wherein, X-1=E-1+(T0＜ ＜ ＜ j), Y-1=D-1+W′0、Z-1=H-1+W0, Aj-1, Bj-1, Cj-1, Dj-1, Ej- 1st, Fj-1, Gj-1, Hj-1 are -1 iterative value of jth of relevant variable word；Xj-1, Yj-1, Z j-1 be respectively the jth of X, Y and Z- 1 iterative value, FFj(Aj-1, Bj-1, Cj-1) and GGj(Ej-1, Fj-1, Gj-1) Boolean function is,
P0(TT2j) be Permutation function,＜ ＜ ＜ 12, ＜ ＜ ＜ j, ＜ ＜ ＜ 7, ＜ ＜ ＜ 15, ＜ ＜ ＜ 9, ＜ ＜ ＜ 19 are respectively ring shift left 12, j, 7,15,9,19 bit arithmeticsIt is 32 ratios Special XOR, ∧ be 32 bits and computing, ∨ be 32 bits or computing,It is 32 bit inverses；
Judging unit 505, for judging whether j is equal to 63；
If j is equal to 63, export iteration j value SS1j, SS2j of each variable word A, B, C, D, E, F, G, H, TT1j, TT2j、Xj、Yj、Zj、Aj、Bj、Cj、Dj、Ej、Fj、Gj、Hj；
If values of the j less than 63, j increases by 1 and then performs step S3.
Fig. 6 is referred to, the of the device of operand in a kind of reduction SM3 cryptographic Hash algorithms is the embodiment of the invention provides Two embodiments, including：
Second initialization unit 601, for the initial value of the first iterations i being initialized as into 0 and being initialized and first The 0th iterative value V (0) of the corresponding compression function V of iterations i.
First determining unit 602, for being grouped B according to preset message(i), the first formula and the second formula determine 32 bit longs The extension of message word W of degree0-W67, W '0-W′63, the first formula is Second formula isWherein i is the first iterations,It is permutation function；
First initialization unit 603, for respectively initializing the initial value of variable word A, B, C, D, E, F, G, H, X, Y, Z 0 is initialized as A-1, B-1, C-1, D-1, E-1, F-1, G-1, H-1, X-1, Y-1, Z-1 and by secondary iteration number of times j；
Second determining unit 604, for according to the 3rd preset formulaDetermine 32 The constant Tj of bit length；
3rd determining unit 605, for carrying out first interative computation according to preset iterative formula, determines intermediate variable word Iteration j value SS1j, SS2j of SS1, SS2, TT1, TT2, X, Y, Z and each variable word A, B, C, D, E, F, G, H, TT1j, TT2j、Xj、Yj、Zj、Aj、Bj、Cj、Dj、Ej、Fj、Gj、Hj；
Iterative formula is specifically included
SS1j←((Aj-1＜ ＜ ＜ 12)+Xj-1) ＜ ＜ ＜ 7,
TT1j←FFj(Aj-1, Bj-1, Cj-1)+SS2j+Pj-1,
TT2j←GGj(Ej-1, Fj-1, Gj-1)SS1j+Qj-1,
Dj←Cj-1,
Cj←Bj-1＜ ＜ ＜ 9,
Bj←Aj-1,
Aj←TT1j,
Hj←Gj-1,
Gj←Fj-1＜ ＜ ＜ 19,
Fj←Ej-1,
Ej←P0(TT2j),
Xj←Ej-1+(Tj+1＜ ＜ ＜ (j+1)),
Yj←Cj-1+W′j+1,
Zj←Gj-1+Wj+1,
Wherein, X-1=E-1+(T0＜ ＜ ＜ j), Y-1=D-1+W′0、Z-1=H-1+W0, Aj-1, Bj-1, Cj-1, Dj-1, Ej- 1st, Fj-1, Gj-1, Hj-1 are -1 iterative value of jth of relevant variable word；Xj-1, Yj-1, Z j-1 be respectively the jth of X, Y and Z- 1 iterative value, FFj(Aj-1, Bj-1, Cj-1) and GGj(Ej-1, Fj-1, Gj-1) Boolean function is,
P0(TT2j) be Permutation function,＜ ＜ ＜ 12, ＜ ＜ ＜ j, ＜ ＜ ＜ 7, ＜ ＜ ＜ 15, ＜ ＜ ＜ 9, ＜ ＜ ＜ 19 are respectively ring shift left 12, j, 7,15,9,19 bit arithmeticsIt is 32 ratios Special XOR, ∧ be 32 bits and computing, ∨ be 32 bits or computing,It is 32 bit inverses；
Judging unit 606, for judging whether j is equal to 63；
If j is equal to 63, export iteration j value SS1j, SS2j of each variable word A, B, C, D, E, F, G, H, TT1j, TT2j、Xj、Yj、Zj、Aj、Bj、Cj、Dj、Ej、Fj、Gj、Hj；
If values of the j less than 63, j increases by 1 and then performs step S3.
First determining unit 602 also includes：
4th determination subelement 6021, for being grouped B according to preset message(i)Determine parameter N.
The device for reducing operand in SM3 cryptographic Hash algorithms also includes：
Computing unit 607, for using the sequencing of Aj, Bj, Cj, Dj, Ej, Fj, Gj, Hj as bit from high to low The variable that obtains of combination that puts in order carry out XOR with the ith iteration value of compression function V, obtain compression function V's I+1 time iterative value V(i+1)；
Second judging unit 608, for judging whether i is equal to N-1；
If i is equal to N-1, V is exported(N)；
If i is less than N-1, the value of i is added 1 and step S1 is performed.
It is apparent to those skilled in the art that, for convenience and simplicity of description, the system of foregoing description, The specific work process of device and unit, may be referred to the corresponding process in preceding method embodiment, will not be repeated here.
In several embodiments provided herein, it should be understood that disclosed system, apparatus and method can be with Realize by another way.For example, device embodiment described above is only schematical, for example, the unit Divide, only a kind of division of logic function there can be other dividing mode when actually realizing, for example multiple units or component Can combine or be desirably integrated into another system, or some features can be ignored, or do not perform.It is another, it is shown or The coupling each other for discussing or direct-coupling or communication connection can be the indirect couplings of device or unit by some interfaces Close or communicate to connect, can be electrical, mechanical or other forms.
The unit that is illustrated as separating component can be or may not be it is physically separate, it is aobvious as unit The part for showing can be or may not be physical location, you can with positioned at a place, or can also be distributed to multiple On NE.Some or all of unit therein can be according to the actual needs selected to realize the mesh of this embodiment scheme 's.
In addition, during each functional unit in each embodiment of the invention can be integrated in a processing unit, it is also possible to It is that unit is individually physically present, it is also possible to which two or more units are integrated in a unit.Above-mentioned integrated list Unit can both be realized in the form of hardware, it would however also be possible to employ the form of SFU software functional unit is realized.
If the integrated unit is to realize in the form of SFU software functional unit and as independent production marketing or use When, can store in a computer read/write memory medium.Based on such understanding, technical scheme is substantially The part for being contributed to prior art in other words or all or part of the technical scheme can be in the form of software products Embody, the computer software product is stored in a storage medium, including some instructions are used to so that a computer Equipment (can be personal computer, server, or network equipment etc.) performs the complete of each embodiment methods described of the invention Portion or part steps.And foregoing storage medium includes：USB flash disk, mobile hard disk, read-only storage (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disc or CD etc. are various can store journey The medium of sequence code.
The above, the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although with reference to preceding Embodiment is stated to be described in detail the present invention, it will be understood by those within the art that：It still can be to preceding State the technical scheme described in each embodiment to modify, or equivalent is carried out to which part technical characteristic；And these Modification is replaced, and does not make the spirit and scope of the essence disengaging various embodiments of the present invention technical scheme of appropriate technical solution.

Claims (8)

1. in a kind of reduction SM3 cryptographic Hash algorithms operand method, it is characterised in that including：
S1, the extension of message word W that B (i), the first formula and the second formula determine 32 bit lengths is grouped according to preset message0- W67, W '0-W′63, first formula isDescribed Two formula areWherein i is the first iterations,It is permutation function；
S2, respectively by the initial value of variable word A, B, C, D, E, F, G, H, X, Y, Z be initialized as A-1, B-1, C-1, D-1, E-1, Secondary iteration number of times j is simultaneously initialized as 0 by F-1, G-1, H-1, X-1, Y-1, Z-1；
S3, according to the 3rd preset formulaDetermine the constant Tj of 32 bit lengths；
S4, first interative computation is carried out according to preset iterative formula, determines intermediate variable word SS1, SS2, TT1, TT2, X, Y, Z Iteration j value SS1j, SS2j, TT1j, TT2j, Xj, Yj, Zj, Aj, Bj, Cj with each variable word A, B, C, D, E, F, G, H, Dj、Ej、Fj、Gj、Hj；
The iterative formula is specifically included
SS1j←((Aj-1＜ ＜ ＜ 12)+Xj-1) ＜ ＜ ＜ 7,
S S 2 j &RightArrow; S S 1 j &CirclePlus; ( A j - 1 < < < 12 ) ,
TT1j←FFj(Aj-1, Bj-1, Cj-1)+SS2j+Pj-1,
TT2j←GGj(Ej-1, Fj-1, Gj-1)+SS1j+Qj-1,
Dj←Cj-1,
Cj←Bj-1＜ ＜ ＜ 9,
Bj←Aj-1, Aj←TT1j,
Hj←Gj-1,
Gj←Fj-1＜ ＜ ＜ 19,
Fj←Ej-1,
Ej←P0(TT2j),
Xj←Ej-1+(Tj+1＜ ＜ ＜ (j+1)),
Yj←Cj-1+W′j+1,
Zj←Gj-1+Wj+1,
Wherein, X-1=E-1+(T0＜ ＜ ＜ j), Y-1=D-1+W′0、Z-1=H-1+W0, Aj-1, Bj-1, Cj-1, Dj-1, Ej-1, Fj-1, Gj-1, Hj-1 are -1 iterative value of jth of relevant variable word；Xj-1, Yj-1, Zj-1 are respectively the jth -1 time of X, Y and Z Iterative value, FFj(Aj-1, Bj-1, Cj-1) and GGj(Ej-1, Fj-1, Gj-1) Boolean function is,
P0(TT2j) it is displacement Function,＜ ＜ ＜ 12, ＜ ＜ ＜ j, ＜ ＜ ＜ 7th, ＜ ＜ ＜ 15, ＜ ＜ ＜ 9, ＜ ＜ ＜ 19 are respectively ring shift left 12, j, 7,15,9,19 bit arithmetics,For 32 than special Or computing, ∧ be 32 bits and computing, ∨ be 32 bits or computing,It is 32 bit inverses；
S5, judges whether j is equal to 63；
If j is equal to 63, export iteration j value SS1j, SS2j of each variable word A, B, C, D, E, F, G, H, TT1j, TT2j, Xj、Yj、Zj、Aj、Bj、Cj、Dj、Ej、Fj、Gj、Hj；
If values of the j less than 63, j increases by 1 and then performs step S3.
2. in reduction SM3 cryptographic Hash algorithms according to claim 1 operand method, it is characterised in that in step Also include before S1：
S0, is initialized as the initial value of the first iterations i 0 and initializes corresponding with the first iterations i The 0th iterative value V (0) of compression function V.
3. in reduction SM3 cryptographic Hash algorithms according to claim 2 operand method, it is characterised in that step S1 Also include：
B (i) is grouped according to preset message and determines parameter N.
4. in reduction SM3 cryptographic Hash algorithms according to claim 3 operand method, it is characterised in that in step Also include after S5：
S6, using the sequencing of Aj, Bj, Cj, Dj, Ej, Fj, Gj, Hj as bit putting in order and combine from high to low To variable carry out XOR with the ith iteration value of the compression function V, obtain the i+1 time of the compression function V repeatedly Generation value V(i+1)；
S7, judges whether i is equal to N-1；
If i is equal to N-1, V is exported(N)；
If i is less than N-1, the value of i is added 1 and step S1 is performed.
5. in a kind of reduction SM3 cryptographic Hash algorithms operand device, it is characterised in that including：
First determining unit, 32 bit lengths are determined for being grouped B (i), the first formula and the second formula according to preset message Extension of message word W0-W67, W '0-W′63, first formula is Second formula isWherein i is the first iterations,It is displacement Function；
First initialization unit, for respectively by the initial value of variable word A, B, C, D, E, F, G, H, X, Y, Z be initialized as A-1, Secondary iteration number of times j is simultaneously initialized as 0 by B-1, C-1, D-1, E-1, F-1, G-1, H-1, X-1, Y-1, Z-1；
Second determining unit, for according to the 3rd preset formulaDetermine 32 bit lengths Constant Tj；
3rd determining unit, for carrying out first interative computation according to preset iterative formula, determine intermediate variable word SS1, Iteration j value SS1j, SS2j of SS2, TT1, TT2, X, Y, Z and each variable word A, B, C, D, E, F, G, H, TT1j, TT2j, Xj、Yj、Zj、Aj、Bj、Cj、Dj、Ej、Fj、Gj、Hj；
The iterative formula is specifically included
SS1j←((Aj-1＜ ＜ ＜ 12)+Xj-1) ＜ ＜ ＜ 7,
S S 2 j &RightArrow; S S 1 j &CirclePlus; ( A j - 1 < < < 12 ) ,
TT1j←FFj(Aj-1, Bj-1, Cj-1)+SS2j+Pj-1,
TT2j←GGj(Ej-1, Fj-1, Gj-1)+SS1j+Qj-1,
Dj←Cj-1,
Cj←Bj-1＜ ＜ ＜ 9,
Bj←Aj-1,
Aj←TT1j,
Hj←Gj-1,
Gj←Fj-1＜ ＜ ＜ 19,
Ej←Ej-1,
Ej←P0(TT2j),
Xj←Ej-1+(Tj+1＜ ＜ ＜ (j+1)),
Yj←Cj-1+W′j+1,
Zj←Gj-1+Wj+1,
Wherein, X-1=E-1+(T0＜ ＜ ＜ j), Y-1=D-1+W′0、Z-1=H-1+W0, Aj-1, Bj-1, Cj-1, Dj-1, Ej-1, Fj-1, Gj-1, Hj-1 are -1 iterative value of jth of relevant variable word；Xj-1, Yj-1, Zj-1 are respectively the jth -1 time of X, Y and Z Iterative value, FFj(Aj-1, Bj-1, Cj-1) and GGj(Ej-1, Fj-1, Gj-1) Boolean function is,
P0(TT2j) it is displacement Function,＜ ＜ ＜ 12, ＜ ＜ ＜ j, ＜ ＜ ＜ 7th, ＜ ＜ ＜ 15, ＜ ＜ ＜ 9, ＜ ＜ ＜ 19 are respectively ring shift left 12, j, 7,15,9,19 bit arithmetics,For 32 than special Or computing, ∧ be 32 bits and computing, ∨ be 32 bits or computing,It is 32 bit inverses；
Judging unit, for judging whether j is equal to 63；
If j is equal to 63, export iteration j value SS1j, SS2j of each variable word A, B, C, D, E, F, G, H, TT1j, TT2j, Xj、Yj、Zj、Aj、Bj、Cj、Dj、Ej、Fj、Gj、Hj；
If values of the j less than 63, j increases by 1 and then performs step S3.
6. in reduction SM3 cryptographic Hash algorithms according to claim 5 operand device, it is characterised in that also include：
Second initialization unit, for the initial value of the first iterations i being initialized as into 0 and being initialized and described first The 0th iterative value V (0) of the corresponding compression function V of iterations i.
7. in reduction SM3 cryptographic Hash algorithms according to claim 6 operand device, it is characterised in that described One determining unit also includes：
4th determination subelement, parameter N is determined for being grouped B (i) according to preset message.
8. in reduction SM3 cryptographic Hash algorithms according to claim 7 operand device, it is characterised in that also include：
Computing unit, for the arrangement using the sequencing of Aj, Bj, Cj, Dj, Ej, Fj, Gj, Hj as bit from high to low The variable that sequential combination is obtained carries out XOR with the ith iteration value of the compression function V, obtains the compression function V I+1 time iterative value V(i+1)；
Second judging unit, for judging whether i is equal to N-1；
If i is equal to N-1, V is exported(N)；
If i is less than N-1, the value of i is added 1 and step S1 is performed.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107579811A (en) * 2017-07-28 2018-01-12 广州星海集成电路基地有限公司 A kind of hardware optimization method based on SM3 cryptographic Hash algorithms
CN109547192A (en) * 2018-11-08 2019-03-29 北京大学 The parallelization optimization method of SM3 cryptographic Hash algorithm
CN112202546A (en) * 2020-09-29 2021-01-08 山东华翼微电子技术股份有限公司 SM3 cryptographic hash algorithm message expansion serial optimization system and method
CN113741972A (en) * 2021-08-20 2021-12-03 深圳市风云实业有限公司 Parallel processing method of SM3 algorithm and electronic equipment

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107579811A (en) * 2017-07-28 2018-01-12 广州星海集成电路基地有限公司 A kind of hardware optimization method based on SM3 cryptographic Hash algorithms
CN109547192A (en) * 2018-11-08 2019-03-29 北京大学 The parallelization optimization method of SM3 cryptographic Hash algorithm
CN109547192B (en) * 2018-11-08 2020-11-03 北京大学 Parallel optimization method of SM3 cryptographic hash algorithm
CN112202546A (en) * 2020-09-29 2021-01-08 山东华翼微电子技术股份有限公司 SM3 cryptographic hash algorithm message expansion serial optimization system and method
CN112202546B (en) * 2020-09-29 2023-06-23 山东华翼微电子技术股份有限公司 SM3 cipher hash algorithm message expansion serial optimization system and method
CN113741972A (en) * 2021-08-20 2021-12-03 深圳市风云实业有限公司 Parallel processing method of SM3 algorithm and electronic equipment
CN113741972B (en) * 2021-08-20 2023-08-25 深圳市风云实业有限公司 SM3 algorithm parallel processing method and electronic equipment

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